TWM529263U - Semiconductor chip package structure - Google Patents

Abstract

A semiconductor chip package structure includes a semiconductor chip that having a plurality of pads on an active surface, one end of a plurality of metal wires is electrically connected with each pads, a cover which is formed by a plurality of edges and a top with an enclosed edge to encapsulate the semiconductor chip and the metal wire, a plurality of metal connection that is exposed out of the encapsulated body, and each metal connections is connected to another end of the metal wire, in which the portion edges of the cover includes a voids therein.

Description

Semiconductor chip package structure

The present invention relates to a package structure of a semiconductor wafer, and more particularly to a semiconductor chip package structure in which a package process can be completed without using a mold.

After the semiconductor device is functionally manufactured in the fab, it needs to be cut into a wafer, and then the wafer is electrically connected to the circuit board; then, the electrically connected wafer and the circuit board are placed in a mold, and then The resin is injected into the mold to completely cover the wafer and the circuit board; and then, after the resin is cured by baking, the packaging of the semiconductor element is completed.

In this packaging process, the mold is a consumable material, and needs to be separately manufactured according to different wafer sizes; since the cost of mold-making for mold opening is high, in the competition process of product manufacturing, the problem of cost increase is often caused. In addition, each chip must be electrically connected to a circuit board, so that the circuit board is also one of the manufacturing costs.

In order to further reduce the packaging cost of the semiconductor wafer, a simple package structure is required.

According to the above problems, the main object of the present invention is to provide a package structure of a semiconductor wafer, comprising: a semiconductor wafer having a plurality of pads disposed on an active surface thereof; and a plurality of metal wires; One end is electrically connected to the solder pad; the cover body is formed by a plurality of edges and a top of the closed edge for covering the semiconductor wafer and the metal wire; the sealing body is formed in the cover body to cover the semiconductor wafer and the metal wire And exposed to the bottom of the cover; a plurality of metal contacts exposing the surface of the sealant, and each metal contact is electrically connected to the other end of the plurality of metal wires; wherein, some edges of the cover are Configured with pores.

According to the above object, the package structure of the present invention can be effectively reduced in manufacturing cost without going through the process of the mold. In addition, the package structure of the present invention does not need to use a substrate, in addition to further reducing the manufacturing cost, the height of the package structure can also be reduced.

Another main object of the present invention is to provide a method for packaging a semiconductor wafer, comprising: providing a substrate, forming a plurality of regions on the substrate and arranging a plurality of identification marks on each of the regions; sequentially providing semiconductor wafers, each of the semiconductor wafers The active surface is provided with a plurality of pads, and the bottom of the opposite active surface is fixed on each area of the substrate, and is disposed between the identification marks of each area; the line is executed, and each piece is sequentially One end of the metal wire is electrically connected to each of the pads, and the other end of each metal wire is electrically connected to each of the identification marks to form a metal contact; the cover body is provided, and the plurality of metal wires are formed on one side. The accommodating space of the opening, each accommodating space of the cover covers a semiconductor wafer and the metal wire and is fixed to the substrate, and some edges of the cover are provided with apertures; and the injection molding is performed, the mold flow material is passed through the cover The pores on the edge of the body are injected into each of the accommodating spaces in the cover body to form a sealant, and each of the sealant covers the semiconductor wafer and the metal wire; performing peeling, The encapsulant and the substrate and separated from the cover, to expose the metal contact.

According to the above object, the packaging method of the present invention can effectively reduce the manufacturing cost without going through the process of the mold. In addition, the package structure of the present invention does not need to use a substrate, in addition to further reducing the manufacturing cost, the height of the package structure can also be reduced.

10‧‧‧Substrate

12‧‧‧ identification symbol

14‧‧‧ grain area

16‧‧‧ solder balls

20‧‧‧Semiconductor wafer

22‧‧‧ solder pads

30‧‧‧Metal wire

32‧‧‧Metal joints

40‧‧‧ cover

42‧‧‧ Cover area

44‧‧‧ cutting line

46‧‧‧ pores

50‧‧‧Adhesive layer

60‧‧‧metal layer

70‧‧‧ Sealant

Figure 1A is a schematic top view of the substrate of the present invention; Figure 1B is a schematic cross-sectional view of the substrate of the present invention; Figure 2 is a schematic view of the substrate of the present invention combined with a semiconductor wafer; Figure 3 is a schematic view of the semiconductor of the present invention; FIG. 4A is a schematic cross-sectional view of the cover body of the present invention; FIG. 4B is a schematic cross-sectional view of the cover body of the present invention; FIG. 5 is a schematic cross-sectional view of the cover body of the present invention covering the semiconductor wafer; 6A-6C is a schematic cross-sectional view of the injection molding process of the creation; FIG. 7 is a schematic diagram of the bottom surface after the creation is completed; FIG. 8A is a schematic diagram of the bottom surface of the packaging structure after the creation is completed; and FIG. 8B is the completion of the creation Schematic diagram of the package structure after cutting.

In order to clarify the purpose, technical features and advantages of the present invention, the author can understand and implement the present invention, and the technical features and implementation manners of the present invention are explained in the following description in conjunction with the drawings. The description of the preferred embodiments is further illustrated, but the following description of the embodiments is not intended to limit the present invention, and the drawings in the following description are intended to be illustrative of the features of the present invention.

First, please refer to Figure 1A, which is a schematic view of the substrate of this creation. As shown in Fig. 1A, the substrate 10 of the present invention is formed of a polymer material such as a resin or AB glue. bottom The material 10 can be divided into a plurality of die regions 14 on which semiconductor wafers are placed, each of which is distinguished by a dashed line. In addition, the substrate 10 of the present invention can be used with a certain hardness, or the substrate 10 can be subjected to a baking process first, and the substrate 10 also has a certain hardness. Next, a plurality of identification symbols 12 are formed at the peripheral position of the die region 14, each of the identification symbols 12 is a geometric shape, for example, a cross symbol, and each of the identification symbols 12 is made of a metal such as gold or copper or a copper alloy. Wait. Each of the identification symbols 12 may be formed by a semiconductor process by metal deposition or by electroplating or by screen printing. As shown in FIG. 1B, the creation is not limited. In addition, the size of each of the identification symbols of 12 inches can be adjusted according to the number of pads 22 of the semiconductor wafer 20 to be packaged, and the creation is not limited.

Next, please refer to FIG. 2, which is a schematic view of the substrate and the semiconductor wafer of the present invention. As shown in FIG. 2, the semiconductor wafer 20 (for example, DRAM or Flash memory) that has been cut is placed on the substrate 10 by placing each semiconductor wafer 20 one by one via a Handler. The region 14 is and the semiconductor wafer 20 is disposed between each of the identification symbols 12. In addition, the manner in which the semiconductor wafer 20 is placed on the die region 14 on the substrate 10 may be selected by using a resin, in particular a B-Stage resin or a resin having a heat conductive effect as the semiconductor wafer 20 and The adhesive layer of the substrate 10.

Next, please refer to Figure 3, which is a schematic view of the substrate and semiconductor wafer of the present invention. As shown in FIG. 3, the pads 22 on each of the semiconductor wafers 20 are connected to the identification marks 12 of the substrate 10 by a metal wire 30 using a wire bonding machine to form an electrical connection. In a preferred embodiment, when the wire bonding machine forms the metal contacts 32 on the identification symbol 12 in the reverse wire manner, the metal wires 30 are connected to the pads 22 on the semiconductor wafer 20; In another embodiment, the wire bonding may also first select the metal wire 30 and the semiconductor wafer 20 first. After the upper pads 22 are connected, the metal wires 30 are connected to the identification symbol 12, and the metal contacts 32 are formed at the identification symbol 12; wherein, in the present metal contact 32, the metal material is bonded by the wire bonding machine. The identification symbols 12 on a substrate 10 are integrally connected, and each of the metal contacts 32 may have a diameter of 0.01 mm to 0.5 mm. In addition, in the preferred embodiment of the present invention, an adhesive layer 50 may be formed on the die region 14 to secure the semiconductor wafer 20 by the adhesive layer 50; and the adhesive layer 50 may be a cured adhesive. For example, the B-Stage curing adhesive; in addition, the adhesive layer 50 may also be a highly thermally conductive resin, for example, a thermal conductive adhesive formed by using epoxy resin as a main material.

Next, please refer to FIG. 4A and FIG. 4B, which are schematic diagrams of the bottom surface and the cross section of the cover body of the present invention. As shown in FIG. 4A, the cover 40 can be formed by injection molding to form a plurality of cover regions 42 having accommodating spaces, wherein each cover region 42 is composed of a plurality of edges and a top portion enclosing a plurality of edges. form. The cover 40 can be precisely designed such that the accommodating space of each of the cover regions 42 can enclose the semiconductor wafers 20 which are arranged at intervals and have been electrically connected to the substrate 10; wherein the material of the cover 40 can be selected Use plastic or resin. In addition, in the design of the injection molded cover 40, the width of the four circumferences may be designed to be 0.5 to 1 mm, and in the embodiment of the present invention, the width of the four circumferences of the cover 40 is selected to be 0.5 mm; In the case where the cutting line width is about 1.2 mm, the width of the other middle frame other than the four circumferences is selected to be 2.2 mm; wherein the broken line in Fig. 4A is the position representing the cutting line 44. In addition, the cover 40 of the present invention further forms an aperture 46 in the middle of each frame or on the bottom of the frame, the width of which can be selected from 1 to 5 mm, which can be used as an inlet and outlet for subsequent injection molding. In the present embodiment, however, the width of the aperture 46 is selected to be 2.5 mm as shown in Fig. 4B.

Next, please refer to FIG. 5, which is a schematic cross-sectional view of the cover of the present invention covering the semiconductor wafer. As shown in FIG. 5, an adhesive layer may be formed on the bottom frame of the cover 40 (not shown in After the drawing, the adhesive layer 50 is fixed to the substrate 10. Therefore, when the plurality of molded cover regions 42 having the accommodating spaces are aligned, a plurality of spaced-apart semiconductor wafers 20 can be enclosed, as shown in FIG.

Next, please refer to FIG. 6A and FIG. 6B and FIG. 6C, which are schematic cross-sectional views of the injection molding process of the present invention. As shown in FIG. 6A, when each of the cover regions 42 having the accommodating space closes the semiconductor wafer 20 on each of the substrates 10 and is fixed to the substrate 10 by the adhesive layer 50, a note can be made. A molding process for molding, wherein the encapsulating material injected into the cover region 42 may be selected from an epoxy resin (Epoxy) or a low temperature adhesive. When the injected sealant material is injected into the accommodating space of the cover body region 42 by at least one aperture 46 in the injection molded cover 40, the sealant material is injected into the injection port as indicated by the arrow in FIG. 6A; The pressure is applied so that the injected sealant material is completely filled into the accommodating space of the cover body region 42; when the injected sealant material overflows at the other side of the cover body 40, it represents the sealant material. It has been completely filled into each of the cover regions 42; finally, after appropriate warming and baking, the sealant can be cured, as shown in Fig. 6B. According to the design of the present cover 40, in the packaging process of the semiconductor wafer 20, it is not necessary to use any mold, but the cover 40 is replaced, so that the cost of manufacturing the mold can be saved.

Next, please refer to FIG. 6C, which is a schematic cross-sectional view of the substrate from which the substrate is peeled off. As shown in FIG. 6C, when the sealing material has been completely filled into each of the cover regions 42, and after appropriate heating and baking, the sealing material can be cured to form in each of the cover regions 42. A sealant 70 encasing the semiconductor wafer 20. Next, the substrate 10 is peeled off from the edges of the sealant 70 and the cover 40, so that the bottom of the sealant 70 and the plurality of metal contacts 32 are exposed, as shown in FIG. 6C. In the preferred embodiment, after the process of the encapsulant 70 is completed, the encapsulant 70 can be subjected to a low temperature thermal process so that the substrate 10 can be softened to facilitate the peeling of the substrate 10 from the encapsulant 70. In this embodiment, This low temperature thermal process can be selected from 30 to 60 degrees. Obviously, the package structure of the present invention does not require the use of the substrate 10, in addition to further reducing the manufacturing cost, and also reducing the height of the package structure.

Please refer to Figure 7, which is a schematic diagram of the bottom surface after the creation of the creation. As shown in FIG. 7, when the substrate 10 and the sealing body 70 are peeled off, the bottom of the sealing body 70 and the plurality of metal contacts 32 are exposed. At this time, the bottom of the sealing body 70 and the plurality of metal contacts 32 are On the same plane. In the preferred embodiment of the present invention, the metal layer 60 may be formed on the die region 14 in a manner similar to the formation of the identification symbol 12. Thereafter, the adhesive layer 50 is formed on the metal layer 60 to be fixed to the semiconductor wafer 20 by the adhesive layer 50. The adhesive layer 50 may be a highly thermally conductive resin, for example, epoxy resin as a main material. The formed thermal paste. When the substrate 10 is peeled off from the sealant 70, the metal layer 60 is exposed as shown in FIG. By the design of the metal layer 60, the heat dissipation path of the semiconductor wafer 20 can be used; at this time, the bottom of the sealant 70 and the plurality of metal contacts 32, that is, the metal layer 60, are on the same plane.

Please refer to FIG. 8A and FIG. 8B, which are schematic diagrams and cross-sectional views of the bottom surface of the package structure after the creation of the cut. As shown in FIG. 8A, when the substrate 10 and the encapsulant 70 are peeled off, the bottom of the encapsulant 70, the plurality of metal contacts 32, and the metal layer 60 are exposed; and then, a whole package structure is exposed. After a solder paste is formed on each of the metal contacts 32, after a thermal process, a solder ball 16 is formed on each of the metal contacts 32, so that the solder balls 16 protrude from the sealant. 70 bottom.

Finally, after cutting along the dicing line via the laser, the encapsulation of the semiconductor wafer 20 can be completed, as shown in FIG. 8B. Obviously, the present invention can reduce the manufacturing cost by further injecting the molded cover 40 as a mold, which can save the mold required for the conventional injection molding.

The present application then provides a method of packaging a semiconductor wafer, including:

Step 1: providing a substrate 10, and forming a plurality of regions on the substrate 10 and each region is provided with a plurality of identification marks 12, wherein the substrate 10 is formed of a polymer material, such as an AB glue; The substrate 10 can be divided into a plurality of die regions 14 on which semiconductor wafers are placed. A plurality of identification symbols 12 are formed at a peripheral position of the crystal grain region 14. Each of the identification symbols 12 has a geometric shape, for example, a cross symbol, and each of the identification symbols 12 is made of a metal such as gold or copper or a copper alloy. Each of the identification symbols 12 may be formed by a semiconductor process by metal deposition or by electroplating or by screen printing. As shown in FIG. 1B, the creation is not limited.

Step 2: sequentially providing semiconductor wafers 20, a plurality of pads 22 disposed on the active surface of each semiconductor wafer 20, and fixing the bottom of the opposite active surface to each of the die regions 14 of the substrate, and configured Between the identification marks 12 of each area. In addition, the manner in which the semiconductor wafer 20 is placed on the die region 14 on the substrate 10 may be selected from the use of a resin, particularly a B-Stage resin, as the adhesion layer between the semiconductor wafer 20 and the substrate 10. In the preferred embodiment, the metal layer 60 can be formed on the die region 14 in a manner that can be accomplished simultaneously with the formation of the identification symbol 12. Thereafter, an adhesive layer 50 is formed over the metal layer 60 to be bonded to the semiconductor wafer 20 by the adhesive layer 50.

Step 3: performing wire bonding, electrically connecting one end of each metal wire 30 to each of the pads 22 in sequence, and electrically connecting the other end of each metal wire 30 to each of the identification marks 12, and forming The metal contact 32; in the metal contact 32 of the present invention, the metal material is integrally connected with the identification symbol 12 on each of the substrates 10 by a wire bonding machine, and the diameter of each metal contact 32 can be between 1 mm and 10 mm. .

Step 4: providing a cover body, the cover body 40 may be formed by injection molding to form a plurality of cover body regions 42 having an accommodating space, wherein each cover body region 42 has a plurality of edges and closed edges The top is formed. The cover 40 can be precisely designed such that the accommodating space of each of the cover regions 42 can enclose the semiconductor wafers 20 which are arranged at intervals and have been electrically connected to the substrate 10; wherein the material of the cover 40 can be selected Use plastic or resin. In addition, the cover 40 of the present invention is further provided with apertures 46 on some of the edges to serve as injection ports and outlets for the mold flow.

Step 5: performing injection molding by injecting the mold material into each of the accommodating spaces 42 in the cover 40 via at least one aperture 46 on the edge of the cover 40, and the sealing material injected into the cover region 42 can be selected. Epoxy or low temperature glue. When the injected sealant material is injected into the accommodating space of the cover body region 42 by at least one aperture 46 in the injection molded cover 40, the injection port is as indicated by the arrow in FIG. 6A; with appropriate pressure application, The injected sealant material can be completely filled into the accommodating space of the cover body region 42; when the injected sealant material overflows on the other side of the cover body 40, the sealant material is completely filled to Each cover area 42. At this time, the encapsulant 70 is formed to coat the semiconductor wafer 20 and the metal wires 30.

Step 6: Performing heating, the sealing body 70 may be subjected to a low-temperature hot process to make the substrate 10 soften, and the substrate 10 and the sealing body 70 are conveniently peeled off. In the embodiment, the low temperature thermal process can be selected from 30 to 60 degrees. It is to be noted here that this heating step is a selection step, and it is possible to decide whether or not to perform this step depending on the material of the substrate 10 to be used.

Step 6: Performing the peeling is to separate the substrate from the sealant 70 and the cover 40. When the substrate 10 is peeled off from the sealant 70, the bottom of the sealant 70 and the plurality of metal contacts 32 are exposed. When the metal layer 60 is disposed on the die region 14, the metal layer 60 is exposed when the substrate 10 is peeled off from the sealant 70.

Step 7: forming a solder ball, forming a solder paste on each metal contact 32 exposed in a whole package structure, and then performing a hot process, then connecting each metal A solder ball is formed on the dot 32 such that the solder ball 16 protrudes from the bottom of the sealant 70. It should be noted that the step of forming a solder ball is a selection step, and whether the package structure used is a planar grid array (LGA) or a ball grid array (BGA) to determine whether or not the package structure is used. This step is performed; this step is performed when the package structure is to form a BGA package structure.

Step 8: Performing the cutting, after cutting along the cutting line 44 via the laser, the packaging of the semiconductor wafer 20 can be completed, as shown in FIG. 8A or FIG. 8B.

Although the present invention is disclosed above in the preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art, for example, the semiconductor wafer 20 is not limited to a memory, as long as it is formed by a semiconductor process. The grain is the subject of the creation of the package; therefore, the scope of patent protection of this creation shall be subject to the scope of the patent application attached to this specification without departing from the spirit and scope of the creation. The definition is subject to change.

20‧‧‧Semiconductor wafer

22‧‧‧ solder pads

30‧‧‧Metal wire

32‧‧‧Metal joints

40‧‧‧ cover

50‧‧‧Adhesive layer

70‧‧‧ Sealant

Claims (6)

A semiconductor wafer package structure comprising: a semiconductor wafer having a plurality of pads disposed on an active surface thereof; a plurality of metal wires having one end electrically connected to the pads; a cover body having a plurality of edges and a closed a top portion of the edge is formed to cover the semiconductor wafer and the metal wires; a gel is formed in the cover, covering the semiconductor wafer and the metal wires, and is exposed to the cover a bottom portion; and a plurality of metal contacts exposed to the outside of the sealant, and each of the metal contacts is electrically connected to the other end of the plurality of metal wires; wherein some edges of the cover are disposed Porosity. The package structure of a semiconductor wafer according to claim 1, wherein the cover has a rectangular structure. The package structure of a semiconductor wafer according to claim 1, wherein the metal wires are formed in an inverse wire bonding manner. The package structure of the semiconductor wafer according to the first aspect of the invention, wherein the metal contacts exposed to the outside of the sealant are a Land Grid Array (LGA) structure. The package structure of the semiconductor wafer according to claim 1, wherein the metal contacts exposed to the outside of the sealant are a Ball Grid Array (BGA) structure. The package structure of the semiconductor wafer according to claim 1, wherein the cover is made of a polymer material.