CN106486417A - The method of lifting crystal edge yield - Google Patents
The method of lifting crystal edge yield Download PDFInfo
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- CN106486417A CN106486417A CN201510557758.XA CN201510557758A CN106486417A CN 106486417 A CN106486417 A CN 106486417A CN 201510557758 A CN201510557758 A CN 201510557758A CN 106486417 A CN106486417 A CN 106486417A
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- Prior art keywords
- side washing
- inter
- photoresist layer
- level dielectric
- wafer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
Abstract
The present invention relates to a kind of method of lifting crystal edge yield, comprises the following steps：Wafer substrate is provided；In wafer substrate, gluing forms the first photoresist layer, and carries out active area side washing；The position not covered by the first photoresist layer in wafer substrate forms silicon oxide isolation structure；Active area is formed in wafer substrate；Inter-level dielectric is formed on the active area；On inter-level dielectric, gluing forms the second photoresist layer, and carries out contact hole side washing；Under the sheltering of the second photoresist layer, etching inter-level dielectric forms contact hole；Metal is filled to contact in the hole by depositing operation；Inter-level dielectric to being filled with metal carries out planarization process；Side washing region in active area side washing step at least extends to deposition region edge from crystal round fringes.The present invention can lift crystal edge yield by setting suitable side washing region without the need for extra cost.
Description
Technical field
The present invention relates to integrated circuit (IC) manufacture field, brilliant in more particularly to a kind of lifting side washing technique
The method of side yield.
Background technology
During the gluing of wafer, the effect of centrifugal force can cause photoresist accumulation to be formed at the edge of wafer
Residual projection, and then cause the pollution of subsequent technique, reduce crystal edge yield.Wafer is accumulated in order to remove
The photoetching glue residua at edge, generally carries out side washing (Edge Bean Removal, EBR) after coating technique,
To remove the photoetching glue residua of crystal round fringes.
The lifting of crystal edge yield is most important for 8 cun of factories and below 0.18um technique, and traditional side washing
, during follow-up contact metal grinding technics, lapping liquid can be by the contact hole of unfilled metal for technique
Corrosion silicon substrate, as shown in figures 1 and 3, causes substrate damage, causes defect exception, affects yield.
Content of the invention
Based on this, it is necessary to for the defect abnormal problem that substrate damage causes is reduced, a kind of lifting is provided brilliant
The method of side yield.
A kind of method of lifting crystal edge yield, comprises the following steps：Wafer substrate is provided；It is lithographically formed first
Photoresist layer；In the wafer substrate, gluing forms the first photoresist layer, and carries out active area side washing；?
The position not covered by the first photoresist layer in the wafer substrate forms silicon oxide isolation structure；In the crystalline substance
Active area is formed on circle substrate；Inter-level dielectric is formed on the active area；It is lithographically formed the second photoresist layer；
On the inter-level dielectric, gluing forms the second photoresist layer, and carries out contact hole side washing；In second light
The inter-level dielectric is etched under the sheltering of photoresist layer forms contact hole；By depositing operation to the contact in the hole
Filling metal；Inter-level dielectric to being filled with metal carries out planarization process；In the active area side washing step
Side washing region at least extend to from crystal round fringes and described metal filled to the contact in the hole by depositing operation
The step of in deposition region edge.
Wherein in one embodiment, described by depositing operation to described contact in the hole fill metal the step of
Be using chemical vapor deposition method deposits tungsten.
Wherein in one embodiment, the side washing region in the contact hole side washing step is at least from crystal round fringes
Extend to described by depositing operation to the contact in the hole fill metal the step of in deposition region edge 4,
According to claim 1 lifting crystal edge yield method, it is characterised in that the active area side washing and
The two side washing steps of contact hole side washing are removed unnecessary photoresist by organic solvent.
Wherein in one embodiment, the inter-level dielectric to being filled with metal carries out the step of planarization process
Suddenly, including being ground using alkaline slurries.
Wherein in one embodiment, the inter-level dielectric to being filled with metal carries out the step of planarization process
After rapid, also include the step of forming metal connecting line.
Wherein in one embodiment, described offer wafer substrate the step of in, wafer substrate be silicon substrate.
The method of above-mentioned lifting crystal edge yield, in unfilled contact hole silicon oxide isolation structure formed below,
Never the lapping liquid that the contact hole being filled with metal is penetrated down into stopped because of oxidized silicon seperate structure, therefore not
Corrosion damage can be caused to wafer substrate.The method is become without the need for extra by setting suitable side washing region
Originally crystal edge yield can be lifted.
Description of the drawings
Fig. 1 is the schematic diagram of traditional handicraft crystal round fringes after contact metal grinding；
Fig. 2 is wafer substrate axle center and edge schematic diagram；
Fig. 3 causes the abnormal Electronic Speculum schematic diagram of defect for traditional handicraft grinding corrosion silicon substrate；
Fig. 4 is the flow chart of the method for present invention lifting crystal edge yield；
Fig. 5 is the schematic diagram of crystal edge after the completion of step S130 in embodiment 1；
Fig. 6 is the schematic diagram of crystal edge after the completion of step S190 in embodiment 1；
Fig. 7 is the schematic diagram of crystal edge after formation metal connecting line in embodiment 2.
Specific embodiment
For the ease of understanding the present invention, the present invention is described more fully below with reference to relevant drawings.
The first-selected embodiment of the present invention is given in accompanying drawing.But, the present invention can come real in many different forms
Existing, however it is not limited to embodiment described herein.On the contrary, the purpose for providing these embodiments is made to this
Disclosure of the invention content is more thorough comprehensive.
Unless otherwise defined, all of technology used herein and scientific terminology and the technology for belonging to the present invention
The implication that the technical staff in field is generally understood that is identical.The art for being used in the description of the invention herein
Language is intended merely to describe the purpose of specific embodiment, it is not intended that in the restriction present invention.Used herein
Term " and/or " include the arbitrary and all of combination of one or more related Listed Items.
As described in the background art, as the filling of contact hole 10 is formed in 20 metal deposition process of tungsten plug,
Metal deposit regions 300 will not cover full wafer wafer substrate 100, as shown in figure 1, traditional side washing technique exists
In follow-up 20 process of lapping of tungsten plug, lapping liquid (such as alkaline solution) can be by unfilled metal (figure
Oval circle 500 in 1) the corrosion active area of contact hole 10, substrate damage 510 is formed, as Fig. 3 electron microscope institute
Show, cause defect exception, affect yield.
Fig. 2 is the schematic diagram at wafer substrate axle center 110 and edge 120, in this specification side washing technique with
And the reference direction of depositing operation is the direction that wafer substrate edge 120 points to wafer substrate axle center 110, i.e.,
The direction of arrow in Fig. 2.
Fig. 4 is the flow chart of the method for present invention lifting crystal edge yield, enters below by way of two embodiments respectively
Row explanation.
Embodiment 1：
S110, provides wafer substrate 100.
Specifically chosen what kind of substrate can be decided in its sole discretion according to product demand, material including substrate,
Crystal orientation, doping type etc., are not limited herein.Silicon substrate commonly employed in the art.
S120, is lithographically formed the first photoresist layer.
Please also refer to Fig. 5, in wafer substrate 100, gluing forms the first photoresist layer 210, and is had
Source region side washing (removing the photoetching glue residua of crystal round fringes using organic solvent) and photoetching.In the present embodiment,
Side washing size a1 that points to from wafer substrate edge 120 on 110 direction of wafer substrate axle center is sufficiently large, makes light
Photoresist is washed off the deposition region 300 that region at least extends to follow-up metal deposition process from crystal round fringes.
S130, the position not covered by the first photoresist layer in wafer substrate form silicon oxide isolation structure.
Refer to Fig. 5, in wafer substrate 100 not by the first photoresist layer cover position formed silica every
From structure 200.It should be understood that the first photoresist layer 210 is not necessarily directly as silicon oxide isolation structure
200 mask layer, for example, first deposit can form silicon nitride layer in wafer substrate 100, then pass through the first light
210 photoetching of photoresist layer and etch the silicon nitride layer and form suitable pattern, then using the silicon nitride layer as covering firmly
Film layer, forms silicon oxide isolation structure 200.
S140, forms active area in wafer substrate.
After forming silicon oxide isolation structure 200, the structure of active area next can be formed.Can adopt herein
Conventional process, therefore do not repeat.
S150, forms inter-level dielectric on the active area.
Equally inter-level dielectric (ILD) 220 can be formed using conventional process.
S160, is lithographically formed the second photoresist layer.
On inter-level dielectric 220, gluing forms the second photoresist layer, and carries out contact hole side washing and photoetching.
S170, under the sheltering of the second photoresist layer, etching inter-level dielectric forms contact hole.
The photoresist at wafer substrate edge 120 is removed because of side washing, therefore the ILD of lower section exposes, so as to
Be etched in this step removal.
S180, fills metal by depositing operation to contact in the hole.
In the present embodiment, it is to be in filling tungsten, i.e. this step into contact hole (contact) 10 with chemistry
Vapour deposition (CVD) process deposits tungsten, forms tungsten plug 20.Due to the scope (i.e. deposition region 300) for depositing
Wafer substrate edge 120 will not be covered, therefore the contact hole 10 outside deposition region 300 will not be filled by tungsten,
So as to form cavity, as shown in Figure 6.
S190, the inter-level dielectric to being filled with metal carry out planarization process.
It is ground by abrasive disk.In the present embodiment, lapping liquid is alkaline solution.
The method of above-mentioned lifting crystal edge yield, unfilled 10 lower section of contact hole is silicon oxide isolation structure 200,
The contact hole that lapping liquid is never filled with metal in step S190 is penetrated down into, but because of oxidized silicon seperate structure
200 are stopped, therefore will not cause corrosion damage to wafer substrate 100.
It should be understood that metal connecting line 310 is formed by photoetching and etching in crystal column surface after step S190,
Metal connecting line is electrically connected to tungsten plug 20 active area of lower section.
Embodiment 2：
Embodiment 1 be by protecting substrate, embodiment in the oxide layer formed below of unfilled contact hole 10
2 pass through to remove unnecessary ILD so that will not form contact hole outside deposition region 300, prevent grinding
Liquid corrodes the hidden danger of substrate by contact hole 10.
Therefore the differring primarily in that of embodiment 2 and embodiment 1, by rationally arranging from wafer in step S160
Edges of substrate 120 points to side washing size a2 on 110 direction of wafer substrate axle center so that photoresist is washed off
Region at least extends to deposition region 300 from crystal round fringes.Consequently, it is possible in step S170, unnecessary
Inter-level dielectric 220 will be etched away, and directly avoid the generation of the contact hole 10 for being not filled by metal.As schemed
Shown in 7.
Same as Example 1, also include to form metal connecting line 310 by photoetching and etching after step S190
The step of.
Embodiment described above only have expressed the several embodiments of the present invention, and its description is more concrete and detailed,
But therefore can not be construed as limiting the scope of the patent.It should be pointed out that for this area
For those of ordinary skill, without departing from the inventive concept of the premise, some deformation can also be made and is changed
Enter, these belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be with appended power
Profit requires to be defined.
Claims (7)
1. a kind of method of lifting crystal edge yield, comprises the following steps：
Wafer substrate is provided；
It is lithographically formed the first photoresist layer；In the wafer substrate, gluing forms the first photoresist layer, goes forward side by side
Row active area side washing；
The position not covered by the first photoresist layer in the wafer substrate forms silicon oxide isolation structure；
Active area is formed in the wafer substrate；
Inter-level dielectric is formed on the active area；
It is lithographically formed the second photoresist layer；On the inter-level dielectric, gluing forms the second photoresist layer, goes forward side by side
Row contact hole side washing；
The inter-level dielectric is etched under the sheltering of second photoresist layer forms contact hole；
Metal is filled to the contact in the hole by depositing operation；
Inter-level dielectric to being filled with metal carries out planarization process；
Side washing region in the active area side washing step at least extends to described by depositing work from crystal round fringes
Deposition region edge of the skill in the step of the contact in the hole filling metal.
2. the method for lifting crystal edge yield according to claim 1, it is characterised in that described by heavy
Product technique to described contact in the hole fill metal the step of be using chemical vapor deposition method deposits tungsten.
3. according to claim 1 lifting crystal edge yield method, it is characterised in that the contact hole
Side washing region in side washing step at least extends to described by depositing operation to the contact hole from crystal round fringes
Deposition region edge in the step of interior filling metal.
4. according to claim 1 lifting crystal edge yield method, it is characterised in that the active area
Side washing and the two side washing steps of contact hole side washing are removed unnecessary photoresist by organic solvent.
5. according to claim 1 lifting crystal edge yield method, it is characterised in that described to filling
The step of inter-level dielectric of metal carries out planarization process, including being ground using alkaline slurries.
6. according to claim 1 lifting crystal edge yield method, it is characterised in that described to filling
After the step of inter-level dielectric of metal carries out planarization process, also include the step of forming metal connecting line.
7. the method for lifting crystal edge yield according to claim 1, it is characterised in that the offer is brilliant
In the step of circle substrate, wafer substrate is silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510557758.XA CN106486417B (en) | 2015-09-02 | 2015-09-02 | The method for promoting crystal edge yield |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510557758.XA CN106486417B (en) | 2015-09-02 | 2015-09-02 | The method for promoting crystal edge yield |
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| CN106486417A true CN106486417A (en) | 2017-03-08 |
| CN106486417B CN106486417B (en) | 2019-07-23 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112086352A (en) * | 2020-08-06 | 2020-12-15 | 北京烁科精微电子装备有限公司 | Process for growing oxidation isolation layer by using Locos and preparing IGBT chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040035450A1 (en) * | 2000-12-15 | 2004-02-26 | Ko Se-Jong | Apparatus for cleaning the edges of wafers |
| CN1505111A (en) * | 2002-11-28 | 2004-06-16 | 华邦电子股份有限公司 | Process for removing ditch and protrusion |
| CN101206181A (en) * | 2006-12-22 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Device and method for testing edge-washing effect of crystal round fringes |
-
2015
- 2015-09-02 CN CN201510557758.XA patent/CN106486417B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040035450A1 (en) * | 2000-12-15 | 2004-02-26 | Ko Se-Jong | Apparatus for cleaning the edges of wafers |
| CN1505111A (en) * | 2002-11-28 | 2004-06-16 | 华邦电子股份有限公司 | Process for removing ditch and protrusion |
| CN101206181A (en) * | 2006-12-22 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Device and method for testing edge-washing effect of crystal round fringes |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112086352A (en) * | 2020-08-06 | 2020-12-15 | 北京烁科精微电子装备有限公司 | Process for growing oxidation isolation layer by using Locos and preparing IGBT chip |
| CN112086352B (en) * | 2020-08-06 | 2024-02-20 | 北京晶亦精微科技股份有限公司 | Technology for growing oxidation isolation layer and preparing IGBT chip by using Locos |
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| CN106486417B (en) | 2019-07-23 |
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