CN106463596B - The manufacturing process of luminescent device - Google Patents
The manufacturing process of luminescent device Download PDFInfo
- Publication number
- CN106463596B CN106463596B CN201580024877.7A CN201580024877A CN106463596B CN 106463596 B CN106463596 B CN 106463596B CN 201580024877 A CN201580024877 A CN 201580024877A CN 106463596 B CN106463596 B CN 106463596B
- Authority
- CN
- China
- Prior art keywords
- layer
- metal contact
- contact layer
- metal
- method described
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/647—Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0091—Scattering means in or on the semiconductor body or semiconductor body package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
Each embodiment provides a kind of method for forming luminescent device.The method can further comprise setting multilayered structure, wherein the multilayered structure successively includes the second semiconductor layer of substrate, the first semiconductor layer of the first conduction type, active layer and the second conduction type, and including at least one metal contact layer, at least one described metal contact layer is formed at least one of the first semiconductor layer and the second semiconductor layer.The method further includes forming at least one groove above at least one described metal contact layer, and at least one metal support is formed in at least one trench.
Description
Cross reference to related applications
This application claims the priority for the U.S. Provisional Application No. 61/996,662 that on May 14th, 2014 submits, for institute
Purposefully, entire contents of the provisional application is herein incorporated by reference.
Technical field
The method that embodiment relates generally to luminescent device and forms luminescent device.
Background technique
Light emitting diode (LED), for example, GaN (nitridation is sowed) base LED is considered as selecting for the light source of next-generation solid-state lighting
It selects, and comes in the past few decades, the research and development in the field has been achieved with huge progress.High brightness GaN LED is
Backlight, traffic sign and full-color display applied to various uses, such as LCD.
Currently, GaN LED initially enters general illumination market.In order to accelerate to penetrate into general illumination market, need further
Improve the performance of GaN LED.For example, power conversion efficiency of the GaN LED under high power operation must be more excellent, such as higher than
50%, to make them replace current fluorescent lamp (it has about 20% power conversion efficiency), preferably cared for have
Object is tested and cost-benefit benefit.
For further improving the efficiency of the LED currently based on Sapphire Substrate, there are technical restrictions.Due to electrical insulating property
Matter and undesirable thermal conductivity (W/mK), based on sapphire LED often suffer from there are undesirable light extraction, it is undesirable heat dissipation,
Big efficiency under high junction temperature (> 100 DEG C) and high power operation declines (efficiency droop) (> 40%).These disadvantages
Serious bottleneck is provided with further to improve the LED efficiency under the conditions of high power operation.
Therefore, it has been proposed that the concept of inversion type LED (Inverted LED) solves these problems.Inversion type
LED is the structure on metal support, wherein extracting light from the opposite side of electrode, this indicates the technology water of Modern LED technologies
Standard have the advantages that it is many incomparable, such as compare traditional transverse structure LED, with excellent heat transfer and light extraction.
These promising LED can have high efficiency and extremely long service life operating at higher current densities.It is inverted
The principle of formula LED is to remove Sapphire Substrate, and LED is attached to and is served as a contrast with the substitution of good electrical conduction rate and pyroconductivity
Bottom.Substitution substrate will act as conduction electric current electrode and effective heat dissipation path.It, can be to exposed unintentional after substrate removes
The surface (u-GaN) GaN of doping or surface GaN (n-GaN) of n-type doping are roughened or are patterned, to improve light extraction
Take efficiency.
However, the technology not can be realized simply directly, and key point is that substrate removes technique.It is blue precious removing
Before stone, should realize strong and conductive supporting layer first, so as to maintain self-supporting (free standing) LED layer and
Prevent any damage caused by during and after sapphire removes.The supporting layer can be formed by wafer bonding technique,
Wafer bonding technique, using the Au welding procedure of referred to as thermosonic flip chip bonding.
Fig. 1 shows the method that preparation has the LED 100 of inversion type structure.Work identical with lateral chip is used first
Skill prepares LED grain 110, for example including mesa etch, metal pad deposition, mirror surface contact layer deposition, crystal grain cutting etc..
LED grain 110 include the n-GaN layer, MQW (multiple quantum wells) layer and the p-GaN layer that sequentially form on a sapphire substrate and
The n pad and p pad (including transparent ohmic contact layer and reflecting mirror) formed on n-GaN layers and p-GaN layer respectively.It will deposition
There is SiO2The LED grain 110 of passivation layer is overturn, and uses the ultrasonic inversion type bonding technology of heat by p pad and n pad via weldering
Connect convex block 122 (for example, Au convex block) and metal contact layer 124 welding or be bonded to heat sink (submount) 120 (such as copper or
Silicon Wafer).After LED grain 110 is bonded to heat sink 120, it is Sapphire Substrate (may be patterned substrate) and right to remove
It is roughened.Unintentional doped layer between substrate and n-GaN layers or n-GaN layers can also be exposed and are roughened,
To improve light extraction efficiency.P pad and n pad are formed in the same side, so that light will not be by any pad and metal wire institute
Stop, shown in light emitting path as represented in figure 1.
However, since device to heat sink heat conduction path is by one or more soldering projections or Au stud (Au
The diameter of stud is about 50-200 μm) it completes, and the area of soldering projection or Au stud is much smaller than the area of entire device,
Therefore Au welding procedure provides small contact area to be used to radiate.In addition, Au welding and heat sink preparation significantly increase LED
Overall cost.In contrast, metal plating is a kind of inexpensive way for realizing the bonding support plate of inversion type LED.However, falling
The electrode for setting formula LED chip is on the same side, and they must be isolated to form final chip.In addition, right
For metal electroplating process, the part of plating in need must be conductive.This requirement is hindered metal plating skill
Art is applied in inversion type LED preparation process.
Summary of the invention
Each embodiment provides a kind of method for forming luminescent device.The method may include providing multilayered structure,
Described in multilayered structure successively include substrate, the first semiconductor layer of the first conduction type, active layer and the second conduction type
The second semiconductor layer, and including at least one metal contact layer, at least one described metal contact layer is in the first semiconductor
It is formed at least one in both layer and the second semiconductor layer.The method further includes at least one described metal
At least one groove is formed above contact layer, and forms at least one metal support in at least one trench.
Detailed description of the invention
In attached drawing, the same reference symbol in different attached drawings refers generally to same parts.Attached drawing is not necessarily drawn to scale,
And focus on illustrating the principle of the present invention.In the following description, each embodiment is described with reference to the following drawings, in which:
Fig. 1 shows the method that preparation has the LED of inversion type structure；
Fig. 2 shows according to various embodiments to form the method flow diagram of luminescent device；
Fig. 3 shows schematic diagram according to various embodiments, and the schematic shows the top view and section views of layer structure；
Fig. 4 shows schematic diagram according to various embodiments, and the schematic shows the mesa etch in inversion type technique
The top view and section view of layer structure later；
Fig. 5 shows schematic diagram, and the schematic shows the top view of the layer structure outline after etching deeply and sections
Figure；
Fig. 6 shows schematic diagram according to various embodiments, and the schematic shows the multilayers for being formed with metal contact layer
The top view and section view of the profile of structure；
Fig. 7 shows schematic diagram according to various embodiments, and the schematic shows the multilayers for being deposited with the first passivation layer
The top view and section view of structure；
Fig. 8 shows schematic diagram according to various embodiments, and the schematic shows the multilayered structures for being deposited with seed layer
Top view and section view；
Fig. 9 shows schematic diagram according to various embodiments, and the schematic shows be formed with the more of the second passivating structure
The top view and section view of layer structure；
Figure 10 shows schematic diagram according to various embodiments, and the schematic shows be formed with the support of at least one metal
The top view and section view of the multilayered structure of object；
Figure 11 shows schematic diagram according to various embodiments, the schematic shows by Sapphire Substrate from LED wafer
The top view and section view of the technique of removal；
Figure 12 shows schematic diagram, and the schematic shows the LED layer structure after removal substrate, which makes
Use netted island as supporter；
Figure 13 shows schematic diagram according to various embodiments, and the schematic shows roughening processes；
Figure 14 shows schematic diagram according to various embodiments, and the schematic shows the separation of LED grain；
Figure 15 shows schematic diagram according to various embodiments, and the schematic shows facing upward for the inversion type crystal grain in Figure 14
View, the inversion type crystal grain have the copper supporter for being attached to blue film；
Figure 16 shows schematic diagram according to various embodiments, and the schematic shows luminescent devices.
Specific embodiment
Described in detail below to refer to attached drawing, these Detailed description of the inventions show the detail and implementation that the present invention can be implemented
Example.These embodiments are sufficiently described in detail, so that those skilled in the art can implement the present invention.The present invention is not being departed from
In the case where range, other embodiments can be used, and structure and change in logic can be carried out.Each embodiment is not
It centainly excludes each other, because some embodiments can combine to form new implementation with one or more of the other embodiment
Example.
Each embodiment, which is provided using net metal electroplating technology, forms luminescent device (such as inversion type high power
LED method).Compared with traditional technology, each embodiment forms metal support (also referred to as net metal island), as with
The supporter of preparation process afterwards.When this method is applied to inversion type preparation, in the side of pattern technology and net metal island
It helps down, p and n-electrode supporter can be electroplated simultaneously.Compared with traditional inversion type technology, metal support and metal contact layer have greatly
Many contacts area will allow many heat dissipations.Therefore, each embodiment provides one kind and has more cost efficient and have
Very high potential improves the method for yield rate and efficiency.
It should be understood that term " on ", " top ", " transverse direction ", " top ", " bottom " ought be used in the following description
Whens equal, these terms are to use for convenience and help to understand relative position or direction, are not intended to limit any dress
It sets or the orientation of any part of structure or any device or structure.
Fig. 2 shows according to various embodiments to form method flow Figure 200 of luminescent device.
202, multilayered structure is set.The multilayered structure successively include substrate, the first conduction type the first semiconductor layer,
Second semiconductor layer of active layer and the second conduction type, and including the first semiconductor layer and the second semiconductor layer extremely
Few upper at least one metal contact layer formed.
204, at least one groove is formed above at least one metal contact layer.
206, at least one supporter is formed at least one groove.
According to various embodiments, multilayered structure is LED (light emitting diode) structure.First and second semiconductor layer and active
Layer is formed together LED structure together at least one metal contact layer.
According to various embodiments, the area of metal support is substantially near the metal contact layer face below metal support
Product.The area of metal support can refer to the bottom surface area of the metal support directly or indirectly contacted with metal contact layer.
The area of metal contact layer can refer to the top surface area of the metal contact layer directly or indirectly contacted with metal support.
In various embodiments, at least one groove is formed, is included in above multilayered structure and forms passivating structure.Passivation
Structure includes passivation part, limits at least one groove and/or connects adjacent groove.In the exemplary embodiment, two
Mutually passivation part can limit groove therebetween.In the exemplary embodiment, the connection of passivation part therebetween or isolation two can be passed through
Adjacent trenches.
In various embodiments, the method can further comprise cutting or be etched through one or more passivation parts with
Form at least one luminescent device crystal grain.
In various embodiments, passivation part is coplanar at least one metal support.As explanation, when overturning multilayer knot
When structure is so that substrate is in top, coplanar passivation part and at least one metal support are formed and used as substrate supports
Object.
In various embodiments, each passivation portion can have the width within the scope of 20 μm to 2mm.
In various embodiments, passivating structure is formed can include: photoresist layer is deposited on multilayered structure；And by photoetching
Glue-line exposure and imaging, so that removing the photoresist part at least one metal contact layer to form at least one ditch
Slot.
In various embodiments, photoresist layer can be deposited with 10 μm to 500 μm of thickness.
In various embodiments, after forming at least one metal support, passivating structure can be removed, and by insulating materials
It is deposited into the region for removing passivating structure.
In various embodiments, at least one groove is formed with 10 μm to 500 μm of depth or thickness.
In various embodiments, the trench depth formed above metal contact layer on the first semiconductor layer is greater than the
The groove formed above metal contact layer on two semiconductor layers, so that rectangular on metal contact layer on the first semiconductor layer
At groove have the thickness bigger than the groove formed above the metal contact layer on the second semiconductor layer.
In various embodiments, the thickness that at least one metal support is formed is much larger than at least one metal contact layer
Thickness, so that sufficiently thick metal support can be used as the meal substrate supports of LED structure.In various embodiments, at least one
A metal support is formed with 10 μm to 500 μm of thickness.
In various embodiments, at least one metal support includes copper or silver.
In various embodiments, plating, electron beam evaporation plating, hot evaporation, physical vapour deposition (PVD) (PVD), chemical gas can be used
Deposit one of (CVD) or sputtering sedimentation mutually to form at least one metal support.
In various embodiments, the method further includes: before forming groove, at least one metal contact layer
Upper formation seed layer.
In various embodiments, seed layer is formed to enhance the adhesion strength of subsequent metal supporter deposition.Seed layer can
Including material selected from the following: Cu (copper), Ni (nickel), W (tungsten), Au (gold), TaN (tantalum nitride), Ti (titanium), Pt (platinum), TiN
(titanium nitride), Sn (tin) and any other suitable metal.The thickness of seed layer 324 can be 10nm to 500nm.
Following methods can be used to carry out deposited seed layer: electron beam deposition, sputter, physical vapour deposition (PVD) (PVD), chemical gaseous phase
Deposit (CVD), plasma reinforced chemical vapour deposition (PECVD), ion beam depositing, electrochemical deposition or any other suitable
Deposition method.
In various embodiments, before forming groove, the method can further comprise: be formed above multilayered structure
Further passivating structure, so that at least one metal contact layer is exposed substantially；And the shape on exposed metal contact layer
At seed layer.
In various embodiments, forming further passivating structure can further comprise: passivation is deposited on multilayered structure
Layer and etch passivation layer to expose at least one metal contact layer substantially.For example, at least one metal contact layer can be exposed
Entire top surface.
In various embodiments, at least one metal contact layer may include reflection layer.Reflection layer is also referred to as specular layer,
It has 90% or more high reflectance in the visible spectrum.Specular layer may include Al (aluminium), Ag (silver), Ti (titanium), Pt
(platinum), Cr (chromium), Pd (palladium) or other metals with high reflectivity.
In various embodiments, at least one metal contact layer on the first semiconductor may include one or more surface
Layout comprising point, cross spider or interdigital.
In various embodiments, the thickness of at least one metal contact layer can be 3nm to 2000nm.
In various embodiments, one of following methods can be used to form at least one metal contact layer: electron beam
Deposition, sputter, physical vapour deposition (PVD), chemical vapor deposition, plasma reinforced chemical vapour deposition, ion beam depositing, electrochemistry
Deposition or any other suitable deposition method.
In various embodiments, the method can further comprise: the second semiconductor layer of etching and active layer, so that exposure
At least one first part of first semiconductor layer, and at least one second part of the first semiconductor layer is kept by active layer
It is covered with the second semiconductor layer.
In various embodiments, the contact of at least one metal is formed at least one first part of the first semiconductor layer
Layer.At least one metal contact layer in the first part of first semiconductor layer can be described as the metal contact of the first conduction type
Layer.The metal contact layer of first conduction type may include or can by Ti, Al, Pt, Pd, Cr, Au, ITO (tin indium oxide) or appoint
What its suitable metal or conductive metal oxide are made.
In various embodiments, at least one metal contact layer is formed on the second semiconductor layer.In the second semiconductor layer
The metal contact layer of upper formation can be described as the metal contact layer of the second conduction type.The metal contact layer of second conduction type can wrap
It includes or can be by Ni, Ag, Ti, Au, Pt, Pd, Al, W, Mo (molybdenum), Ta (tantalum), TaN, refractory metal, metal alloy, ITO (indium oxide
Tin) and at least one of any other suitable metal or the compound of any of these materials be made.
In various embodiments, at least one ditch is formed above the metal contact layer of at least one the first conduction type
Slot, and at least one groove is formed above the metal contact layer of at least one the second conduction type.In the first conduction type
Metal contact layer above groove and the groove above the metal contact layer of the second conduction type can simultaneously or separately be formed.
Depth possessed by groove above the metal contact layer of the first conduction type can be greater than the metal in the second conduction type and connect
Groove above contact layer.
In various embodiments, the metal support of at least one the first conduction type is formed in the gold of the first conduction type
Belong at least one groove above contact layer, and the metal support of at least one the second conduction type is formed in second and leads
In at least one groove above the metal contact layer of electric type.The metal support of first conduction type and the second conduction type
Metal support can simultaneously or separately be formed.Thickness possessed by the metal support of first conduction type, which can be greater than second, leads
The metal support of electric type.
In various embodiments, the second semiconductor layer and active layer are being etched at least one of the first semiconductor layer of exposure
After part, at least one isolated groove can be formed, extends through at least one first part of the first semiconductor layer.
It in various embodiments, can be by etching the first part of the first semiconductor layer until exposure substrate is isolated to be formed
Groove.
In various embodiments, isolated groove can be filled with passivation layer.
In various embodiments, the method can further comprise cutting or etching multilayer along at least one isolated groove
Structure is to form at least one luminescent device crystal grain.
In various embodiments, the method can further comprise using one in laser lift-off, grinding or chemical etching
Kind is to remove substrate.
In various embodiments, multilayered structure can be formed by following steps: the first conduction type is formed on the substrate
The first semiconductor layer, form active layer on the first semiconductor layer and form the of the second conduction type on active layer
Two semiconductor layers.
In various embodiments, Metallo-Organic Chemical Vapor deposition or molecular beam epitaxy can be used to grow on substrate
One or more of first semiconductor layer, active layer and second semiconductor layer.
In various embodiments, substrate can be selected from the group comprising following material: sapphire (Al2O3), silicon carbide
(SiC), gallium nitride (GaN), aluminium nitride (AlN) and GaAs (GaAs).In various embodiments, substrate can be the face c lining
Bottom, also referred to as (0001) substrate.In various embodiments, substrate can be coated with nucleating layer, for example, GaN or AlGaN (aluminium nitride
Gallium) nucleating layer, to mitigate the lattice mismatch between substrate and the nitration case of subsequent deposition.
In various embodiments, grow unintentional doped layer on substrate, and its be clipped in substrate and the first semiconductor layer it
Between.Substrate is removed with the unintentional doped layer of exposure.In various embodiments, exposed unintentional doped layer can be roughened.
In various embodiments, unintentional doped layer may include gallium nitride (u-GaN) layer of unintentional doping, for mitigating
Lattice mismatch between substrate and the nitration case of subsequent deposition.
In various embodiments, the first semiconductor layer of the first conduction type may include the gallium nitride (n-GaN) of n-type doping
Layer, or may include other suitable materials, such as aluminium gallium nitride alloy (n-AlGaN) layer of n-type doping, the InGaN (n- of n-type doping
InGaN) layer or aluminum indium gallium nitride (n-AlGaInN) layer of n-type doping.N-type dopant can be Si (silicon) or Ge (germanium).
In various embodiments, the second semiconductor layer of the second conduction type may include the gallium nitride (p-GaN) of p-type doping
Layer, or may include other suitable materials, such as aluminium gallium nitride alloy (p-AlGaN) layer of p-type doping, the InGaN (p- of p-type doping
InGaN) layer or aluminum indium gallium nitride (p-AlGaInN) layer of p-type doping.P-type dopant can be Mg (magnesium), Be (beryllium) or Zn
(zinc).
In various embodiments, active layer may include one or more quantum well layers being clipped between quantum barrier layer.Each
In a embodiment, active layer may include the single quantum well layer being clipped between quantum barrier layer, referred to as single quantum well (SQW) structure,
Or including multiple quantum well layers, each quantum well layer is clipped between quantum barrier layer, referred to as multiple quantum wells (MQW) structure.Quantum
Well layer and quantum barrier layer can be formed by alternate succession.
In various embodiments, one or more quantum well layers may include InGaN.It can be according to required launch wavelength
To change the indium component in Quantum Well.Quantum well layer can be unintentional doping.
In various embodiments, quantum barrier layer may include gallium nitride.Quantum barrier layer can be unintentional doping or can
With doped with n-type dopant, such as Si or Ge.
According to various embodiments, N-shaped and p-type supporter can be electroplated once, and keeps n and p metal contact layer complete
Contact metal support.It is primary unlike most of electroplating technology that a pad is only electroplated, as provided by passivating structure
With the help of mesh pattern, p and n metal support can be connected during electroplating technology, therefore once can just be electroplated and get well them.
This completely attaches to LED layer structure and metal support, therefore provides preferable heat dissipation.
It is heavy that metal substrate is completed in whole wafer level or distinct die level unlike traditional handicraft
Product, can carry out metal support deposition/plating of each embodiment, wherein the passivation part of passivating structure is set in die level
It sets between crystal grain and crystal grain so that crystal grain to link together.
The crystal grain of separation usually conventionally is not obtained by cutting entire copper wafer, in each embodiment
In method, it is only necessary to the passivation part of passivating structure is cut or etched, simple die separation technique is achieved in,
With low workload and high production.
Crystal grain assembling, the passivation being arranged in various embodiments conventionally will not be separated by temporary substrates
The passivation part of structure can be used as supporter and all crystal grains keep together, this provides the self-supporting of preparation process
Assembling.Therefore, the method for each embodiment simplifies technique, reduces cost and improves output.
The each embodiment for the technique for being used to form luminescent device is described below with reference to Fig. 3 to 14.
Fig. 3 shows schematic diagram 300, indicates the top view and section view of layer structure according to various embodiments.
Above-mentioned each embodiment is to being effective about following figure 3 and 16 the embodiment described, and vice versa.
As shown in figure 3, it illustrates the substrate 302 sequentially formed, the first conduction type the first semiconductor layer 304, have
Second semiconductor layer 306 of active layer and Second Type.Although active layer and the second semiconductor layer shown for purpose of explanation and
Labeled as one layer 306 it should be appreciated that active layer forms and is clipped in the first semiconductor layer 304 and the second semiconductor
Between layer 306.Sequence of layer in Fig. 3 is also referred to as LED epitaxial structure or LED wafer.
In various embodiments, LED epitaxial structure can be formed as follows: is deposited using Metallo-Organic Chemical Vapor
Or molecular beam epitaxy comes growth regulation semi-conductor layer 304, active layer and the second semiconductor layer 306 on substrate 302.
In following exemplary embodiments, substrate 302 can be Sapphire Substrate.First semiconductor layer 304 can be N-shaped
Doped layer, such as n-GaN layers.Active layer 306 can be InGaN/GaN active layer.Second semiconductor layer 306 can be p-type and mix
Diamicton, such as p-GaN layer.It is understood that various other suitable materials can be used for equivalent layer.
Fig. 4 shows schematic diagram 400 according to various embodiments, indicates after the mesa etch of inversion type technique
The top view and section view of layer structure.
As shown in figure 4, mesa etch can be carried out for inversion type technique, until exposure n-GaN layer 304.
In various embodiments, etchable p-GaN layer and active layer 306, so that at least one of exposure n-GaN layer 304
First part 308, and at least one second part 310 holding of n-GaN layer 304 is covered by active layer and p-GaN layer 306
Lid.Mesa etch can form at least one mesa structure 306, may include the first part 308 of n-GaN layer 304 and adjacent
P-GaN layer and active layer 306.
Fig. 5 shows schematic diagram 500, indicates the top view and section view of the layer structure outline after etching deeply.
As shown in figure 5, deep etching can be carried out, until exposure substrate 302.In various embodiments, n-GaN layers etchable
304 at least one first part 308, until exposure substrate 302, to form at least one isolated groove 312.In each implementation
In example, isolated groove 312 extends through at least one first part 308 of n-GaN layer 304, and is formed and be isolated for crystal grain
And the die separation in subsequent technique.
Fig. 6 shows schematic diagram 600 according to various embodiments, and expression is formed with p metal contact layer and the contact of n metal
The top view and section view of the profile of the multilayered structure of layer.
As shown in fig. 6, at least one p metal contact layer 314 can be deposited in p-GaN layer 306.It can be by least one n
Metal contact layer 316 deposits on n-GaN layer 304, such as in the first part 308 of n-GaN layer 304.Therefore, p metal connects
Contact layer 314 and n metal contact layer 316 are formed in the same side relative to n-GaN layer 304 and substrate 302.
P metal contact layer 314 may include ohmic contact layer and reflection layer (also referred to as specular layer), and can be described as p gold
Belong to mirror surface contact layer 314.P metallic mirror surface contact layer can have 90% or more high reflectance.P metallic mirror surface contact layer 314
May include or can be by Ni, Ag, Ti, Au, Pt, Pd, Al, W, Mo, Ta, TaN, refractory metal, metal alloy, ITO (tin indium oxide)
It is made at least one of any other suitable metal or the compound of these materials.The thickness of p metal contact layer 314 can
For 3nm to 2000nm.Following methods can be used to deposit p metal contact layer 314: electron beam deposition, sputter, physical vapor are heavy
Product, chemical vapor deposition, plasma reinforced chemical vapour deposition, ion beam depositing, electrochemical deposition or any other suitable
Deposition method.
N metal contact layer 316 may include or can be by Ti, Al, Pt, Pd, Cr, Ti, Au, ITO or any other suitable
Metal or conductive metal oxide are made.N metal contact layer 316 may also include specular layer, and can be described as n metallic mirror surface and connect
Contact layer 316.N metallic mirror surface contact layer can have 90% or more high reflectance.The thickness of n metal contact layer 316 can be 3nm
To 2000nm.Following methods can be used to deposit n metal contact layer 316: electron beam deposition, sputter, physical vapour deposition (PVD), chemistry
Vapor deposition, plasma reinforced chemical vapour deposition, ion beam depositing, electrochemical deposition or any other suitable deposition side
Method.
N metallic mirror surface contact layer 316 may be designed to various layouts, such as point, cross spider and interdigital or combinations thereof.If
The rule of thumb of meter is to reach best current spread with minimum area, so that light-emitting area is maximum.In view of P-contact layer 314 and n
The same side structure of contact layer 316, setting and formation n metallic mirror surface contact layer 316 are anti-with the light of enhancing arrival n-contact region
Penetrate rate.Therefore, it is designed compared to traditional lateral chip, it is suppressed that light blocking problem.
What is described in the above-described embodiments includes substrate 302, n-GaN layer 304, active layer and p-GaN layer 306 and p gold
The structure for belonging to contact layer 314 and n metal contact layer 316 can be described as multilayered structure 320 or can be described as LED structure 320.
It in various embodiments, can be in air or N2/O2About 5 minutes short is carried out in mixture with about 300-600 DEG C to move back
Fire, to realize better Ohmic contact.
Fig. 7 shows schematic diagram 700 according to various embodiments, indicates the multilayered structure for being deposited with the first passivating structure
Top view and section view.
As shown in fig. 7, the first passivating structure 322 can be formed above multilayered structure 320.In various embodiments, it is formed
And the first passivating structure 322 is patterned, so that exposing at least one metal contact layer substantially.For example, p metal contact layer 314
And/or the top surface of n metal contact layer 316 can expose substantially and without the first passivating structure.P metal contact layer 314 and/or n metal
The exposed area of contact layer 316 can be respectively substantially close to the top surface area of p metal contact layer 314 and/or n metal contact layer 316.
This allows the contact area of the subsequent metal support formed above metal contact layer 314,316 and metal contact layer enough
Greatly.
In various embodiments, the first passivating structure 322 can be formed by following steps: being sunk on multilayered structure 320
Product passivation layer 322, and etch passivation layer 322 to expose at least one metal contact layer 314,316 substantially.
In various embodiments, passivation layer 322 can be formed to fill isolated groove 312.
In various embodiments, passivation layer 322 can be deposited on the side wall of respective mesa structure, for example, being deposited on isolation
The side wall of groove 312, the side wall of metal contact layer 314,316, p-GaN layer and active layer 306 side wall on etc..
Fig. 8 shows schematic diagram 800 according to various embodiments, indicates the vertical view for being deposited with the multilayered structure of seed layer
Figure and sectional view.
As shown in figure 8, seed layer 324 can be deposited at least one of metal contact layer 314,316, it is subsequent to enhance
The adhesion strength of metal deposit.Seed layer 324 may include selected from Cu, Ni, W, Au, TaN, Ti, Pt, TiN, Sn and any other conjunction
The material of suitable metal.The thickness of seed layer 324 can be 10nm to 500nm.Following methods can be used to carry out deposited seed layer 324: electricity
Beamlet deposition, sputter, physical vapour deposition (PVD), chemical vapor deposition, plasma reinforced chemical vapour deposition, ion beam depositing, electricity
Chemical deposition or any other suitable deposition method.
In various embodiments, thin photoresist can be utilized to form the netted island pattern for seed layer deposition.Therefore, make
Pattern material forms the seed layer with mesh pattern on the top of at least one metal contact layer 314,316 with photoresist
324.Mesh pattern can have many variations, if the netted connection of different number between two islands is (for example, be deposited on metal contact layer
314,316 seed layer portion) and different in width netted connection (for example, between corresponding construction 304,306,314,316
Passivation layer 322).
Fig. 9 shows schematic diagram 900 according to various embodiments, indicates the multilayered structure for being formed with the second passivating structure
Top view and section view.
As shown in figure 9, the second passivating structure 330 is formed in 320 top of multilayered structure, such as on multilayered structure 320
It is formed on first passivating structure 322.Second passivating structure 330 may include passivation part 332, is limited at least one metal and connects
At least one groove 334 of the top of contact layer 314,316 and/or the adjacent groove of connection, as shown in Figure 9.
In various embodiments, the second passivating structure 330 can be formed as follows: being deposited on multilayered structure 320
Photoresist layer 336, and by 336 exposure and imaging of photoresist layer, so that will be at least one metal contact layer 3143,316 and
Photoresist part in seed layer 324 is removed to form at least one groove 334.It illustratively, can be by thick patterned material layer
336 (such as SU8 or 125nXT) are spun on the surface of the first passivating structure 322 and seed layer 324.Patterned material layer 336 can
With 10 μm to 500 μm of thickness.After exposure, develop to patterned material layer 336, according to different baking process
It may be different.After development, pattern structure 330 forms the groove 334 with pattern-free material.
In various embodiments, patterned material layer may include photoresist, oxide, nitride or other suitable Jie
Electric material.
Second passivating structure 330 is shown as the pattern structure on the surface of the first passivating structure 322.Patterning materials
The thickness of wall can be 10 μm to 500 μm.Groove 334 be also referred to as netted island region (when subsequent plating metal in the trench, shape
Reticulate island), be it is exposed, without patterning materials.Groove/netted island region 334 size (such as width) can be 100
μm to 2mm.The depth of groove 334 or the thickness in island area can be 10 μm to 500 μm.Each 332 (also referred to as netted company of passivation part
Socket part point) width can be 20 μm to 2mm.Passivation part/netted connection 332 thickness can be 10 μm to 500 μm.
In various embodiments, the groove 334 for being formed in 314 top of n metal contact layer has than being formed in the contact of p metal
The groove 334 of 314 top of layer bigger depth or thickness, as shown in Figure 9.Therefore, it is subsequently formed on n metal contact layer 316
The metal support of side has the thickness bigger than the metal support for being formed in 314 top of p metal contact layer.
In various embodiments, 334 area of groove of 316 top of n metal contact layer is formed in (for example, contact seed layer
The base area of the groove 334 of 324 or n metal contact layer 316) with the area of n metal contact layer 316 (for example, contact seed layer
324 or groove 334 n metal contact layer 316 top surface area) it is of substantially equal.It is formed in the ditch of 314 top of p metal contact layer
334 area of slot (for example, base area of the groove 334 of contact seed layer 324 or p metal contact layer 314) and p metal contact layer
314 area (for example, top surface area of the p metal contact layer 314 of contact seed layer 324 or groove 334) is of substantially equal.
Figure 10 shows schematic diagram 1000 according to various embodiments, and expression is formed at least one metal support
The top view and section view of multilayered structure.
As shown in Figure 10, after the second passivating structure 330 formed in Fig. 9 is to form groove/netted island region 334,
At least one metal support 344,346 is formed at least one groove 334.
Illustratively, plating metal supporter 344,346 (also referred to as metal net shaped island) is filled by the second passivation pattern
Groove 334 defined by 330.It is formed and can be described as p metal support 344 for the metal support 344 of p metal contact layer 314
Or p-electrode 344.It is formed and can be described as n metal support 346 or n-electrode for the metal support 346 of n metal contact layer 316
346.P metal support 344 and n metal support 346 are connected and are isolated by passivation part/netted connection 332.
In various embodiments, metal support 344,346 can be formed with 10 μm to 500 μm of thickness.In each implementation
In example, n metal support 346 can have the thickness bigger than p metal support 344.In various embodiments, metal support
344,346 thickness is much larger than the thickness of metal contact layer 314,316, so that thick metal support 344,346 can be used as LED junction
The meal substrate supports of structure.
In various embodiments, the area of p metal support 344 is (for example, contact seed layer 324 or p metal contact layer
The base area of 314 p metal support 344) can substantially near p metal contact layer 314 area (for example, contact seed
The top surface area of the p metal contact layer 314 of 324 or p of layer metal support 344), and the area of n metal support 346
(for example, base area of the n metal support 346 of contact seed layer 324 or n metal contact layer 316) can be substantially near n
The area of metal contact layer 316 is (for example, the top of the n metal contact layer 316 of contact seed layer 324 or n metal support 346
Face area), to form sufficiently large contact area between metal support 344,346 and metal contact layer 314,316.
In various embodiments, metal support/netted island 344,346 can have excellent heat conductivity and superior electrical conductivity
Property.Copper, silver or the other suitable metals for having these properties can be used as metal support/netted island 344,346
Material.
In the exemplary embodiment, copper plating can be used for for copper being electroplated into groove/netted island region 334, and wherein copper has
There are excellent electric conductivity and thermal conductivity (401W/mK).It can be used the cupric sulfate pentahydrate that purity is 99% as electrolyte, and
Addition of such as happy 320C additive for thinking chemical (Enthone Chemistry) as the electroplating quality for improving copper can be used
Agent.The range of electroplating current density may be configured as 2A/dm2To 20A/dm2.Corresponding rate of deposition range can be 50 μm/h to 200
μm/h.The thickness range of layers of copper 344,346 can be 10 μm to 500 μm.Other metal depositions, such as electron beam also can be used
Vapor deposition, hot evaporation, PVD, CVD or sputtering sedimentation carry out deposited metal supporter 344,346.
In various embodiments, the passivation part 332 of metal support 344,346 and the second passivating structure 330 can be
Coplanar, as shown in Figure 10, to be for example used as supporter or metal substrate when multilayered structure to be turned into downward.
The metal support formed according to various embodiments/netted island 344,346 can be used for a variety of purposes.In first aspect
In, metal support/netted island 344 and 346 can be used as the electrode of luminescent device.In second aspect, metal support/net
Shape island 344,346 can be used as heat sink and final supporter.P metal support 344 can have than n metal support 346 more
Big area and it can be used for being more effectively carried out heat dissipation.In a third aspect, metal support/netted island 344,346 and
Groove/netted connection 332 can be used as all crystal grains keeping together to be used for the connection of subsequent technique and supporter.
According to various embodiments, metal support 344,346 can be formed directly on metal contact layer 314,316, with
Metal contact layer 314,316 is physically contacted, without forming seed layer 324.
In various embodiments, after metal support deposition, the second passivating structure 330 can be retained as to isolation material
Material and additional backing material.In various embodiments, for example, if being used for the Other substrate materials of the second passivating structure 330 not
Suitable for being isolated and supporting, acetone may be used as solvent to remove the second passivating structure 330.It can be by insulating materials (as by force
Adhesive and isolated material) deposit to remove the second passivating structure 330 region in, so as to be filled in metal support 344,
In region between 346.
Figure 11 shows schematic diagram 1100 according to various embodiments, indicates to remove Sapphire Substrate from LED wafer
Technique top view and section view.
As shown in figure 11, the LED layer structure of Figure 10 is inverted so that substrate 302 upward.Laser lift-off, grinding can be used
Or method for chemially etching removes substrate 302.
Figure 12 shows schematic diagram 1200, and it illustrates the LED layer structures after removal Sapphire Substrate 302, uses
Netted island 344,346 is used as supporter.
In various embodiments, buffering and coalescing layer can be deposited (for example, GaN (u-GaN) layer of unintentional doping (does not show
Out)) and it is sandwiched between substrate and n-GaN layer 304.Therefore, after removing substrate 302, u-GaN layers can be exposed.It can
It does not need to expose n-GaN layer 304 by etching, because n contact layer 316 can be formed in the other side of n-GaN layer 304.
Figure 13 shows schematic diagram 1300 according to various embodiments, and it illustrates roughening processes.
In order to improve light extraction efficiency, wet etching or (such as such as photoetching, nanometer pressure of other patterning techniques can be passed through
Print and nanosphere lithography) surface of exposed u-GaN layer is roughened.
In various embodiments, n-GaN layer 302 can be exposed after removing substrate, and in a similar way to sudden and violent
The surface of the n-GaN layer 302 of dew is roughened.
Exposed surface, which can be roughened, pattern 350 comprising various shape, such as cone, pyramid, cylindricality and hemisphere
Shape, and the size range of spacing, diameter and height is in 100nm to 5 μ ms.
Figure 14 shows schematic diagram 1400 according to various embodiments, and it illustrates the separation of LED grain.
After u-GaN layers of surface is roughened and/or is patterned, use metal support 344,346 as gold
The LED grain for belonging to substrate, which attaches, to be perhaps placed on blue film 352 and can be separated by cutting machine or chemical etching,
As shown in figure 14.
In various embodiments, can by the second passivating structure 330 passivation part/it is netted connection 332 in one or
It is multiple to form one or more LED grains.In various embodiments, it can be cut along at least one isolated groove 312
It cuts or etches to form one or more LED grains.
In various embodiments, 322 part of the first passivating structure being filled in isolated groove 312 can be patterned
And it removes, by the passivation part of the second passivating structure 330/332 exposure of netted connection.Cleavable or etch passivation part/
It is netted to connect 332 to separate LED grain.
Figure 15 shows schematic diagram 1500 according to various embodiments, indicates looking up for the inversion type crystal grain in Figure 14
Figure has the copper supporter for being attached to blue film.
As shown in figure 15, multiple LED grains are attached on blue film 352, it, can be by multiple LED after removing blue film 352
Die separation is at single chip, as shown in figure 16.
Figure 16 shows luminescent device crystal grain or chip 1600 according to various embodiments.Luminescent device 1600 includes multilayer
Structure 1620, multilayered structure 1620 include successively the first semiconductor layer 304 (for example, n-type doping layer) of the first conduction type, have
The second semiconductor layer (for example, p-type doping layer) of active layer and the second conduction type, and have in the first semiconductor layer 304
With upper at least one metal contact layer formed of at least one of the second semiconductor layer 306 (for example, 314 He of p metal contact layer
N metal contact layer 316).Luminescent device 1600 further comprises at least one metal support (for example, p metal support 344
With n metal support), it is formed at least one groove of at least one 314,316 top of metal contact layer.
Preferably, seed layer 324 can be deposited between metal contact layer 314,316 and metal support 344,346.
Metal contact layer 314,316 can be insulated and be connected by passivation layer 322.It can be by being further passivated
Layer 336 to metal support 344,346 is insulated and is connected.
The area of the p metal support 344 contacted with p metal contact layer 314 or preferred seed layer 324 can substantially connect
The area of the p metal contact layer 314 closely contacted with p metal support 344 or preferred seed layer 324.With n metal contact layer
316 or the area of n metal support 346 that contacts of preferred seed layer 324 can substantially near with n metal support 346 or
The area for the n metal contact layer 316 that preferred seed layer 324 contacts.
Fig. 3 above to each embodiment described in 15 illustrates more than one LED grain.But it is to be understood that
It include that the method to form groove and metal support can also carry out single crystal grain according to above-mentioned each embodiment.
In the preparation that the method disclosed in above-mentioned each embodiment can be used for opto-electronic device, such as high-capacity LED, photoelectricity
Detector, laser diode and such as bipolar transistor microelectronic component.
According to above-mentioned each embodiment, netted electroplating technology is provided, for preparing inversion type height on the metallic substrate
Power LED.Therefore, p-electrode and n-electrode can be electroplated, simultaneously so as to p-contact and the n contact of the chip and connecing for metal support
Contacting surface product is no better than chip size.The net metal being electroplated together with p and n metal support connects simultaneously during electroplating technology
And by delineating or etching netted connection delamination in final chip preparing process, this increases to heat-conducting area
Almost entire size of devices.Compared with traditional inversion type technology, this is with much better heat dissipation.Further, since the gold of plating
Contact layer, supporter and heat sink can be used as simultaneously by belonging to supporter, this can substantially reduce cost.
Therefore, the method in each embodiment significantly improves radiating efficiency, increases output, reduces costs and right
It is very promising for the large-scale production of high power inversion type LED.
According to various embodiments, remove Sapphire Substrate and the exposed surface GaN is roughened or pattern with
Improve light extraction efficiency.It can be formed between LED layer structure and the metal contact layer of metal support substrate using high reflection mirror
Face, this can also contribute to improve light extraction efficiency.It, can be relative to the same of substrate and n-GaN layers for inversion type LED technique
N-electrode and p-electrode are formed on side.Therefore, light will not be stopped by any pad and metal wire.The technique does not need etching u-
GaN, and thick many GaN layers facilitate preferable light extraction.
The thermal conductivity of Sapphire Substrate is very poor (thermal conductivity is about 41.9W/mK), and LED is produced since junction temperature increases
Raw serious efficiency decline, caused by which is the big thermal resistance by Sapphire Substrate.According to various embodiments, pass through
Using the metal support with high heat conductance, such as copper metal supporter (thermal conductivity is about 401W/mK), generated in LED
Heat can effectively distribute and be able to maintain the high efficiency of LED.Compared with traditional inversion type technique, p-GaN and heat sink
Between contact area it is much larger, this allows good heat dissipation.
In the conventional technology, the metal substrate deposition of whole wafer level and metal substrate cutting technique are necessary.
Stress and bending may be generated in LED wafer, this will lead to the cracking and damage that LED film is generated after removing Sapphire Substrate
Wound.This will lead to LED and generates instant or incipient fault, and reduce the output and reliability of LED.Further, in metal substrate
Metallic is easy to produce during cutting technique, this is serious pollutant for LED and may cause leakage of current
With the problem of short circuit.These factors can reduce output and cause integrity problem.
According to various embodiments, it the netted die level that is connected to can be used to carry out metal net shaped island deposition, effectively inhibit
Stress and curved generation.For the separation of crystal grain, simple cutting technique only cuts netlike connecting part, this will be big
Big the problem of reducing metallic particles pollution, so as to improve the output and reliability of inversion type technique.
According to various embodiments, the metal support of netted connection can be used as supporter and p and n-electrode, section simultaneously
The cost of additional temporary support wafer during preparation process has been saved, and has therefore reduced cost.For inversion type technique
For, p and n-electrode pad are electroplated as self-supporting layer, which obviate welding procedure and saved for Au stud metal
With heat sink cost.As a result, preparation cost can reduce 10 to 20% compared with controlled collapsible chip connec-tion.Therefore each embodiment
Method has the efficiency in cost-effectiveness and material/process.
Although the contents of the present invention are specifically illustrated and are described by reference to specific embodiment, those skilled in the art
It should be understood that in the case where not departing from the spirit and scope of the present invention being defined by the following claims, wherein in form and
There can be various changes in details.Therefore, the scope of the present invention is indicated by appended claims, and it is intended that is covered
Fall into all changes in the meaning and scope of the equivalent of claim.
Claims (33)
1. a kind of method for forming luminescent device, which comprises
There is provided multilayered structure, the multilayered structure successively include substrate, the first semiconductor layer of the first conduction type, active layer with
And second conduction type the second semiconductor layer, and there is metal contact layer, the metal contact layer is formed in the first half and leads
On each of both body layer and the second semiconductor layer,
Groove is formed above each metal contact layer；
Wherein forming the groove includes: that passivating structure is formed above the multilayered structure, and the passivating structure includes passivation
Part, the passivation part limit the groove and limit the coupling part of connection adjacent trenches；And
Metal support is formed in groove and coupling part.
2. according to the method described in claim 1,
Wherein the area of the metal support is substantially near the metal contact layer area below metal support.
3. according to the method described in claim 1, further comprising:
One or more passivation parts are cut or are etched through to form at least one luminescent device crystal grain.
4. according to the method described in claim 1,
Wherein the passivation part is coplanar with metal support.
5. according to the method described in claim 1,
Wherein each passivation portion has the width within the scope of 20 μm to 2mm.
6. according to the method described in claim 1, wherein forming the passivating structure and including:
Photoresist layer is deposited on the multilayered structure；And
By the photoresist layer exposure and imaging, so that the photoresist layer part on the metal contact layer is removed, with shape
At the groove.
7. according to the method described in claim 6,
Wherein the photoresist layer can deposit 10 μm to 500 μm of thickness.
8. according to the method described in claim 1, further comprising:
After forming the metal support, the passivating structure is removed；And
Insulated metal is deposited into the region for having removed passivating structure.
9. according to the method described in claim 1,
Wherein the groove is formed with 10 μm to 500 μm of depth.
10. according to the method described in claim 1,
The trench depth wherein formed above the metal contact layer above first semiconductor layer is greater than described the second half
The trench depth formed above metal contact layer in conductor layer, so that rectangular on metal contact layer on the first semiconductor layer
At metal support thickness to be greater than the metal support that is formed above the metal contact layer on second semiconductor layer thick
Degree.
11. according to the method described in claim 1,
Wherein the metal support is formed with 10 μm to 500 μm of thickness.
12. according to the method described in claim 1,
Wherein the metal support includes copper or silver.
13. according to the method described in claim 1, further comprising:
Use one of plating, electron beam evaporation plating, hot evaporation, physical vapour deposition (PVD), chemical vapor deposition or sputtering sedimentation
To form metal support.
14. according to the method described in claim 1, further comprising:
Before forming the groove, seed layer is formed on metal contact layer.
15. according to the method for claim 14, further comprising:
Before forming the groove, further passivating structure is formed above the multilayered structure, so that by the metal
Contact layer exposes substantially；And
Seed layer is formed on the metal contact layer of the exposure.
16. according to the method for claim 15, wherein forming the further passivating structure and including:
The deposit passivation layer on the multilayered structure, and
The passivation layer is etched to expose the metal contact layer substantially.
17. according to the method described in claim 1,
Wherein the metal contact layer includes reflection layer.
18. according to the method described in claim 1,
Wherein the metal contact layer on first semiconductor includes one or more surface placement, surface placement's packet
Include point, cross spider or interdigital.
19. according to the method described in claim 1, further comprising:
Using electron beam deposition, sputter, physical vapour deposition (PVD), chemical vapor deposition, ion beam depositing or electrochemical deposition,
To form the metal contact layer.
20. according to the method described in claim 1, further comprising:
Second semiconductor layer and active layer are etched, so that at least one first part of first semiconductor layer is sudden and violent
Dew, and at least one second part holding of first semiconductor layer is covered by the active layer and the second semiconductor layer
Lid.
21. according to the method for claim 20, further comprising:
Metal contact layer is formed at least one first part of first semiconductor layer.
22. according to the method for claim 20, further comprising:
Metal contact layer is formed on second semiconductor layer.
23. according to the method for claim 20, further comprising:
Second semiconductor layer and active layer are being etched to expose at least one first part of first semiconductor layer
Later, at least one isolated groove for extending through at least one first part of first semiconductor layer is formed.
24. according to the method for claim 23,
Wherein by etching the first part of first semiconductor layer until exposure substrate forms the isolated groove.
25. according to the method for claim 23,
Wherein the isolated groove is filled with passivation layer.
26. according to the method for claim 25, further comprising:
Along at least one described isolated groove multilayered structure is cut or etched to form at least one luminescent device crystal grain.
27. according to the method described in claim 1, further comprising:
Substrate is removed using one of following methods: laser lift-off, grinding or chemical etching.
28. according to the method for claim 27,
Wherein unintentional doped layer is clipped between the substrate and the first semiconductor layer；
Remove the substrate wherein to expose unintentional doped layer.
29. according to the method for claim 28, further comprising:
The unintentional doped layer of the exposure is roughened.
30. according to the method for claim 28,
Wherein the unintentional doped layer includes the gallium nitride layer of unintentional doping.
31. according to the method described in claim 1,
Wherein first semiconductor layer include the gallium nitride layer of n-type doping, the aluminum gallium nitride of n-type doping, n-type doping nitrogen
Change the aluminium gallium nitride alloy indium layer of indium gallium layer or n-type doping.
32. according to the method described in claim 1,
Wherein second semiconductor layer include the gallium nitride layer of p-type doping, the aluminum gallium nitride of p-type doping, p-type doping nitrogen
Change the aluminium gallium nitride alloy indium layer of indium gallium layer or p-type doping.
33. according to the method described in claim 1,
Wherein the active layer includes the one or more quantum well layers clamped by quantum barrier layer.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201461996662P | 2014-05-14 | 2014-05-14 | |
| US61/996,662 | 2014-05-14 | ||
| PCT/SG2015/050100 WO2015174924A1 (en) | 2014-05-14 | 2015-05-07 | Method of forming a light-emitting device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106463596A CN106463596A (en) | 2017-02-22 |
| CN106463596B true CN106463596B (en) | 2019-07-09 |
Family
ID=54480318
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201580024877.7A Expired - Fee Related CN106463596B (en) | 2014-05-14 | 2015-05-07 | The manufacturing process of luminescent device |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP3143648A4 (en) |
| CN (1) | CN106463596B (en) |
| TW (1) | TW201547053A (en) |
| WO (1) | WO2015174924A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102017106410A1 (en) * | 2017-03-24 | 2018-09-27 | Osram Opto Semiconductors Gmbh | Method for producing an optoelectronic component and optoelectronic component |
| TWI633681B (en) * | 2017-06-09 | 2018-08-21 | 美商晶典有限公司 | Micro led display module manufacturing method |
| CN107293623A (en) * | 2017-07-12 | 2017-10-24 | 厦门乾照光电股份有限公司 | A kind of LED chip and preparation method thereof |
| DE102018119688A1 (en) * | 2018-08-14 | 2020-02-20 | Osram Opto Semiconductors Gmbh | Optoelectronic semiconductor component with a first contact element, which has a first and a second section, and method for producing the optoelectronic semiconductor component |
| CN111933765B (en) * | 2020-07-03 | 2022-04-26 | 厦门士兰明镓化合物半导体有限公司 | Miniature light-emitting diode and manufacturing method thereof, and miniature LED display module and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2194586A1 (en) * | 2008-12-08 | 2010-06-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| CN102881811A (en) * | 2011-07-12 | 2013-01-16 | 株式会社东芝 | Semiconductor light emitting device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070126016A1 (en) * | 2005-05-12 | 2007-06-07 | Epistar Corporation | Light emitting device and manufacture method thereof |
| JP5281612B2 (en) * | 2010-05-26 | 2013-09-04 | 株式会社東芝 | Semiconductor light emitting device and manufacturing method thereof |
-
2015
- 2015-05-07 CN CN201580024877.7A patent/CN106463596B/en not_active Expired - Fee Related
- 2015-05-07 EP EP15792197.4A patent/EP3143648A4/en not_active Withdrawn
- 2015-05-07 WO PCT/SG2015/050100 patent/WO2015174924A1/en active Application Filing
- 2015-05-11 TW TW104114843A patent/TW201547053A/en unknown
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2194586A1 (en) * | 2008-12-08 | 2010-06-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| CN102881811A (en) * | 2011-07-12 | 2013-01-16 | 株式会社东芝 | Semiconductor light emitting device |
Also Published As
| Publication number | Publication date |
|---|---|
| EP3143648A1 (en) | 2017-03-22 |
| EP3143648A4 (en) | 2017-09-27 |
| TW201547053A (en) | 2015-12-16 |
| CN106463596A (en) | 2017-02-22 |
| WO2015174924A1 (en) | 2015-11-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104538507B (en) | Method for preparing semiconductor light-emitting apparatus | |
| CN103378240B (en) | Luminescent device and light emitting device packaging piece | |
| CN106463596B (en) | The manufacturing process of luminescent device | |
| EP1941556B1 (en) | Semiconductor light-emitting device with metal support substrate | |
| JP5881689B2 (en) | LIGHT EMITTING ELEMENT CHIP AND ITS MANUFACTURING METHOD | |
| CN101840967A (en) | Indium-gallium-aluminum-nitrogen semiconductor luminescent device and preparation method thereof | |
| WO2006076208A2 (en) | Systems and methods for removing operating heat from a light emitting diode | |
| JP2012084933A (en) | Light emitting device and method of manufacturing the same | |
| TW200834698A (en) | Die separation | |
| WO2001091196A1 (en) | Group iii nitride compound semiconductor light-emitting device and method for producing the same | |
| TW201128803A (en) | Devices on textured substrates and methods for fabricating semiconductive devices | |
| CN102067345A (en) | Method for fabricating semiconductor light-emitting device with double-sided passivation | |
| CN112186079A (en) | Preparation method of LED chip with vertical structure | |
| CN105742450A (en) | Preparation method for LED chip capable of forming light spots with specific planar geometric patterns through illumination, and structure of LED chip | |
| TW201304187A (en) | Solid state optoelectronic device with plated support substrate | |
| US20150372207A1 (en) | Semiconductor light emitting device package | |
| US7910389B2 (en) | Vertical semiconductor light-emitting device and method of manufacturing the same | |
| KR101438812B1 (en) | Reflective structure and light emitting device | |
| KR20080053180A (en) | Supporting substrates for semiconductor light emitting device and high-performance vertical structured semiconductor light emitting devices using the supporting substrates | |
| US20140014999A1 (en) | Solid state lighting devices with low contact resistance and methods of manufacturing | |
| TW201212287A (en) | Semiconductor light emitting device and method for manufacturing the semiconductor light emitting device | |
| TWI307175B (en) | Non-substrate light emitting diode and fabrication method thereof | |
| CN204144301U (en) | A kind of light emitting diode with vertical structure | |
| TW201246603A (en) | Solid state lighting devices with reduced dimensions and methods of manufacturing | |
| TW201019505A (en) | Opto-electronic device structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190709 Termination date: 20210507 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |