CN106463596A - Method of forming a light-emitting device - Google Patents
Method of forming a light-emitting device Download PDFInfo
- Publication number
- CN106463596A CN106463596A CN201580024877.7A CN201580024877A CN106463596A CN 106463596 A CN106463596 A CN 106463596A CN 201580024877 A CN201580024877 A CN 201580024877A CN 106463596 A CN106463596 A CN 106463596A
- Authority
- CN
- China
- Prior art keywords
- layer
- metal contact
- metal
- contact layer
- methods according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/647—Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0091—Scattering means in or on the semiconductor body or semiconductor body package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Abstract
Various embodiments provide a method of forming a light-emitting device. The method may include providing a multi-layer structure, wherein the multi-layer structure includes a substrate, a first semiconductor layer of a first conductivity type, an active layer and a second semiconductor layer of a second conductivity type in sequence, and includes at least one metal contact formed on at least one of the first semiconductor layer and the second semiconductor layer. The method further includes forming at least one trench over the at least one metal contact, and forming at least one metal support in the at least one trenches.
Description
Cross-Reference to Related Applications
This application claims the priority of the U.S. Provisional Application No. 61/996,662 of on May 14th, 2014 submission, for institute
Purposefully, entire contents of the provisional application is herein incorporated by reference.
Technical field
Embodiment relates generally to luminescent device and the method forming luminescent device.
Background technology
Light emitting diode (LED), for example, GaN (nitridation is sowed) base LED is considered the light source choosing for solid-state illumination of future generation
Select, and come in the past few decades, the research and development in this field has been achieved with huge progress.High brightness GaN LED is
It is applied to various uses, the backlight of such as LCD, traffic signss and full-color display.
At present, GaN LED initially enters general illumination market.In order to accelerate to penetrate into general illumination market, need further
Improve the performance of GaN LED.For example, power conversion efficiency under high power operation for the GaN LED must be more excellent, for example, be higher than
50%, to make them replace current fluorescent lamp (it has about 20% power conversion efficiency), thus having more preferable Gu
Object is tested and cost-benefit benefit.
For the efficiency improving the LED being currently based on Sapphire Substrate further, there are technical limitations.Due to electrical insulating property
Matter and bad thermal conductivity (W/m K), often suffered from based on sapphire LED exist bad light extraction, bad radiating,
High junction temperature (>100 DEG C) and high power operation under big efficiency decline (efficiency droop) (>40%).These shortcomings
LED efficiency for improving further under the conditions of high power operation is provided with serious bottleneck.
Therefore, it has been proposed that the concept of inversion type LED (Inverted LED) is solving these problems.Inversion type
LED is the structure on metal support, wherein to extract light from the opposite side of electrode, and this represents the technology water of Modern LED technologies
Standard has many unrivaled advantages, such as compares traditional transversary LED, and it has excellent conduction of heat and light extraction.
Even if these promising LED operate at higher current densities also can have high efficiency and extremely long service life.It is inverted
The principle of formula LED is to remove Sapphire Substrate, and LED is attached to the replacement lining with good electrical conduction rate and pyroconductivity
Bottom.Substitute substrate to will act as conducting the electrode of electric current and effective heat dissipation path.After substrate removes, can be unintentional to expose
GaN (n-GaN) surface of GaN (u-GaN) surface of doping or N-shaped doping is roughened or is patterned, to improve light extraction
Take efficiency.
However, this technology not can simply directly be realized, and key point is that substrate removes technique.Removing blue treasured
It should realize strong and conductive supporting layer first before stone, so as to maintain self-supporting (free standing) LED layer and
Prevent any damage causing during and after sapphire removes.This supporting layer can be formed by wafer bonding technique,
Wafer bonding technique, application is referred to as the Au welding procedure of thermosonic flip chip bonding.
Fig. 1 shows the method that preparation has the LED 100 of inversion type structure.First by with lateral chip identical work
Skill to prepare LED grain 110, for example, includes mesa etch, metal pad deposition, minute surface contact layer deposition, crystal grain cutting etc..
LED grain 110 include n-GaN layer, MQW (MQW) layer and the p-GaN layer sequentially forming on a sapphire substrate and
The n pad being formed on n-GaN layer and p-GaN layer respectively and p pad (including transparent ohmic contact layer and reflecting mirror).To deposit
There is SiO2The LED grain 110 of passivation layer overturns, and uses hot ultrasonic inversion type bonding technology by p pad and n pad via weldering
Connect projection 122 (for example, Au projection) and metal contact layer 124 weld or be bonded to heat sink (submount) 120 (as copper or
Silicon Wafer).After LED grain 110 is bonded to heat sink 120, remove Sapphire Substrate (possibly patterned substrate) and right
It is roughened.Unintentional doped layer between substrate and n-GaN layer or n-GaN layer also can be exposed and be roughened,
To improve light extraction efficiency.P pad and n pad are formed at the same side, thus light will not be by any pad and metal wire institute
Stop, shown in light emitting path as represented in figure 1.
However, because device is by one or more soldering projections or Au stud (Au to heat sink heat conduction path
The diameter of stud is about 50-200 μm) completing, and the area of soldering projection or Au stud is much smaller than the area of whole device,
Therefore Au welding procedure provides little contact area and comes for radiating.Additionally, Au welding and heat sink preparation significantly increase LED
Holistic cost.Comparatively, metal plating is a kind of inexpensive way of the bonding gripper shoe realizing inversion type LED.However, falling
The electrode putting formula LED chip is on the same side, and they must be isolated to form final chip.Additionally, it is right
For metal electroplating process, plating in need must be partly conductive.This requirement hinders metal plating skill
Art is applied in inversion type LED preparation technology.
Content of the invention
Each embodiment provides a kind of method forming luminescent device.Methods described may include offer multiple structure, its
Described in multiple structure include substrate, the first semiconductor layer of the first conduction type, active layer and the second conduction type successively
The second semiconductor layer, and include at least one metal contact layer, at least one metal contact layer described is in the first quasiconductor
In layer and the second semiconductor layer at least one upper formation.Methods described further includes at least one metal described
Form at least one groove above contact layer, and form at least one metal support at least one groove described.
Brief description
In accompanying drawing, the same reference symbol in different accompanying drawings refers generally to same parts.Accompanying drawing is not necessarily drawn to scale,
And focus on the principle of the present invention is described.In the following description, each embodiment is described with reference to the following drawings, wherein：
Fig. 1 shows the method that preparation has the LED of inversion type structure；
Fig. 2 shows the method flow diagram forming luminescent device according to each embodiment；
Fig. 3 shows the schematic diagram according to each embodiment, the schematic shows top view and the sectional view of Rotating fields；
Fig. 4 shows the schematic diagram according to each embodiment, the schematic shows the mesa etch in inversion type technique
The top view of Rotating fields afterwards and sectional view；
Fig. 5 shows schematic diagram, the schematic shows the top view of Rotating fields profile and section after deep etching
Figure；
Fig. 6 shows the schematic diagram according to each embodiment, the schematic shows the multilamellar being formed with metal contact layer
The top view of the profile of structure and sectional view；
Fig. 7 shows the schematic diagram according to each embodiment, and the schematic shows deposition has the multilamellar of the first passivation layer
The top view of structure and sectional view；
Fig. 8 shows the schematic diagram according to each embodiment, and the schematic shows deposition has the multiple structure of Seed Layer
Top view and sectional view；
Fig. 9 shows the schematic diagram according to each embodiment, the schematic shows and is formed with the many of the second passivating structure
The top view of Rotating fields and sectional view；
Figure 10 shows the schematic diagram according to each embodiment, the schematic shows and is formed with the support of at least one metal
The top view of the multiple structure of thing and sectional view；
Figure 11 shows the schematic diagram according to each embodiment, the schematic shows Sapphire Substrate from LED wafer
The top view of the technique removing and sectional view；
Figure 12 shows schematic diagram, the schematic shows the LED layer structure removing after substrate, and this LED layer structure makes
With netted island as supporter；
Figure 13 shows the schematic diagram according to each embodiment, the schematic shows roughening process；
Figure 14 shows the schematic diagram according to each embodiment, the schematic shows the separation of LED grain；
Figure 15 shows the schematic diagram according to each embodiment, the schematic shows facing upward of the inversion type crystal grain in Figure 14
View, this inversion type crystal grain has the copper supporter being attached to blue film；
Figure 16 shows the schematic diagram according to each embodiment, the schematic shows luminescent device.
Specific embodiment
Refer to the attached drawing described in detail below, these brief descriptions illustrate detail and the enforcement that the present invention can be implemented
Example.Fully describe these embodiments in detail, so that those skilled in the art can implement the present invention.Without departing from the present invention
In the case of scope, other embodiments can be adopted, and structure and change in logic can be carried out.Each embodiment is not
Necessarily exclude each other, because some embodiments can combine to form new enforcement with one or more of the other embodiment
Example.
Each embodiment is provided and is formed luminescent device (such as inversion type high power using net metal electroplating technology
LED method).Compared with conventional art, each embodiment formed metal support (also referred to as net metal island), as
The supporter of preparation technology afterwards.When the method is applied prepare to inversion type when, in the side of pattern technology and net metal island
Help down, p and n-electrode supporter can be electroplated simultaneously.Compared with traditional inversion type technology, metal support and metal contact layer have greatly
A lot of contacts area will allow good a lot of radiating.Therefore, each embodiment provides a kind of more cost efficient and has
The method to improve yield rate and efficiency for the very high potential.
It should be appreciated that ought in the following description using term " on ", " top ", " horizontal ", " top ", " bottom "
Deng when, these terms be for convenience and using and contribute to understanding relative position or direction, and be not intended to limit any dress
Put or structure or any device or structure any part orientation.
Fig. 2 shows the method flow Figure 200 forming luminescent device according to each embodiment.
202, multiple structure is set.This multiple structure include successively substrate, the first semiconductor layer of the first conduction type,
Active layer and the second semiconductor layer of the second conduction type, and include in the first semiconductor layer and the second semiconductor layer extremely
Few upper at least one metal contact layer being formed.
204, form at least one groove above at least one metal contact layer.
206, at least one groove forms at least one supporter.
According to each embodiment, multiple structure is LED (light emitting diode) structure.First and second semiconductor layer and active
Layer forms LED structure together with least one metal contact layer.
According to each embodiment, the area of metal support is substantially near the metal contact layer face below metal support
Long-pending.The area of metal support can refer to the bottom surface area of metal support directly or indirectly contacting with metal contact layer.
The area of metal contact layer can refer to the top surface area of metal contact layer directly or indirectly contacting with metal support.
In various embodiments, form this at least one groove, including formation passivating structure above multiple structure.Passivation
Structure includes passivation part, and it limits this at least one groove and/or connects adjacent groove.In the exemplary embodiment, two
Mutually passivation part can limit groove therebetween.In the exemplary embodiment, can be connected by passivation part therebetween or isolation two
Adjacent trenches.
In various embodiments, methods described can further include cut or be etched through one or more passivation parts with
Form at least one luminescent device crystal grain.
In various embodiments, passivation part and at least one metal support are coplanar.As explanation, when upset multilamellar knot
Structure is so that when substrate is in top, coplanar passivation part and at least one metal support are formed and used as substrate supports
Thing.
In various embodiments, each passivation portion can have 20 μm of width to 2mm.
In various embodiments, form passivating structure may include：Photoresist layer is deposited on multiple structure；And by photoetching
Glue-line exposed and developed so that the photoresist part at least one metal contact layer is removed to form at least one ditch
Groove.
In various embodiments, photoresist layer can deposit 10 μm to 500 μm of thickness.
In various embodiments, after forming at least one metal support, removable passivating structure, and by insulant
It is deposited into removing the region of passivating structure.
In various embodiments, at least one groove is formed with 10 μm to 500 μm of depth or thickness.
In various embodiments, the gash depth being formed above metal contact layer on the first semiconductor layer is more than the
The groove that formed above metal contact layer on two semiconductor layers is so that square on metal contact layer on the first semiconductor layer
The groove becoming has the thickness bigger than the groove being formed above the metal contact layer on the second semiconductor layer.
In various embodiments, the thickness that at least one metal support is formed is much larger than at least one metal contact layer
Thickness is so that sufficiently thick metal support can be used as the meal substrate supports of LED structure.In various embodiments, at least one
Individual metal support is formed with 10 μm to 500 μm of thickness.
In various embodiments, at least one metal support includes copper or silver.
In various embodiments, can be using plating, electron beam evaporation plating, hot evaporation, physical vapour deposition (PVD) (PVD), chemical gas
Mutually deposit one of (CVD) or sputtering sedimentation to form at least one metal support.
In various embodiments, methods described further includes：Before forming groove, at least one metal contact layer
Upper formation Seed Layer.
In various embodiments, form Seed Layer to strengthen the adhesion strength of subsequent metal supporter deposition.Seed Layer can
Including selected from following material：Cu (copper), Ni (nickel), W (tungsten), Au (golden), TaN (tantalum nitride), Ti (titanium), Pt (platinum), TiN
(titanium nitride), Sn (stannum) and any other suitable metal.The thickness of Seed Layer 324 can be 10nm to 500nm.
Deposited seed layer can be carried out using following methods：Electron beam deposition, sputter, physical vapour deposition (PVD) (PVD), chemical gaseous phase
Deposition (CVD), plasma reinforced chemical vapour deposition (PECVD), ion beam depositing, electrochemical deposition or any other suitable
Deposition process.
In various embodiments, before forming groove, methods described can further include：Formed above multiple structure
Further passivating structure is so that substantially expose at least one metal contact layer；And expose metal contact layer on shape
Become Seed Layer.
In various embodiments, form further passivating structure can further include：Deposition passivation on multiple structure
Layer, and etch passivation layer is with basic at least one metal contact layer of exposure.For example, at least one metal contact layer can be exposed
Whole top surface.
In various embodiments, at least one metal contact layer may include reflection layer.Reflection layer is also referred to as specular layer,
It has 90% and above high reflectance in the visible spectrum.Specular layer may include Al (aluminum), Ag (silver-colored), Ti (titanium), Pt
(platinum), Cr (chromium), Pd (palladium) or other metals with high reflectance.
In various embodiments, at least one metal contact layer on the first quasiconductor may include one or more surface
Layout, it includes point, reticule or interdigital.
In various embodiments, the thickness of at least one metal contact layer can be 3nm to 2000nm.
In various embodiments, at least one metal contact layer can be formed using one of following methods：Electron beam
Deposition, sputter, physical vapour deposition (PVD), chemical vapor deposition, plasma reinforced chemical vapour deposition, ion beam depositing, electrochemistry
Deposition or any other suitable deposition process.
In various embodiments, methods described can further include：Etch the second semiconductor layer and active layer so that exposing
At least one Part I of first semiconductor layer, and at least one Part II holding of the first semiconductor layer is by active layer
Covered with the second semiconductor layer.
In various embodiments, the contact of at least one metal is formed at least one Part I of the first semiconductor layer
Layer.At least one metal contact layer on the Part I of the first semiconductor layer can be described as the metal contact of the first conduction type
Layer.The metal contact layer of the first conduction type may include or by Ti, Al, Pt, Pd, Cr, Au, ITO (tin indium oxide) or can appoint
What its suitable metal or conducting metal oxide are made.
In various embodiments, at least one metal contact layer is formed on the second semiconductor layer.In the second semiconductor layer
The metal contact layer of upper formation can be described as the metal contact layer of the second conduction type.The metal contact layer of the second conduction type can wrap
Include or can be by Ni, Ag, Ti, Au, Pt, Pd, Al, W, Mo (molybdenum), Ta (tantalum), TaN, refractory metal, metal alloy, ITO (Indium sesquioxide.
Stannum) and the complex of any other suitable metal or these materials any at least one make.
In various embodiments, form at least one ditch above the metal contact layer of at least one the first conduction type
Groove, and form at least one groove above the metal contact layer of at least one the second conduction type.In the first conduction type
Metal contact layer above groove and the groove above the metal contact layer of the second conduction type can simultaneously or separately be formed.
The depth that groove above the metal contact layer of the first conduction type has can connect more than the metal in the second conduction type
Groove above contact layer.
In various embodiments, the metal support of at least one the first conduction type is formed at the gold of the first conduction type
Belong at least one groove above contact layer, and the metal support of at least one the second conduction type is formed at second and leads
In at least one groove above the metal contact layer of electric type.The metal support of the first conduction type and the second conduction type
Metal support can simultaneously or separately be formed.The thickness that the metal support of the first conduction type has can be led more than second
The metal support of electric type.
In various embodiments, etching the second semiconductor layer and active layer with expose the first semiconductor layer at least one
After part, at least one isolated groove can be formed, it extends through at least one Part I of the first semiconductor layer.
In various embodiments, isolation can be formed by etching the Part I of the first semiconductor layer until exposing substrate
Groove.
In various embodiments, isolated groove can be filled with passivation layer.
In various embodiments, methods described can further include to cut along at least one isolated groove or etch multilamellar
Structure is to form at least one luminescent device crystal grain.
In various embodiments, methods described can further include using in laser lift-off, grinding or chemical etching
Plant and to remove substrate.
In various embodiments, multiple structure can be formed by following steps：First conduction type is formed on substrate
The first semiconductor layer, form active layer and the second conduction type is formed on active layer the on the first semiconductor layer
Two semiconductor layers.
In various embodiments, can be using metal organic chemical vapor deposition or molecular beam epitaxy come in Grown
One or more of first semiconductor layer, active layer and second semiconductor layer.
In various embodiments, substrate can select from the group comprising following material：Sapphire (Al2O3), carborundum
(SiC), gallium nitride (GaN), aluminium nitride (AlN) and GaAs (GaAs).In various embodiments, substrate can be c face lining
Bottom, also referred to as (0001) substrate.In various embodiments, substrate can be coated with nucleating layer, for example, GaN or AlGaN (aluminium nitride
Gallium) nucleating layer, to mitigate the lattice mismatch between substrate and the nitration case of subsequent deposition.
In various embodiments, in the unintentional doped layer of Grown, and its be clipped in substrate and the first semiconductor layer it
Between.Remove substrate to expose unintentional doped layer.In various embodiments, the unintentional doped layer exposing can be roughened.
In various embodiments, unintentional doped layer may include gallium nitride (u-GaN) layer of unintentional doping, for mitigating
Lattice mismatch between substrate and the nitration case of subsequent deposition.
In various embodiments, the first semiconductor layer of the first conduction type may include the gallium nitride (n-GaN) of N-shaped doping
Layer, or may include other suitable materials, such as aluminium gallium nitride alloy (n-AlGaN) layer of N-shaped doping, the InGaN (n- of N-shaped doping
InGaN) aluminum indium gallium nitride (n-AlGaInN) layer of layer or N-shaped doping.N-type dopant can be Si (silicon) or Ge (germanium).
In various embodiments, the second semiconductor layer of the second conduction type may include the gallium nitride (p-GaN) of p-type doping
Layer, or may include other suitable materials, such as aluminium gallium nitride alloy (p-AlGaN) layer of p-type doping, the InGaN (p- of p-type doping
InGaN) aluminum indium gallium nitride (p-AlGaInN) layer of layer or p-type doping.P-type dopant can be Mg (magnesium), Be (beryllium) or Zn
(zinc).
In various embodiments, active layer may include one or more quantum well layers being clipped between quantum barrier layer.Each
In individual embodiment, active layer may include the single quantum well layer being clipped between quantum barrier layer, referred to as single quantum well (SQW) structure,
Or including multiple quantum well layers, each quantum well layer is clipped between quantum barrier layer, referred to as MQW (MQW) structure.Quantum
Well layer and quantum barrier layer can be formed by alternate succession.
In various embodiments, one or more quantum well layers may include InGaN.Can be according to required launch wavelength
To change the indium component in SQW.Quantum well layer can be unintentional doping.
In various embodiments, quantum barrier layer may include gallium nitride.Quantum barrier layer can be unintentional doping or can
With doped with n-type dopant, such as Si or Ge.
According to each embodiment, N-shaped and p-type supporter can be electroplated once, and make n and p metal contact layer complete
Contacting metal supporter.Once only electroplate a pad unlike most of electroplating technology, provided by passivating structure
With the help of net-like pattern, p and n metal support can be connected during electroplating technology, get well them therefore, it is possible to once just electroplate.
This makes LED layer structure completely attach to metal support, therefore provides and preferably radiates.
Metal substrate is completed unlike traditional handicraft on whole wafer level or distinct die level sink
Long-pending, the metal support deposition/plating of each embodiment can be carried out on die level, the passivation part of wherein passivating structure sets
Put between crystal grain and crystal grain so that crystal grain to link together.
Conventionally generally do not obtain detached crystal grain by cutting whole copper wafer, in each embodiment
It is only necessary to being cut to the passivation part of passivating structure or etching in method, it is achieved in simple die separation technique, its
There is low workload and high production.
Conventionally crystal grain assembling, the passivation arranging in various embodiments will not separated by temporary substrates
The passivation part of structure can be used as supporter and all crystal grains keep together, and this provides the self-supporting of preparation technology
Assembling.Therefore, the method for each embodiment simplifies technique, decreases cost and improve output.
Each embodiment of technique for forming luminescent device to be described below with reference to Fig. 3 to 14.
Fig. 3 shows schematic diagram 300, and it represents the top view of the Rotating fields according to each embodiment and sectional view.
Each embodiment above-mentioned is to being effective with regard to the embodiment described in figure 3 below and 16, and vice versa.
As shown in figure 3, it illustrates the substrate 302 sequentially forming, the first semiconductor layer 304 of the first conduction type, having
Active layer and the second semiconductor layer 306 of Second Type.Although for purpose of explanation active layer and the second semiconductor layer are shown and
It is labeled as one layer 306 it should be appreciated that active layer forms and is clipped in the first semiconductor layer 304 and the second quasiconductor
Between layer 306.Sequence of layer in Fig. 3 is also referred to as LED epitaxial structure or LED wafer.
In various embodiments, LED epitaxial structure can be formed as follows：Using metal organic chemical vapor deposition
Or molecular beam epitaxy comes growth regulation semi-conductor layer 304, active layer and the second semiconductor layer 306 on substrate 302.
In following exemplary embodiments, substrate 302 can be Sapphire Substrate.First semiconductor layer 304 can be N-shaped
Doped layer, such as n-GaN layer.Active layer 306 can be InGaN/GaN active layer.Second semiconductor layer 306 can be that p-type is mixed
Diamicton, such as p-GaN layer.It is understood that various other suitable materials can be used for equivalent layer.
Fig. 4 shows the schematic diagram 400 according to each embodiment, and it represents after the mesa etch of inversion type technique
The top view of Rotating fields and sectional view.
As shown in figure 4, for inversion type technique, mesa etch can be carried out, until exposing n-GaN layer 304.
In various embodiments, etchable p-GaN layer and active layer 306 are so that expose at least one of n-GaN layer 304
Part I 308, and at least one Part II 310 of n-GaN layer 304 keeps being covered by active layer and p-GaN layer 306
Lid.Mesa etch can form at least one mesa structure 306, and it may include the Part I 308 of n-GaN layer 304 and adjacent
P-GaN layer and active layer 306.
Fig. 5 shows schematic diagram 500, and it represents the top view of the Rotating fields profile after deep etching and sectional view.
As shown in figure 5, deep etching can be carried out, until exposing substrate 302.In various embodiments, etchable n-GaN layer
304 at least one Part I 308, until exposing substrate 302, to form at least one isolated groove 312.In each enforcement
In example, isolated groove 312 extends through at least one Part I 308 of n-GaN layer 304, and is formed for crystal grain isolation
And the die separation in subsequent technique.
Fig. 6 shows the schematic diagram 600 according to each embodiment, and it represents that being formed with p metal contact layer contacts with n metal
The top view of the profile of multiple structure of layer and sectional view.
As shown in fig. 6, at least one p metal contact layer 314 can be deposited in p-GaN layer 306.Can be by least one n
Metal contact layer 316 deposits on n-GaN layer 304, such as on the Part I 308 of n-GaN layer 304.Therefore, p metal connects
Contact layer 314 and n metal contact layer 316 are formed at the same side with respect to n-GaN layer 304 and substrate 302.
P metal contact layer 314 may include ohmic contact layer and reflection layer (also referred to as specular layer), and can be described as p gold
Belong to minute surface contact layer 314.P metallic mirror surface contact layer can have 90% and above high reflectance.P metallic mirror surface contact layer 314
May include or can be by Ni, Ag, Ti, Au, Pt, Pd, Al, W, Mo, Ta, TaN, refractory metal, metal alloy, ITO (tin indium oxide)
Make with least one in the complex of any other suitable metal or these materials.The thickness of p metal contact layer 314 can
For 3nm to 2000nm.P metal contact layer 314 can be deposited using following methods：Electron beam deposition, sputter, physical vapor are sunk
Long-pending, chemical vapor deposition, plasma reinforced chemical vapour deposition, ion beam depositing, electrochemical deposition or any other suitable
Deposition process.
N metal contact layer 316 may include or can be suitable by Ti, Al, Pt, Pd, Cr, Ti, Au, ITO or any other
Metal or conducting metal oxide are made.N metal contact layer 316 may also include specular layer, and can be described as n metallic mirror surface and connect
Contact layer 316.N metallic mirror surface contact layer can have 90% and above high reflectance.The thickness of n metal contact layer 316 can be 3nm
To 2000nm.N metal contact layer 316 can be deposited using following methods：Electron beam deposition, sputter, physical vapour deposition (PVD), chemistry
Vapour deposition, plasma reinforced chemical vapour deposition, ion beam depositing, electrochemical deposition or any other suitable deposition side
Method.
N metallic mirror surface contact layer 316 may be designed to various layouts, such as point, reticule and interdigital etc. or a combination thereof.If
The empirical law of meter is to reach best current spread with minimum area so that light-emitting area is maximum.In view of P-contact layer 314 and n
The same side structure of contact layer 316, setting and formation n metallic mirror surface contact layer 316 are to strengthen the anti-of the light reaching n-contact region
Penetrate rate.Therefore, compare traditional lateral chip design it is suppressed that light blocking problem.
The inclusion substrate 302, n-GaN layer 304, active layer and the p-GaN layer 306 that describe in the above-described embodiments and p gold
Belong to contact layer 314 and the structure of n metal contact layer 316 can be described as multiple structure 320 or can be described as LED structure 320.
In various embodiments, can be in air or N2/O2Carry out about 5 minutes short with about 300-600 DEG C in mixture to move back
Fire, to realize more preferable Ohmic contact.
Fig. 7 shows the schematic diagram 700 according to each embodiment, and it represents that deposition has the multiple structure of the first passivating structure
Top view and sectional view.
As shown in fig. 7, the first passivating structure 322 can be formed above multiple structure 320.In various embodiments, formed
And pattern the first passivating structure 322 so that substantially exposing at least one metal contact layer.For example, p metal contact layer 314
And/or the top surface of n metal contact layer 316 can expose and no the first passivating structure substantially.P metal contact layer 314 and/or n metal
The exposed area of contact layer 316 can respectively substantially close to p metal contact layer 314 and/or n metal contact layer 316 top surface area.
The contact area of this metal support that can allow follow-up formation above metal contact layer 314,316 and metal contact layer is enough
Greatly.
In various embodiments, the first passivating structure 322 can be formed by following steps：Heavy on multiple structure 320
Long-pending passivation layer 322, and etch passivation layer 322 exposes at least one metal contact layer 314,316 with basic.
In various embodiments, passivation layer 322 can be formed to fill isolated groove 312.
In various embodiments, passivation layer 322 can be deposited on the side wall of respective mesa structure, for example, is deposited on isolation
The side wall of groove 312, the side wall, p-GaN layer and active layer 306 of metal contact layer 314,316 side wall first-class.
Fig. 8 shows the schematic diagram 800 according to each embodiment, and it represents that deposition has the vertical view of the multiple structure of Seed Layer
Figure and sectional view.
As shown in figure 8, Seed Layer 324 can be deposited at least one of metal contact layer 314,316, follow-up to strengthen
The adhesion strength of metal deposit.Seed Layer 324 may include selected from Cu, Ni, W, Au, TaN, Ti, Pt, TiN, Sn and any other conjunction
The material of suitable metal.The thickness of Seed Layer 324 can be 10nm to 500nm.Deposited seed layer 324 can be carried out using following methods：Electricity
Beamlet deposition, sputter, physical vapour deposition (PVD), chemical vapor deposition, plasma reinforced chemical vapour deposition, ion beam depositing, electricity
Chemical deposition or any other suitable deposition process.
In various embodiments, thin photoresist can be utilized to form the netted island pattern for seed layer deposition.Therefore, make
Pattern material forms the Seed Layer with net-like pattern on the top of at least one metal contact layer 314,316 with photoresist
324.Net-like pattern can have many changes, and the netted connection of varying number between such as two islands (for example, is deposited on metal contact layer
314th, 316 seed layer portion) and different in width netted connection (for example, between corresponding construction 304,306,314,316
Passivation layer 322).
Fig. 9 shows the schematic diagram 900 according to each embodiment, and it represents the multiple structure being formed with the second passivating structure
Top view and sectional view.
As shown in figure 9, the second passivating structure 330 is formed above multiple structure 320, such as on multiple structure 320
Formed on first passivating structure 322.Second passivating structure 330 may include passivation part 332, and it is limited at least one metal and connects
At least one groove 334 of contact layer 314,316 top and/or connect adjacent groove, as shown in Figure 9.
In various embodiments, the second passivating structure 330 can be formed as follows：Multiple structure 320 deposits
Photoresist layer 336, and will be exposed and developed for photoresist layer 336 so that will be at least one metal contact layer 3143,316 and
Photoresist part in Seed Layer 324 removes to form at least one groove 334.Exemplarily, can be by thick patterned material layer
336 (as SU8 or 125nXT) are spun on the first passivating structure 322 and the surface of Seed Layer 324.Patterned material layer 336 can
There is 10 μm to 500 μm of thickness.After exposure, patterned material layer 336 is developed, it is according to different baking process
It is probably different.After development, pattern structure 330 forms the groove 334 with pattern-free material.
In various embodiments, patterned material layer may include photoresist, oxide, nitride or other suitable Jie
Electric material.
Second passivating structure 330 is shown as the pattern structure on the surface of the first passivating structure 322.Patterning materials
The thickness of wall can be 10 μm to 500 μm.Groove 334 also referred to as netted island region (when follow-up plated metal in the trench, its shape
Reticulate island), it is to expose, and does not have patterning materials.The size (such as width) in groove/netted island region 334 can be 100
μm to 2mm.The thickness in the depth of groove 334 or island area can be 10 μm to 500 μm.Each passivation part 332 (also referred to as netted company
Socket part is divided) width can be for 20 μm to 2mm.Passivation part/netted thickness connecting 332 can be 10 μm to 500 μm.
In various embodiments, the groove 334 being formed at n metal contact layer 314 top has ratio and is formed at the contact of p metal
The bigger depth of groove 334 above layer 314 or thickness, as shown in Figure 9.Therefore, it is subsequently formed on n metal contact layer 316
The metal support of side has the thickness bigger than the metal support being formed at p metal contact layer 314 top.
In various embodiments, groove 334 area being formed at n metal contact layer 316 top (for example, contacts Seed Layer
The base area of the groove 334 of 324 or n metal contact layers 316) (for example, contact Seed Layer with the area of n metal contact layer 316
324 or groove 334 n metal contact layer 316 top surface area) of substantially equal.It is formed at the ditch of p metal contact layer 314 top
Groove 334 area (for example, the base area of the groove 334 of contact Seed Layer 324 or p metal contact layer 314) and p metal contact layer
314 area (for example, the top surface area of the p metal contact layer 314 of contact Seed Layer 324 or groove 334) is of substantially equal.
Figure 10 shows the schematic diagram 1000 according to each embodiment, and its expression is formed with least one metal support
The top view of multiple structure and sectional view.
As shown in Figure 10, after the second passivating structure 330 in forming Fig. 9 is to form groove/netted island region 334,
At least one metal support 344,346 is formed at least one groove 334.
Exemplarily, plated metal supporter 344,346 (also referred to as metal net shaped island) is filling by the second passivation pattern
The groove 334 that 330 are limited.Form the metal support 344 for p metal contact layer 314 and can be described as p metal support 344
Or p-electrode 344.Form the metal support 346 for n metal contact layer 316 and can be described as n metal support 346 or n-electrode
346.P metal support 344 and n metal support 346 are connected by passivation part/netted connection 332 and isolate.
In various embodiments, metal support 344,346 can be formed with 10 μm to 500 μm of thickness.In each enforcement
In example, n metal support 346 can have the thickness bigger than p metal support 344.In various embodiments, metal support
344th, 346 thickness is much larger than the thickness of metal contact layer 314,316 so that thick metal support 344,346 can be used as LED junction
The meal substrate supports of structure.
In various embodiments, area (for example, contact Seed Layer 324 or the p metal contact layer of p metal support 344
The base area of 314 p metal support 344) (for example, seed can be contacted substantially near the area of p metal contact layer 314
The top surface area of the p metal contact layer 314 of layer 324 or p metal support 344), and the area of n metal support 346
(for example, the base area of the n metal support 346 of contact Seed Layer 324 or n metal contact layer 316) can be substantially near n
Area (for example, the top of the n metal contact layer 316 of contact Seed Layer 324 or n metal support 346 of metal contact layer 316
Face area) to form sufficiently large contact area between metal support 344,346 and metal contact layer 314,316.
In various embodiments, metal support/netted island 344,346 can possess excellent heat conductivity and superior electrical conductivity
Property.Copper, silver or possess other suitable metals of these properties and can be used as metal support/netted island 344,346
Material.
In the exemplary embodiment, copper plating can be used for electroplating in groove/netted island region 334 by copper, wherein copper tool
There are excellent electric conductivity and heat conductivity (401W/m K).Copper sulphate pentahydrate that purity be 99% can be used as electrolyte, and
Can be used if the additives such as the happy 320C thinking chemical (Enthone Chemistry) are as the interpolation of the electroplating quality improving copper
Agent.The scope of electroplating current density may be configured as 2A/dm2To 20A/dm2.Corresponding rate of deposition scope can be 50 μm/h to 200
μm/h.The thickness range of layers of copper 344,346 can be 10 μm to 500 μm.It is also possible to use other metal deposition, such as electron beam
Evaporation, hot evaporation, PVD, CVD or sputtering sedimentation, carry out deposited metal supporter 344,346.
In various embodiments, the passivation part 332 of metal support 344,346 and second passivating structure 330 can be
Coplanar, as shown in Figure 10, to be used as supporter or metal substrate for example when being turned into down multiple structure.
Multiple purposes be can be used for according to metal support/netted island 344,346 that each embodiment is formed.In first aspect
In, metal support/netted island 344 and 346 can be used as the electrode of luminescent device.In second aspect, metal support/net
Shape island 344,346 can be used as heat sink and final supporter.P metal support 344 can have than n metal support 346 more
Big area and can be used for is more effectively carried out radiating.In a third aspect, metal support/netted island 344,346 and
Groove/netted connection 332 can be used as all crystal grains keep together for the connection of subsequent technique and supporter.
According to each embodiment, metal support 344,346 can be formed directly on metal contact layer 314,316, with
Physical contact metal contact layer 314,316, without forming Seed Layer 324.
In various embodiments, after metal support deposition, the second passivating structure 330 can be retained as isolating material
Material and additional backing material.In various embodiments, for example, if being used for the Other substrate materials of the second passivating structure 330 not
It is applied to isolation and supports, then can use acetone as solvent to remove the second passivating structure 330.Can be by insulant (as by force
Binding agent and isolated material) deposit in the region removing the second passivating structure 330 so that be filled in metal support 344,
In region between 346.
Figure 11 shows the schematic diagram 1100 according to each embodiment, and Sapphire Substrate is removed by its expression from LED wafer
The top view of technique and sectional view.
As shown in figure 11, the LED layer structure of Figure 10 is inverted so that substrate 302 upward.Laser lift-off, grinding can be used
Or method for chemially etching removes substrate 302.
Figure 12 shows schematic diagram 1200, it illustrates the LED layer structure removing after Sapphire Substrate 302, its use
Netted island 344,346 is as supporter.
In various embodiments, (for example, GaN (u-GaN) layer of unintentional doping (does not show with coalescing layer can to deposit buffering
Go out)) and be sandwiched between substrate and n-GaN layer 304.Therefore, after removing substrate 302, u-GaN layer can be exposed.Can
Do not need to expose n-GaN layer 304 by etching, because n contact layer 316 can be formed at the opposite side of n-GaN layer 304.
Figure 13 shows the schematic diagram 1300 according to each embodiment, it illustrates roughening process.
In order to improve light extraction efficiency, can be by wet etching or other patterning techniques (such as such as photoetching, nanometer pressure
Print and nanosphere lithography) the surface of the u-GaN layer exposing is roughened.
In various embodiments, after removing substrate, n-GaN layer 302 can be exposed, and in a similar manner to sudden and violent
The surface of the n-GaN layer 302 of dew is roughened.
The surface exposing can be roughened pattern 350, and it includes variously-shaped, such as cone, pyramid, cylindricality and hemisphere
Shape, and the size range of spacing, diameter and height is in 100nm to 5 μ m.
Figure 14 shows the schematic diagram 1400 according to each embodiment, it illustrates the separation of LED grain.
After the surface to u-GaN layer is roughened and/or patterns, metal support 344,346 is used as gold
The LED grain belonging to substrate can be attached or be placed on blue film 352, and can be separated by cutting machine or chemical etching,
As shown in figure 14.
In various embodiments, can by one of passivation part/netted connection 332 of the second passivating structure 330 or
Multiple forming one or more LED grain.In various embodiments, can be cut along at least one isolated groove 312
Cut or etch to form one or more LED grain.
In various embodiments, the first passivating structure 322 being filled in isolated groove 312 part can be patterned
And remove, the passivation part of the second passivating structure 330/netted connection 332 is exposed.Cleavable or etch passivation part/
Netted connection 332 is to separate LED grain.
Figure 15 shows the schematic diagram 1500 according to each embodiment, and it represents looking up of the inversion type crystal grain in Figure 14
Figure, it has the copper supporter being attached to blue film.
As shown in figure 15, multiple LED grain are attached on blue film 352, after removing blue film 352, can be by the plurality of LED
Die separation becomes single chip, as shown in figure 16.
Figure 16 shows luminescent device crystal grain or chip 1600 according to each embodiment.Luminescent device 1600 includes multilamellar
Structure 1620, multiple structure 1620 includes the first semiconductor layer 304 (for example, N-shaped doped layer) of the first conduction type successively, has
Second semiconductor layer (for example, p-type doped layer) of active layer and the second conduction type, and have in the first semiconductor layer 304
With at least one of the second semiconductor layer 306 upper at least one metal contact layer (for example, p metal contact layer 314 He being formed
N metal contact layer 316).Luminescent device 1600 further includes at least one metal support (for example, p metal support 344
With n metal support), it is formed at least one groove of at least one metal contact layer 314,316 top.
Preferably, Seed Layer 324 can be deposited between metal contact layer 314,316 and metal support 344,346.
By passivation layer 322, metal contact layer 314,316 can be insulated and be connected.Can be passivated by further
Layer 336 metal support 344,346 to be insulated and connects.
The area of the p metal support 344 being contacted with p metal contact layer 314 or preferred Seed Layer 324 can substantially be connect
The area of the nearly p metal contact layer 314 contacting with p metal support 344 or preferred Seed Layer 324.With n metal contact layer
The area of the n metal support 346 of 316 or preferred Seed Layer 324 contacts can substantially near with n metal support 346 or
The area of the n metal contact layer 316 of preferred Seed Layer 324 contact.
Fig. 3 above illustrates more than one LED grain to each embodiment described in 15.But it is to be understood that,
Include forming groove according to each embodiment above-mentioned and the method for metal support also can be carried out to single crystal grain.
In the preparation that method disclosed in each embodiment above-mentioned can be used for opto-electronic device, such as high-capacity LED, photoelectricity
Detector, laser diode and as the microelectronic component such as bipolar transistor.
According to each embodiment above-mentioned, there is provided netted electroplating technology, high for preparing inversion type on the metallic substrate
Power LED.Therefore, p-electrode and n-electrode can be electroplated, so that the p-contact of this chip contacts with n and the connecing of metal support simultaneously
Contacting surface is amassed and is no better than die size.The net metal electroplated together with p and n metal support is connected simultaneously during electroplating technology
And in final chip preparing process by delineate or etching netted connect and delamination, this makes heat-conducting area increase to
Almost whole size of devices.Compared with traditional inversion type technology, this has much better radiating.Further, since the gold of plating
Belong to supporter and can be used simultaneously as contact layer, supporter and heat sink, this can substantially reduce cost.
Therefore, the method in each embodiment significantly improves radiating efficiency, increased output, reduces cost and right
It is very promising for the large-scale production of high power inversion type LED.
According to each embodiment, remove Sapphire Substrate and the GaN surface exposing is roughened or patterned with
Improve light extraction efficiency.Application high reflection mirror between LED layer structure and the metal contact layer of metal support substrate can be formed at
Face, this can also contribute to improve light extraction efficiency.For inversion type LED technique, can be same with respect to substrate and n-GaN layer
N-electrode and p-electrode are formed on side.Therefore, light will not be stopped by any pad and metal wire.This technique does not need to etch u-
GaN, and thick a lot of GaN layer contributes to preferable light extraction.
The heat conductivity of Sapphire Substrate is very poor (thermal conductivity is about 41.9W/m K), and LED produces because junction temperature increases
The serious efficiency of life declines, and this junction temperature increase is to be led to by the big thermal resistance of Sapphire Substrate.According to each embodiment, pass through
Using the metal support with high heat conductance, such as copper metal supporter (thermal conductivity is about 401W/m K), produce in LED
Heat can effectively distribute and can keep the high efficiency of LED.Compared with traditional inversion type technique, p-GaN and heat sink
Between contact area much larger, this allows good radiating.
In the conventional technology, the metal substrate deposition of whole wafer level and metal substrate cutting technique are necessary.
Stress and bending may be produced in LED wafer, this can lead to produce cracking and the damage of LED film after removing Sapphire Substrate
Wound.This will lead to LED to produce instant or incipient fault, and reduce output and the reliability of LED.Further, in metal substrate
Easily metallic is produced, this is serious pollutant for LED and may lead to leakage of current during cutting technique
With short-circuit problem.These factors can reduce output and cause integrity problem.
According to each embodiment, metal net shaped island deposition can be carried out using the netted die level that is connected to, it effectively suppresses
Stress and the generation of bending.For the separation of crystal grain, simple cutting technique only cuts netlike connecting part, and this will be big
The big problem reducing metallic particles pollution, thus improve output and the reliability of inversion type technique.
According to each embodiment, the metal support of netted connection can be used simultaneously as supporter and p and n-electrode, its section
Save the cost of extra temporary support wafer during preparation technology, and therefore decrease cost.For inversion type technique
For, p and n-electrode pad are all electroplated as self-supporting layer, which obviates welding procedure and save for Au stud metal
With heat sink cost.As a result, compared with controlled collapsible chip connec-tion, preparation cost can reduce 10 to 20%.Therefore each embodiment
Method has the efficiency in cost benefit and material/process.
Although present disclosure specifically illustrates by reference to specific embodiment and describes, those skilled in the art
It should be understood that in the case of without departing from the spirit and scope of the present invention being defined by the following claims, wherein in form and
Various changes can be had on details.Therefore, the scope of the present invention is represented by claims, and it is intended that covers
All changes in the implication and scope of the equivalent falling into claim.
Claims (34)
1. a kind of method forming luminescent device, methods described includes：
There is provided multiple structure, described multiple structure include successively substrate, the first semiconductor layer of the first conduction type, active layer with
And second conduction type the second semiconductor layer, and there is at least one metal contact layer, described at least one metal contact
Layer is formed at least one of the first semiconductor layer and the second semiconductor layer,
Form at least one groove above at least one metal contact layer described；And
Form at least one metal support at least one groove.
2. method according to claim 1,
The area of wherein said metal support is substantially near the metal contact layer area below metal support.
3. method according to claim 1 and 2, wherein forms at least one groove described and includes：
Form passivating structure above described multiple structure, described passivating structure include limiting at least one groove described and/or
Connect the passivation part of adjacent trenches.
4. method according to claim 3, further includes：
Cut or be etched through one or more described passivation parts to form at least one luminescent device crystal grain.
5. the method according to claim 3 or 4,
Wherein said passivation part and at least one metal support are coplanar.
6. the method according to any one of claim 3 to 5,
Passivation portion described in each of which has 20 μm of width to 2mm.
7. the method according to any one of claim 3 to 6, wherein forms described passivating structure and includes：
Photoresist layer is deposited on described multiple structure；And
Will be exposed and developed for described photoresist layer so that the photoresist layer part at least one metal contact layer described is moved
Remove, to form at least one groove described.
8. method according to claim 7,
Wherein said photoresist layer can deposit 10 μm to 500 μm of thickness.
9. the method according to any one of claim 3 to 8, further includes：
After forming at least one metal support described, remove described passivating structure；And
Insulated metal is deposited into removing the region of passivating structure.
10. method according to any one of claim 1 to 9,
At least one groove wherein said is formed with 10 μm to 500 μm of depth.
11. methods according to any one of claim 1 to 10,
The gash depth being formed wherein above the metal contact layer of described first semiconductor layer is more than described the second half
The gash depth that formed above metal contact layer in conductor layer is so that square on metal contact layer on the first semiconductor layer
It is thick that the metal support thickness becoming is more than the metal support being formed above the metal contact layer on described second semiconductor layer
Degree.
12. methods according to any one of claim 1 to 11,
At least one metal support wherein said is formed with 10 μm to 500 μm of thickness.
13. methods according to any one of claim 1 to 12,
At least one metal support wherein said includes copper or silver.
14. methods according to any one of claim 1 to 13, further include：
Using one of plating, electron beam evaporation plating, hot evaporation, physical vapour deposition (PVD), chemical vapor deposition or sputtering sedimentation
To form at least one metal support.
15. methods according to any one of claim 1 to 14, further include：
Before forming described groove, Seed Layer is formed at least one metal contact layer.
16. methods according to claim 15, further include：
Formed described groove before, form further passivating structure above described multiple structure so that by described at least
One metal contact layer exposes substantially；And
Seed Layer is formed on the metal contact layer of described exposure.
17. methods according to claim 16, wherein form described further passivating structure and include：
Deposit passivation layer on described multiple structure, and
Described passivation layer is etched substantially to expose at least one metal contact layer described.
18. methods according to any one of claim 1 to 17,
At least one metal contact layer wherein said includes reflection layer.
19. methods according to any one of claim 1 to 18,
Wherein at least one metal contact layer on described first quasiconductor includes one or more surface placement, described table
Face layout includes point, reticule or interdigital.
20. methods according to any one of claim 1 to 19, further include：
Using electron beam deposition, sputter, physical vapour deposition (PVD), chemical vapor deposition, plasma reinforced chemical vapour deposition, ion
Bundle deposition, electrochemical deposition or any other suitable sedimentation, to form at least one metal contact layer described.
21. methods according to any one of claim 1 to 20, further include：
Etch described second semiconductor layer and active layer so that will be sudden and violent at least one Part I of described first semiconductor layer
Reveal, and at least one Part II of described first semiconductor layer keeps being covered by described active layer and the second semiconductor layer
Lid.
22. methods according to claim 21, further include：
At least one Part I of described first semiconductor layer forms at least one metal contact layer.
23. methods according to claim 21 or 22, further include：
Described second semiconductor layer forms at least one metal contact layer.
24. methods according to any one of claim 21 to 23, further include：
Etch described second semiconductor layer and active layer so that at least one portion of described first semiconductor layer to be exposed after,
Form at least one isolated groove of at least one Part I extending through described first semiconductor layer.
25. methods according to claim 24,
Wherein form described isolated groove by etching the Part I of described first semiconductor layer until exposing substrate.
26. methods according to claim 24 or 25,
Wherein said isolated groove is filled with passivation layer.
27. methods according to claim 26, further include：
To cut or to etch multiple structure along at least one isolated groove described to form at least one luminescent device crystal grain.
28. methods according to any one of claim 1 to 27, further include：
Remove substrate using one of following methods：Laser lift-off, grinding or chemical etching.
29. methods according to claim 28,
Wherein unintentional doped layer is clipped between described substrate and the first semiconductor layer；
Wherein remove described substrate to expose unintentional doped layer.
30. methods according to claim 29, further include：
The unintentional doped layer of described exposure is roughened.
31. methods according to claim 29 or 30,
Wherein said unintentional doped layer includes the gallium nitride layer of unintentional doping.
32. methods according to any one of claims 1 to 31,
Wherein said first semiconductor layer includes the gallium nitride layer of N-shaped doping, the aluminum gallium nitride of N-shaped doping, the nitrogen of N-shaped doping
Change indium gallium layer or the aluminium gallium nitride alloy indium layer of N-shaped doping.
33. methods according to any one of claims 1 to 32,
Wherein said second semiconductor layer includes the gallium nitride layer of p-type doping, the aluminum gallium nitride of p-type doping, the nitrogen of p-type doping
Change indium gallium layer or the aluminium gallium nitride alloy indium layer of p-type doping.
34. methods according to any one of claims 1 to 33,
Wherein said active layer includes the one or more quantum well layers clamped described in quantum barrier layer.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201461996662P | 2014-05-14 | 2014-05-14 | |
| US61/996,662 | 2014-05-14 | ||
| PCT/SG2015/050100 WO2015174924A1 (en) | 2014-05-14 | 2015-05-07 | Method of forming a light-emitting device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106463596A true CN106463596A (en) | 2017-02-22 |
| CN106463596B CN106463596B (en) | 2019-07-09 |
Family
ID=54480318
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201580024877.7A Expired - Fee Related CN106463596B (en) | 2014-05-14 | 2015-05-07 | The manufacturing process of luminescent device |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP3143648A4 (en) |
| CN (1) | CN106463596B (en) |
| TW (1) | TW201547053A (en) |
| WO (1) | WO2015174924A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107293623A (en) * | 2017-07-12 | 2017-10-24 | 厦门乾照光电股份有限公司 | A kind of LED chip and preparation method thereof |
| CN110476259A (en) * | 2017-03-24 | 2019-11-19 | 欧司朗光电半导体有限公司 | For manufacturing the method and opto-electronic device of opto-electronic device |
| CN111933765A (en) * | 2020-07-03 | 2020-11-13 | 厦门士兰明镓化合物半导体有限公司 | Miniature light-emitting diode and manufacturing method thereof, and miniature LED display module and manufacturing method thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI633681B (en) * | 2017-06-09 | 2018-08-21 | 美商晶典有限公司 | Micro led display module manufacturing method |
| DE102018119688A1 (en) | 2018-08-14 | 2020-02-20 | Osram Opto Semiconductors Gmbh | Optoelectronic semiconductor component with a first contact element, which has a first and a second section, and method for producing the optoelectronic semiconductor component |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070126016A1 (en) * | 2005-05-12 | 2007-06-07 | Epistar Corporation | Light emitting device and manufacture method thereof |
| EP2194586A1 (en) * | 2008-12-08 | 2010-06-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| US20110291148A1 (en) * | 2010-05-26 | 2011-12-01 | Kabushiki Kaisha Toshiba | Semiconductor light emitting device and method for manufacturing same |
| CN102881811A (en) * | 2011-07-12 | 2013-01-16 | 株式会社东芝 | Semiconductor light emitting device |
-
2015
- 2015-05-07 CN CN201580024877.7A patent/CN106463596B/en not_active Expired - Fee Related
- 2015-05-07 EP EP15792197.4A patent/EP3143648A4/en not_active Withdrawn
- 2015-05-07 WO PCT/SG2015/050100 patent/WO2015174924A1/en active Application Filing
- 2015-05-11 TW TW104114843A patent/TW201547053A/en unknown
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070126016A1 (en) * | 2005-05-12 | 2007-06-07 | Epistar Corporation | Light emitting device and manufacture method thereof |
| EP2194586A1 (en) * | 2008-12-08 | 2010-06-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| US20110291148A1 (en) * | 2010-05-26 | 2011-12-01 | Kabushiki Kaisha Toshiba | Semiconductor light emitting device and method for manufacturing same |
| CN102881811A (en) * | 2011-07-12 | 2013-01-16 | 株式会社东芝 | Semiconductor light emitting device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110476259A (en) * | 2017-03-24 | 2019-11-19 | 欧司朗光电半导体有限公司 | For manufacturing the method and opto-electronic device of opto-electronic device |
| US11658277B2 (en) | 2017-03-24 | 2023-05-23 | Osram Oled Gmbh | Method for producing an optoelectronic component, and optoelectronic component |
| CN107293623A (en) * | 2017-07-12 | 2017-10-24 | 厦门乾照光电股份有限公司 | A kind of LED chip and preparation method thereof |
| CN111933765A (en) * | 2020-07-03 | 2020-11-13 | 厦门士兰明镓化合物半导体有限公司 | Miniature light-emitting diode and manufacturing method thereof, and miniature LED display module and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201547053A (en) | 2015-12-16 |
| CN106463596B (en) | 2019-07-09 |
| WO2015174924A1 (en) | 2015-11-19 |
| EP3143648A4 (en) | 2017-09-27 |
| EP3143648A1 (en) | 2017-03-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11563158B2 (en) | Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated systems and methods | |
| CN103378240B (en) | Luminescent device and light emitting device packaging piece | |
| US7977691B2 (en) | Light emitting device and method of manufacturing the same | |
| US8368100B2 (en) | Semiconductor light emitting diodes having reflective structures and methods of fabricating same | |
| EP1941556B1 (en) | Semiconductor light-emitting device with metal support substrate | |
| US20110018013A1 (en) | Thin-film flip-chip series connected leds | |
| CN101840967A (en) | Indium-gallium-aluminum-nitrogen semiconductor luminescent device and preparation method thereof | |
| US20120273823A1 (en) | Nitride semiconductor light emitting element and method of manufacturing the same | |
| US20140084244A1 (en) | Wafer Level Photonic Device Die Structure and Method of Making the Same | |
| CN106463596B (en) | The manufacturing process of luminescent device | |
| CN1998094B (en) | Fabrication of reflective layer on semiconductor light emitting diodes | |
| TW200403869A (en) | Contacting scheme for large and small area semiconductor light emitting flip chip devices | |
| JP2006005369A (en) | Light-emitting device with transparent submount having reverse-side via | |
| US20140217457A1 (en) | Light-emitting element chip and manufacturing method therefor | |
| US20150214435A1 (en) | Semiconductor light emitting diode device and formation method thereof | |
| CN102067345A (en) | Method for fabricating semiconductor light-emitting device with double-sided passivation | |
| CN105742450A (en) | Preparation method for LED chip capable of forming light spots with specific planar geometric patterns through illumination, and structure of LED chip | |
| KR101438812B1 (en) | Reflective structure and light emitting device | |
| CN107731975B (en) | Nanotube LED and manufacturing method thereof | |
| US7910389B2 (en) | Vertical semiconductor light-emitting device and method of manufacturing the same | |
| KR20080053180A (en) | Supporting substrates for semiconductor light emitting device and high-performance vertical structured semiconductor light emitting devices using the supporting substrates | |
| EP2438628A1 (en) | Light emitting semiconductor device and method for manufacturing | |
| CN204144301U (en) | A kind of light emitting diode with vertical structure | |
| EP2668674A1 (en) | Solid state lighting devices with reduced dimensions and methods of manufacturing | |
| CN104269470A (en) | Method for preparing perpendicular structure LED thin film chip capable of releasing stress and structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190709 Termination date: 20210507 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |