CN106449666A - 阵列基板和显示装置 - Google Patents

阵列基板和显示装置 Download PDF

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Publication number
CN106449666A
CN106449666A CN201611095901.9A CN201611095901A CN106449666A CN 106449666 A CN106449666 A CN 106449666A CN 201611095901 A CN201611095901 A CN 201611095901A CN 106449666 A CN106449666 A CN 106449666A
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China
Prior art keywords
layer
conductive layer
conductive
array base
passivation
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CN201611095901.9A
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CN106449666B (zh
Inventor
刘晓娣
袁广才
王刚
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN201611095901.9A priority Critical patent/CN106449666B/zh
Publication of CN106449666A publication Critical patent/CN106449666A/zh
Priority to US15/743,597 priority patent/US20190027509A1/en
Priority to PCT/CN2017/091984 priority patent/WO2018099079A1/zh
Application granted granted Critical
Publication of CN106449666B publication Critical patent/CN106449666B/zh
Priority to US16/721,109 priority patent/US10804298B2/en
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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Abstract

提供一种阵列基板和显示装置。该阵列基板包括衬底基板和依次设置在衬底基板上的第一导电层和第二导电层，在第一导电层和第二导电层之间设置至少两个在垂直于衬底基板的方向上连续形成的钝化层。设置连续形成的钝化层，便于通过调节钝化层的成分使得第二导电层和与其接触的钝化层之间具有较好的粘附性，可使得各层之间连接性能更稳定。设置连续形成的钝化层，也便于在钝化层中形成凹槽以提高ACF胶非电性连接区的高度差，使得处于凹槽中的各向异性导电胶变形或断裂，从而提高各向异性导电胶的各向异性导电率，以减少显示屏的短路和/或断路。从而，可以提高阵列基板的稳定性、可靠性和信赖性。

Description

阵列基板和显示装置
技术领域
本公开至少一实施例涉及一种阵列基板和显示装置。
背景技术
大尺寸氧化物阵列基板目前处于量产和性能提升阶段，量产的氧化物阵列基板基本上为刻蚀阻挡层(Etching Stop Layer，ESL)结构。虽然刻蚀阻挡层氧化物阵列基板的技术水平已经量产，但是由于氧化物阵列基板的器件信赖性和可靠性问题使得目前产品一直存在补偿方式复杂、繁琐(比如使用光学补偿、内部电学补偿、外部电学补偿等)和寿命有待提高的问题，并且性能有待提升以适用苛刻环境，如军用产品、高温、潮湿环境。
发明内容
本公开的至少一实施例涉及一种阵列基板和显示装置，以提高阵列基板的稳定性、可靠性和信赖性+效果/解决的问题。
本公开的至少一实施例提供一种阵列基板，包括衬底基板和依次设置在所述衬底基板上的第一导电层和第二导电层，其中，在所述第一导电层和所述第二导电层之间设置至少两个在垂直于所述衬底基板的方向上连续形成的钝化层。
本公开的至少一实施例还提供一种显示装置，包括本公开实施例所述的任一阵列基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为ITO与树脂(resin)接触不良的扫描电子显微镜(scanning electronmicroscope，SEM)照片；
图2为邦定区击穿示意图；
图3为本公开一实施例提供的阵列基板的俯视图；
图4为图3的A-B向剖视图；
图5a为本公开一实施例提供的图3的邦定区的一种俯视图；
图5b为本公开一实施例提供的图3的邦定区的另一种俯视图；
图6a为本公开一实施例提供的在衬底基板上形成第三导电层；
图6b为本公开一实施例提供的在第三导电层上形成栅极绝缘层和有源层；
图6c为本公开一实施例提供的在有源层上形成刻蚀阻挡层；
图6d为本公开一实施例提供的在刻蚀阻挡层上形成第一导电层；
图6e为本公开一实施例提供的在第一导电层上形成至少两个在垂直于衬底基板的方向上连续形成的钝化层；
图6f为本公开一实施例提供的在至少两个在垂直于衬底基板的方向上连续形成的钝化层上形成第二导电层；
图7为本公开一实施例提供的一种显示装置(邦定前)的示意图；
图8a为本公开一实施例提供的一种显示装置的邦定区的剖视图；
图8b为本公开一实施例提供的一种显示装置的邦定区(ACF胶具有裂纹)的剖视图；
图9为本公开一实施例提供的一种显示装置(包括显示区和周边区)的剖视图；
附图标记：
01-显示区；02-周边区；021-邦定区；101-衬底基板；106-第一导电层；110-第二导电层；107-第一钝化层；108-第二钝化层；109-第三钝化层；102-第三导电层；1060-第一导电结构；1101-第二导电结构；115-凹槽；1151-凹槽的间隔部；1152-凹槽的连接部；201-电路板；202-连接电极层；2020-连接电极；0301-裂纹；10-阵列基板；20-对置基板。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
通常的阵列基板，包括显示区和设置在显示区至少一侧的周边区。在显示区，作为像素电极的氧化铟锡(ITO)可通过贯穿树脂层的过孔与薄膜晶体管的漏极电连接，像素电极设置在树脂层上，与树脂层接触。但ITO与树脂层的粘附性不好，容易使得ITO与树脂层之间出现接触不良的问题，如图1所示，图1中ITO层01102与树脂层0789的粘附性不好。在周边区，一方面，在显示面板与驱动IC的接口衔接区域(邦定区)，也同样会有类似的ITO层01102与树脂层0789的粘附性不好的问题，易发生断路。另一方面，因挠性板上贴装芯片(Chip OnFilm，COF)(驱动IC)的连接电极与显示面板的邦定区的接线通过各向异性导电胶(Anisotropic Conductive Film，ACF胶)电连接，相邻的两条接线之间的ACF胶需处于非电连接的状态，但因接线之间距离较小，故而容易产生短路，造成击穿，如图2所示，图2中示出了邦定区的击穿区域。通常的阵列基板寿命低，钝化层与电极层粘附性不好，邦定区易发生短路、断路不良。
本公开至少一实施例提供一种阵列基板，包括衬底基板和依次设置在衬底基板上的第一导电层和第二导电层，在第一导电层和第二导电层之间设置至少两个在垂直于衬底基板的方向上连续形成的钝化层。
该阵列基板具有如下至少之一的有益效果。
(1)设置连续形成的钝化层，便于通过调节钝化层的成分使得第二导电层和与其接触的钝化层之间具有较好的粘附性，可使得各层之间连接性能更稳定。
(2)设置连续形成的钝化层，也便于在钝化层中形成凹槽以提高ACF胶的非电性连接区的高度差，使得处于凹槽中的各向异性导电胶变形或断裂，从而提高各向异性导电胶的各向异性导电率，以减少显示屏的短路和/或断路。
从而，可以提高阵列基板的稳定性、可靠性和信赖性。可延长阵列基板使用寿命，拓宽阵列基板使用领域。例如，可改善阵列基板在苛刻条件，如高温高湿环境下阵列基板的寿命和应用范围。
实施例一
本实施例提供一种阵列基板10，如图3所示，包括显示区01和设置在显示区01至少一侧的周边区02，图3中还示出了位于周边区02的邦定区(bonding area)021。例如，邦定区021可被配置来连接外接电路。例如，邦定区021可被配置来与驱动IC相连，例如，可作为柔性电路板引出区。
如图4所示，该阵列基板包括衬底基板101和依次设置在衬底基板101上的第一导电层106和第二导电层110，在第一导电层106和第二导电层110之间设置至少两个在垂直于衬底基板101的方向上连续形成的钝化层。第一导电层106、至少两个钝化层和第二导电层110设置在周边区02。图4中以在第一导电层106和第二导电层110之间设置三个在垂直于衬底基板101的方向上连续形成的钝化层为例进行说明。三个钝化层包括依次设置在衬底基板101上的第一钝化层107、第二钝化层108和第三钝化层109。
本实施例提供的阵列基板10，至少具有如下有益效果：通过设置连续形成的钝化层，可便于通过调节钝化层的成分使得第二导电层和与其接触的钝化层之间具有较好的粘附性，可使得各层之间连接性能更稳定。
例如，如图4所示，第一导电层106包括多个彼此绝缘的第一导电结构1060，第二导电层110包括多个彼此绝缘的第二导电结构1101，多个第一导电结构1060和多个第二导电结构1101一一对应，第二导电结构1101通过贯穿至少两个钝化层的过孔789(图4中未示出，请参见图5a、图5b、图6f和/或图9)与第一导电结构1060电连接(图4中未示出，请参见图6f和/或图9的周边区域02)。
一个示例中，如图4所示，该阵列基板还包括第三导电层102，第三导电层102设置在衬底基板101和第一导电层106之间，并与第一导电层106和第二导电层110电绝缘。
本实施例提供的阵列基板10，至少还具有如下有益效果：通过设置连续形成的钝化层，也便于在钝化层中形成凹槽以提高ACF胶的非电性连接区的高度差，使得处于凹槽中的各向异性导电胶变形或断裂，从而提高各向异性导电胶的各向异性导电率，以减少显示屏的短路和/或断路。
一个示例中，如图4和图5a所示，阵列基板还包括凹槽115，凹槽115贯穿至少两个钝化层中靠近多个第二导电结构1101的至少一个钝化层，并且，至少与多个第一导电结构1060接触的钝化层未被凹槽115贯穿，凹槽115至少包括间隔部1151，在平行于衬底基板101的方向上，间隔部1151位于相邻两个第二导电结构1101之间。图5a中以凹槽115包括间隔部1151为例进行说明。凹槽115的设置，可以提高COF非电性连接区的高度差，使得处于凹槽中的各向异性导电胶断裂，从而提高各向异性导电胶的各向异性导电率，以减少显示屏的短路和/或断路。从而，可以提高阵列基板的稳定性、可靠性和信赖性。可延长阵列基板使用寿命，拓宽阵列基板使用领域。
一个示例中，如图4和图5b所示，凹槽115可至少还包括连接部1152，连接部1152连接相邻两个间隔部1151。连接部1152的设置，可使得ACF胶在更多的凹槽区域具有高度差，从而可使得ACF胶在凹槽处变形或断裂以使得相邻两个第二连接结构1101之间能更好的非电性相连，以避免短路。
一个示例中，靠近第二导电层110的钝化层的材质包括SiNx。SiNx具有较好的粘附性，增加了钝化层与第二导电层110材料的粘附性，从而，可提高导电材料与其连接的连接性能，提高阵列基板的稳定性、可靠性和信赖性。
一个示例中，第一钝化层107材质包括SiOx，第二钝化层108材质包括SiOxNy，第三钝化层109材质包括SiNx。通过调节钝化层的成分使得第二导电层和与其接触的钝化层之间具有较好的粘附性，可使得各层之间连接性能更稳定。
以上以第一导电层106、至少两个钝化层和第二导电层110设置在周边区02为例进行说明。但本实施例并不限于此。
例如，如图6f所示，在显示区01还包括与第一导电层106同层设置的第一电极，以及与第二导电层110同层设置的第二电极1102，第一电极和第二电极之间设置至少两个钝化层，第一电极包括源极1062和漏极1061，第二电极可为像素电极1102或公共电极。像素电极1102可通过贯穿设置在第一导电层106和第二导电层110之间的至少两个钝化层与漏极1061电连接。例如，第一电极和第二电极之间设置三个钝化层：第一钝化层107、第二钝化层108和第三钝化层109。例如，显示区01还包括与第三导电层102同层设置的栅极1021。
一个示例中，第三导电层102为栅极层，显示区的栅极层包括栅极1021，周边区域的第三结构1020可与栅极1021同层形成。第三导电层102之上形成有栅极绝缘层103。图9中还示出了有源层104以及设置在有源层104上的刻蚀阻挡层105。
在第一导电层106和第二导电层110之间还可以设置其他数量的至少两个钝化层，本实施例对此不作限定。
以制作图6f所示的阵列基板为例，本实施例还提供一种阵列基板的制造方法，该阵列基板的制造方法包括如下步骤。
步骤1、在玻璃，塑料(聚酰亚胺)、硅等衬底基板上，使用溅射方法淀积金属层，金属层材质例如可为Mo、Al/Nd、Al/Nd/Mo、Mo/Al/Nd/Mo、Au/Ti、Pt/Ti等金属或合金，并光刻刻蚀，将金属层图形化，得到第三导电层102，第三导电层102包括显示区01的栅极1021(第三导电结构)和周边区02的第三导电结构1020，如图6a所示。
步骤2、形成栅极绝缘层103和有源层104，如图6b所示。例如，栅极绝缘层103可采用常压化学气相沉积、低压化学气相沉积、等离子辅助体化学气相淀积、溅射等制备方法，淀积SiOx、SiNx、SiON、Al2O3、HfO2、ZrO2、TiO2,，Y2O3、La2O3、Ta2O5等单层或多层栅绝缘层。例如，有源层104可采用溅射、溶胶-凝胶、真空蒸镀、喷涂、喷墨打印等方法制备，如氧化铟镓锌IGZO、氮氧化锌ZnON，氧化铟锡锌ITZO，氧化锌锡ZTO、氧化锌铟ZIO、氧化铟镓IGO、氧化铝锌锡AZTO等。
步骤3、形成刻蚀阻挡层105，如图6c所示。例如，可采用原子层沉积、常压化学气相沉积、低压化学气相沉积、等离子辅助体化学气相淀积、溅射，sol-gel等制备方法，淀积SiOx、SiNx、SiON、Al2O3、TEOS等单层或多层结构，并图形化，得到刻蚀阻挡层105。
步骤4、形成第一导电层106，如图6d所示。例如，可使用溅射方法淀积Mo、AlNd、AlNd/Mo、Mo/AlNd/Mo、Au/Ti、Pt/Ti等金属或合金层，并光刻刻蚀，图形化薄膜层，得到第一导电层106。第一导电层106可包括源极1062和漏极1061以及周边区02的第一导电结构1060。
步骤5、形成至少两个在垂直于衬底基板的方向上连续形成的钝化层，如图6e所示。例如，可采用热生长、常压化学气相沉积、低压化学气相沉积、等离子辅助体化学气相淀积、溅射，旋转涂覆等制备方法生长钝化层。例如，可制备SiOx、SiNx、SiOxNy、Al2O3、树脂中的一种或者多种材料或不同组分构成的多层钝化层。
步骤6、形成接触孔和/或凹槽，并形成第二导电层，如图6f所示。例如，可图形化钝化层，刻蚀接触孔和/或凹槽，并溅射透明导电材料，例如，ITO，图形化做电引出，形成第二导电层第二导电层材质不限于ITO。
步骤7、退火处理。例如，可在真空、氮气、空气或氧气环境中对上述产品进行退火，退火温度可以在120-450℃之间，退火时间为0.5小时-3小时。
实施例二
与实施例一不同的是，第一导电层106、至少两个钝化层和第二导电层110仅设置在显示区01。可参照图6f左侧的显示区01。第一导电层106包括多个彼此绝缘的第一导电结构1060，第一导电结构1060可为源极1062和漏极1061。第二导电层110包括多个彼此绝缘的第二导电结构1102，第二导电结构1102可为像素电极。第二导电结构1102可通过贯穿至少两个钝化层的过孔与第一导电结构1060电连接。
一个示例中，第二导电结构1102也可为公共电极。第二导电结构1102为公共电极时，第二导电结构1102与第一导电结构电绝缘。
一个示例中，靠近第二导电层110的钝化层的材质包括SiNx。SiNx具有较好的粘附性，从而，可提高导电材料与其连接的连接性能，提高阵列基板的稳定性、可靠性和信赖性。例如第一导电层106和第二导电层110之间设置三个钝化层，靠近第二导电层110的钝化层是指第三钝化层109。
一个示例中，三个钝化层包括依次设置在衬底基板101上的第一钝化层107、第二钝化层108和第三钝化层109，第一钝化层107材质包括SiOx，第二钝化层108材质包括SiOxNy，第三钝化层109材质包括SiNx。通过调节钝化层的成分使得第二导电层和与其接触的钝化层之间具有较好的粘附性，可使得各层之间连接性能更稳定。
实施例三
本实施例提供一种显示装置，包括实施例一至二所述的任一阵列基板。
例如，显示装置包括液晶显示装置或有机发光二极管显示装置，但不限于此。
例如，显示装置可包括电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等显示装置。
以下以显示装置为液晶显示装置为例进行说明。当显示装置采用液晶显示装置时，可采用ADS、HADS、TN、VA等各种模式，本实施例对此不作限定。
一个示例中，如图7所示，可将阵列基板10与对置基板20对盒，并在其间形成液晶层(图中未示出液晶层)，暴露出邦定区021。例如，如图8a所示，显示装置还包括电路板201，电路板201上设置有连接电极层202，连接电极层202包括多个彼此绝缘的连接电极2020，多个连接电极2020与多个第二导电结构1101一一对应，连接电极2020通过各向异性导电胶301与第二导电结构1101电连接。例如，电路板201可为柔性电路板，柔性电路板上可贴装芯片，即形成COF，但不限于此。
例如，各向异性导电胶301位于连接电极2020和与该连接电极2020对应的第二导电结构1101之间的部分为电连接区3011，各向异性导电胶301位于相邻两个连接电极2020之间的部分为非电连接区3012。例如，各向异性导电胶301内设置有多个导电粒子，每个导电粒子外可包裹绝缘层，从而，在热压后可形成电连接区3011和非电连接区3012。电连接区3011的各向异性导电胶301在其厚度方向上导电，在平行于其表面的方向不导电。
在第一导电层106和第二导电层110之间设置至少两个在垂直于衬底基板101的方向上连续形成的钝化层，从而，提高了第二导电层110与COF非电性连接区的高度差，凹槽115的设置，在不需要电连接的位置，形成较大的坡度角，从而，如图8b所示，可使得各向异性导电胶301在位于凹槽115内的部分断裂，以增大非接触区电阻。即各向异性导电胶301在位于凹槽115内的部分具有裂纹0301。例如，如图8b所示，裂纹0301可形成在凹槽的边缘，例如，裂纹0301可在凹槽115的爬坡位置处(凹槽内的第一钝化层107靠近第二钝化层108的位置处)形成，但不限于此。例如，裂纹0301可也可以形成在凹槽115的第二钝化层108和第三钝化层109处。例如，利用热塑性在230度以内的合适延展性的ACF胶在凹槽处(台阶处)形变或断裂来提高ACF胶非电连接区3012的各向异性导电率，改善COF的电性连接，可以减少显示屏的短路和断路。该阵列基板在制作时可不新增加掩模板(Mask)，有利于成本控制。
图9示出了采用图6f所示的显示基板形成的显示装置的示意图。
本公开的实施例以COF与邦定区的接线电连接为例进行说明，但驱动IC不限于COF，还可以为其他形式，本公开的实施例对此不作限定。
这里应该理解的是，在本公开的实施例中，“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
在本公开的实施例中，构图或构图工艺可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤，或者可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程，利用光刻胶、掩模板、曝光机等形成图形。可根据本公开的实施例中所形成的结构选择相应的构图工艺。
有以下几点需要说明：
(1)除非另作定义，本公开实施例以及附图中，同一附图标记代表同一含义。
(2)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(3)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。连续形成的层之间没有其他中间层或中间元件。
(4)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

1.一种阵列基板，包括衬底基板和依次设置在所述衬底基板上的第一导电层和第二导电层，其中，在所述第一导电层和所述第二导电层之间设置至少两个在垂直于所述衬底基板的方向上连续形成的钝化层。
2.根据权利要求1所述的阵列基板，还包括第三导电层，其中，所述第三导电层设置在所述衬底基板和所述第一导电层之间，并与所述第一导电层和所述第二导电层电绝缘。
3.根据权利要求1所述的阵列基板，其中，所述第一导电层包括多个彼此绝缘的第一导电结构，所述第二导电层包括多个彼此绝缘的第二导电结构，所述多个第一导电结构和所述多个第二导电结构一一对应，所述第二导电结构通过贯穿所述至少两个钝化层的过孔与所述第一导电结构电连接。
4.根据权利要求3所述的阵列基板，还包括凹槽，其中，所述凹槽贯穿所述至少两个钝化层中靠近所述多个第二导电结构的至少一个钝化层，并且，至少一个与所述多个第一导电结构接触的钝化层未被所述凹槽贯穿，所述凹槽至少包括间隔部，在平行于所述衬底基板的方向上，所述间隔部位于相邻两个第二导电结构之间。
5.根据权利要求4所述的阵列基板，其中，所述凹槽至少还包括连接部，所述连接部连接相邻两个所述间隔部。
6.根据权利要求1-5任一项所述的阵列基板，其中，靠近所述第二导电层的钝化层的材质包括SiNx。
7.根据权利要求1-5任一项所述的阵列基板，其中，所述第一导电层和所述第二导电层之间设置三个钝化层，所述三个钝化层包括依次设置在所述衬底基板上的第一钝化层、第二钝化层和第三钝化层，所述第一钝化层材质包括SiOx，所述第二钝化层材质包括SiOxNy，所述第三钝化层材质包括SiNx。
8.根据权利要求1-5任一项所述的阵列基板，其中，所述阵列基板包括显示区和设置在所述显示区至少一侧的周边区，所述第一导电层、所述至少两个钝化层和所述第二导电层设置在所述周边区。
9.根据权利要求8所述的阵列基板，其中，在所述显示区还包括与所述第一导电层同层设置的第一电极，以及与所述第二导电层同层设置的第二电极，所述第一电极和所述第二电极之间设置所述至少两个钝化层，所述第一电极包括源极和漏极，所述第二电极为像素电极或公共电极。
10.根据权利要求1所述的阵列基板，其中，所述阵列基板包括显示区和设置在所述显示区至少一侧的周边区，所述第一导电层、所述至少两个钝化层和所述第二导电层设置在所述显示区。
11.根据权利要求10所述的阵列基板，其中，靠近所述第二导电层的钝化层的材质包括SiNx。
12.根据权利要求10所述的阵列基板，其中，所述第一导电层和所述第二导电层之间设置三个钝化层，所述三个钝化层包括依次设置在所述衬底基板上的第一钝化层、第二钝化层和第三钝化层，所述第一钝化层材质包括SiOx，所述第二钝化层材质包括SiOxNy，所述第三钝化层材质包括SiNx。
13.一种显示装置，包括权利要求1-12任一项所述的阵列基板。
14.根据权利要求13所述的显示装置，还包括电路板，其中，所述电路板上设置有连接电极层，所述连接电极层包括多个彼此绝缘的连接电极，所述多个连接电极与所述多个第二导电结构一一对应，所述连接电极通过各向异性导电胶与所述第二导电结构电连接。
15.根据权利要求13所述的显示装置，其中，所述各向异性导电胶位于所述凹槽内的部分具有裂纹。
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