CN106449365A - Rework method for avoiding rear-stage intermetallic dielectric layer embedded particle defects - Google Patents

Rework method for avoiding rear-stage intermetallic dielectric layer embedded particle defects Download PDF

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Publication number
CN106449365A
CN106449365A CN201610985518.4A CN201610985518A CN106449365A CN 106449365 A CN106449365 A CN 106449365A CN 201610985518 A CN201610985518 A CN 201610985518A CN 106449365 A CN106449365 A CN 106449365A
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China
Prior art keywords
dielectric layer
type grain
back segment
grain defect
metal dielectric
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Pending
Application number
CN201610985518.4A
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Chinese (zh)
Inventor
谢素兰
李健
许隽
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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Priority to CN201610985518.4A priority Critical patent/CN106449365A/en
Publication of CN106449365A publication Critical patent/CN106449365A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a rework method for avoiding rear-stage intermetallic dielectric layer embedded particle defects. The rework method includes: step 1, detecting embedded particle defects after a process of forming a metal titanium nitride mask on a silicon dioxide covered layer; step 2, removing the metal titanium nitride mask through etching; step 3, flattening the silicon dioxide covered layer; step 4, growing silicon dioxide on the flattened silicon dioxide covered layer to enable thickness of the flattened silicon dioxide covered layer to reach a target value.

Description

A kind of reworking method for solving back segment inter-metal dielectric layer baried type grain defect
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of solve electricity Jie between back segment metal The reworking method of matter layer baried type grain defect.
Background technology
Current 55 Nano semiconductor integrated circuit fabrication process back segment inter-metal dielectric layer typically has three to five layers, per layer Film stack pattern be：Silicon carbide barrier layer/low-k silicon dioxide layer/silicon dioxide mask/nitride metal titanium is covered Mould/silicon dioxide is covered, and any one website in five layer films deposition is likely to produce grain defect problem, if Deposition finds surface defect when station, can be done over again by the method for scrubber, crystal column surface granule is rinsed out, but such as Fruit be baried type grain defect, granule a part of buried in the film between, as shown in figure 1, such case scrubber can not send out The effect of waving, then can only directly discharge the batch or scrap wafer, not have any other flow process of doing over again.Thus cause greatly Product yield loss and cost.
Accordingly, it is desirable to a kind of reworking method for solving back segment inter-metal dielectric layer baried type grain defect can be provided.
Content of the invention
The technical problem to be solved is there is drawbacks described above in prior art, provides one kind and can solve the problem that The reworking method of back segment inter-metal dielectric layer baried type grain defect.
In order to realize above-mentioned technical purpose, according to the present invention, there is provided a kind of back segment inter-metal dielectric layer that solves is imbedded The reworking method of type grain defect, including：
First step：After the technique that nitride metal titanium mask is formed on silica overlayer detect baried type Grain defect；
Second step：Nitride metal titanium mask is removed by etching；
Third step：So that silica overlayer planarization；
Four steps：Silicon dioxide growth is carried out to the silica overlayer for planarizing so that the titanium dioxide of planarization The thickness of silicon covering layer reaches target thickness.
Preferably, third step causes silica overlayer to planarize by cmp.
Preferably, third step causes the thickness of silica overlayer thinning.
Preferably, the thickness of the silica overlayer before target thickness is cmp.
In order to above-mentioned technical purpose is realized, according to the present invention, additionally provide a kind of back segment inter-metal dielectric layer that solves and bury Enter the reworking method of type grain defect, including：
First step：Baried type grain defect is detected after the technique for forming silica overlayer；
Second step：So that silica overlayer planarization；
Third step：Silicon dioxide growth is carried out to the silica overlayer for planarizing so that the titanium dioxide of planarization The thickness of silicon covering layer reaches target thickness.
Preferably, second step causes silica overlayer to planarize by cmp.
Preferably, second step causes the thickness of silica overlayer thinning.
Preferably, the thickness of the silica overlayer before target thickness is cmp.
The invention provides a kind of reworking method for solving back segment inter-metal dielectric layer baried type grain defect, can solve The yield that certainly back segment inter-metal dielectric layer baried type grain defect is caused reduces problem.
Description of the drawings
In conjunction with accompanying drawing, and by reference to detailed description below, it will more easily have more complete understanding to the present invention And its adjoint advantages and features is more easily understood, wherein：
Fig. 1 schematically shows the microscopic view of baried type grain defect.
Fig. 2 schematically shows and is imbedded according to the solution back segment inter-metal dielectric layer of first preferred embodiment of the invention The first step of the reworking method of type grain defect.
Fig. 3 schematically shows and is imbedded according to the solution back segment inter-metal dielectric layer of first preferred embodiment of the invention The second step of the reworking method of type grain defect.
Fig. 4 schematically shows and is imbedded according to the solution back segment inter-metal dielectric layer of first preferred embodiment of the invention The third step of the reworking method of type grain defect.
Fig. 5 schematically shows and is imbedded according to the solution back segment inter-metal dielectric layer of first preferred embodiment of the invention The four steps of the reworking method of type grain defect.
Fig. 6 schematically shows and is imbedded according to the solution back segment inter-metal dielectric layer of second preferred embodiment of the invention The first step of the reworking method of type grain defect.
Fig. 7 schematically shows and is imbedded according to the solution back segment inter-metal dielectric layer of second preferred embodiment of the invention The second step of the reworking method of type grain defect.
Fig. 8 schematically shows and is imbedded according to the solution back segment inter-metal dielectric layer of second preferred embodiment of the invention The third step of the reworking method of type grain defect.
It should be noted that accompanying drawing is used for the present invention to be described, and the unrestricted present invention.Note, represent that the accompanying drawing of structure can Can be not necessarily drawn to scale.Also, in accompanying drawing, same or like element indicates same or like label.
Specific embodiment
In order that present disclosure is more clear and understandable, with reference to specific embodiments and the drawings in the present invention Appearance is described in detail.
The reason for yield that the baried type grain defect of the present inventor's analysis inter-metal dielectric layer is caused reduces, Substantially as the projection of baried type grain defect has influence on the graph exposure of follow-up photoetching, copper cash disconnection is ultimately resulted in, if Inter-metal dielectric layer surface rubbing can be carried out according still further to former technique stack manner after wafer has baried type grain defect Do over again, then do not have this problem.
Will be detailed below the preferred embodiments of the present invention.
<First preferred embodiment>
Fig. 2 to Fig. 5 schematically shows the solution back segment inter-metal dielectric according to first preferred embodiment of the invention Each step of the reworking method of layer baried type grain defect.
As shown in Figures 2 to 5, solution back segment inter-metal dielectric layer baried type granule according to the preferred embodiment of the invention The reworking method of defect includes：
First step：After the technique that nitride metal titanium mask 30 is formed on silica overlayer 20 detect embedment Type grain defect 10；
Second step：Nitride metal titanium mask 30 is removed by etching；
Third step：So that silica overlayer 20 is planarized；
Typically, third step causes silica overlayer 20 to planarize by cmp.
Wherein, third step causes the thickness of silica overlayer 20 thinning.
Four steps：Silicon dioxide growth is carried out to the silica overlayer 20 for planarizing so that the dioxy of planarization The thickness of SiClx cover layer 20 reaches target thickness.
For example, the thickness of the silica overlayer 20 before target thickness is cmp.
Thus, the invention provides a kind of solve back segment inter-metal dielectric layer baried type grain defect reworking method, Can solve the problem that the yield that back segment inter-metal dielectric layer baried type grain defect is caused reduces problem.
<Second preferred embodiment>
Fig. 6 to Fig. 8 schematically shows the solution back segment inter-metal dielectric according to second preferred embodiment of the invention Each step of the reworking method of layer baried type grain defect.
As shown in Figure 6 to 8, solution back segment inter-metal dielectric layer baried type granule according to the preferred embodiment of the invention The reworking method of defect includes：
First step：Baried type grain defect is detected after the technique for forming silica overlayer；
Second step：So that silica overlayer 20 is planarized；
Typically, second step causes silica overlayer 20 to planarize by cmp.
Wherein, second step causes the thickness of silica overlayer 20 thinning.
Third step：Silicon dioxide growth is carried out to the silica overlayer 20 for planarizing so that the dioxy of planarization The thickness of SiClx cover layer 20 reaches target thickness.
For example, the thickness of the silica overlayer 20 before target thickness is cmp.
Equally, thus, the invention provides a kind of solve doing over again for back segment inter-metal dielectric layer baried type grain defect Method, can solve the problem that the yield that back segment inter-metal dielectric layer baried type grain defect is caused reduces problem.
The invention provides a kind of reworking method for solving back segment inter-metal dielectric layer baried type grain defect, can solve The yield that certainly back segment inter-metal dielectric layer baried type grain defect is caused reduces problem.
Furthermore, it is necessary to illustrate, unless stated otherwise or point out, term " first " otherwise in description, " Two ", the description such as " 3rd " is used only for each component in differentiation description, element, step etc., rather than for representing each Logical relation or ordering relation between component, element, step etc..
It is understood that although the present invention is disclosed as above with preferred embodiment, but above-described embodiment it is not used to Limit the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit, Many possible variations being made all to technical solution of the present invention using the technology contents of the disclosure above and modify, or is revised as Equivalent embodiments with change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention Any simple modification made for any of the above embodiments, equivalent variations and modification, all still fall within the scope of technical solution of the present invention protection Interior.
And it should also be understood that the present invention is not limited to specific method described herein, compound, material, system Technology, usage and application is made, they can change.It should also be understood that term described herein be used merely to describe specific Embodiment, rather than be used for limiting the scope of the present invention.Must be noted that herein and claims used in Singulative " one ", " one kind " and " being somebody's turn to do " include complex reference, unless context explicitly indicates that contrary.Therefore, example Such as, the citation to one or more elements is meaned to the citation of " element ", and including known to those skilled in the art Its equivalent.Similarly, as another example, the citation of " step " or " device " is meaned to one or Multiple steps or the citation of device, and potentially include secondary step and second unit.Should be managed with broadest implication All conjunctions that solution is used.Therefore, word "or" should be understood that the definition with logical "or", rather than logical exclusive-OR Definition, unless context explicitly indicates that contrary.Structure described herein will be understood as also quoting from the function of the structure Equivalent.Can be interpreted that approximate language should be understood like that, unless context explicitly indicates that contrary.
And, the method for the embodiment of the present invention and/or the realization of system may include manual, automatic or execute in combination selected Task.And, the real instrument of the embodiment of the method according to the invention and/or system and equipment are logical using operating system Cross hardware, software or its combination and realize several selected tasks.

Claims (8)

1. a kind of solve back segment inter-metal dielectric layer baried type grain defect reworking method, it is characterised in that include：
First step：Baried type granule is detected after the technique for forming nitride metal titanium mask on silica overlayer to lack Fall into；
Second step：Nitride metal titanium mask is removed by etching；
Third step：So that silica overlayer planarization；
Four steps：Silicon dioxide growth is carried out to the silica overlayer for planarizing so that the silicon dioxide of planarization covers The thickness of cap rock reaches target thickness.
2. the reworking method for solving back segment inter-metal dielectric layer baried type grain defect according to claim 1, which is special Levy and be, third step causes silica overlayer to planarize by cmp.
3. according to claim 1 and 2 solve back segment inter-metal dielectric layer baried type grain defect reworking method, its It is characterised by, third step causes the thickness of silica overlayer thinning.
4. according to claim 1 and 2 solve back segment inter-metal dielectric layer baried type grain defect reworking method, its Be characterised by, target thickness be cmp before silica overlayer thickness.
5. a kind of solve back segment inter-metal dielectric layer baried type grain defect reworking method, it is characterised in that include：
First step：Baried type grain defect is detected after the technique for forming silica overlayer；
Second step：So that silica overlayer planarization；
Third step：Silicon dioxide growth is carried out to the silica overlayer for planarizing so that the silicon dioxide of planarization covers The thickness of cap rock reaches target thickness.
6. the reworking method for solving back segment inter-metal dielectric layer baried type grain defect according to claim 5, which is special Levy and be, second step causes silica overlayer to planarize by cmp.
7. according to claim 5 or 6 solution back segment inter-metal dielectric layer baried type grain defect reworking method, its It is characterised by, second step causes the thickness of silica overlayer thinning.
8. according to claim 5 or 6 solution back segment inter-metal dielectric layer baried type grain defect reworking method, its Be characterised by, target thickness be cmp before silica overlayer thickness.
CN201610985518.4A 2016-11-09 2016-11-09 Rework method for avoiding rear-stage intermetallic dielectric layer embedded particle defects Pending CN106449365A (en)

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Application Number Priority Date Filing Date Title
CN201610985518.4A CN106449365A (en) 2016-11-09 2016-11-09 Rework method for avoiding rear-stage intermetallic dielectric layer embedded particle defects

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Application Number Priority Date Filing Date Title
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101178995A (en) * 2006-11-10 2008-05-14 富士通日立等离子显示器股份有限公司 Method for producing substrate assembly for plasma display panel
CN101562147A (en) * 2008-04-18 2009-10-21 和舰科技(苏州)有限公司 Method for removing residual defects
KR20110001092A (en) * 2009-06-29 2011-01-06 주식회사 하이닉스반도체 Method of manufacturing a semiconductor memory device
US9097994B2 (en) * 2012-01-27 2015-08-04 Sematech, Inc. Abrasive-free planarization for EUV mask substrates

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101178995A (en) * 2006-11-10 2008-05-14 富士通日立等离子显示器股份有限公司 Method for producing substrate assembly for plasma display panel
CN101562147A (en) * 2008-04-18 2009-10-21 和舰科技(苏州)有限公司 Method for removing residual defects
KR20110001092A (en) * 2009-06-29 2011-01-06 주식회사 하이닉스반도체 Method of manufacturing a semiconductor memory device
US9097994B2 (en) * 2012-01-27 2015-08-04 Sematech, Inc. Abrasive-free planarization for EUV mask substrates

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