US20070120259A1 - Detection of residual liner materials after polishing in damascene process - Google Patents

Detection of residual liner materials after polishing in damascene process Download PDF

Info

Publication number
US20070120259A1
US20070120259A1 US11/669,180 US66918007A US2007120259A1 US 20070120259 A1 US20070120259 A1 US 20070120259A1 US 66918007 A US66918007 A US 66918007A US 2007120259 A1 US2007120259 A1 US 2007120259A1
Authority
US
United States
Prior art keywords
layer
liner
marker
over
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/669,180
Inventor
Ronald Filippi
Roy Iggulden
Edward Kiewra
Stephen Loh
Ping-Chuan Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US11/669,180 priority Critical patent/US20070120259A1/en
Publication of US20070120259A1 publication Critical patent/US20070120259A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/24—Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the embodiments of the invention generally relate to integrated circuit manufacturing, and more particularly to techniques for identifying defects in integrated circuits during manufacturing.
  • Damascene processing typically involves the deposition of liner films between metal and insulating layers. These liner films should generally be completely removed in non-damascene areas in a subsequent chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • the CMP process typically does not adequately remove all of the liner material due to the local topography from circuit pattern factors and defects, which are both compounded by the general non-uniformity of the CMP process.
  • the residual liner films in between the metal layers in an integrated circuit device cannot be detected during standard inspections thereby causing metal shorting of various structures in the device, which cause significant major yield loss and reliability failure of the device.
  • the residual liner films were easily detectable during a subsequent inspection process.
  • typical residual films appear transparent when viewed by optical inspection. Thus, they generally cannot be detected by routine optical inspection. Therefore, there remains a need for a novel technique that allows for easier and more precise inspections of damascene structures.
  • an embodiment of the invention provides an integrated circuit comprising a substrate; a dielectric layer over and adjacent to the substrate; a marker layer over and adjacent to the dielectric layer; a liner over and adjacent to the marker layer; and a metal layer over and adjacent to the liner, wherein the marker layer comprises an ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer.
  • the marker layer comprises a separate layer from the dielectric layer.
  • the ultraviolet detectable material comprises fluorescent material or phosphorescent material.
  • Another embodiment of the invention provides a method of detecting whether post-CMP (chemical mechanical polishing) defects exist in an integrated circuit, wherein the method comprises depositing a dielectric layer over a substrate; forming a marker layer over the dielectric layer, wherein the marker layer comprises an ultraviolet detectable material; patterning the marker layer and the dielectric layer thereby creating exposed portions of the dielectric layer; depositing a liner over the marker layer and the exposed portions of the dielectric layer; depositing a metal layer over the liner; polishing the metal layer and the liner; and exposing the marker layer to an ultraviolet ray, wherein detection of the ultraviolet detectable material by the ultraviolet ray signals an absence of the metal layer and the liner over the marker layer.
  • CMP chemical mechanical polishing
  • the method further comprises configuring the marker layer as a separate layer from the dielectric layer.
  • the ultraviolet detectable material comprises fluorescent material or phosphorescent material. Additionally, the method further comprises re-polishing the liner upon non-detection of the ultraviolet detectable material by the ultraviolet ray. Furthermore, the marker layer signals an endpoint for CMP processing during fabrication of the integrated circuit.
  • the method further comprises analyzing polishing slurry effluent generated from the polishing process for a presence/absence of the ultraviolet detectable material, wherein detection/non-detection of the ultraviolet detectable material in the polishing slurry effluent signals an endpoint for CMP processing during fabrication of the integrated circuit.
  • Another aspect of the invention provides a method of detecting whether post-CMP (chemical mechanical polishing) defects exist in an integrated circuit, wherein the method comprises depositing a dielectric layer over a substrate; forming a marker layer comprising an ultraviolet detectable material over the dielectric layer; patterning the marker layer and the dielectric layer thereby creating exposed portions of the dielectric layer; depositing a liner over the marker layer and the exposed portions of the dielectric layer; depositing a metal layer over the liner; and polishing the metal layer and liner and the marker layer.
  • CMP chemical mechanical polishing
  • the method further comprises exposing the dielectric layer to an ultraviolet light; and detecting whether the liner and the marker layer are present over the dielectric layer, wherein detection of the ultraviolet detectable material by the ultraviolet light signals a presence of the liner and the marker layer over the dielectric layer. Moreover, the method further comprises configuring the marker layer as a separate layer from the dielectric layer.
  • the ultraviolet detectable material comprises fluorescent material or phosphorescent material.
  • the method further comprises re-polishing the liner and the marker layer upon detection of the ultraviolet detectable material by the ultraviolet light; and analyzing polishing slurry effluent generated from the polishing process for a presence/absence of the ultraviolet detectable material, wherein detection/non-detection of the ultraviolet detectable material in the polishing slurry effluent signals an endpoint for CMP processing during fabrication of the integrated circuit.
  • the advantages afforded by the embodiments of the invention include improved process yield, performance, and reliability. Moreover, the embodiments of the invention also provide a low-cost improvement, which may reduce overall processing time by limiting the number of rework or CMP “touch-up” steps. By monitoring the CMP slurry for lack of marker material after the marker material is first detected, overpolishing of the damascene lines (which would result in higher resistance wires) can also be reduced.
  • FIG. 1 is a schematic diagram of a partially completed integrated circuit according to an embodiment of the invention
  • FIG. 2 is a schematic diagram of a partially completed integrated circuit following dual-damascene patterning according to an embodiment of the invention
  • FIG. 3 is a schematic diagram of a partially completed integrated circuit following liner deposition according to an embodiment of the invention.
  • FIG. 4 is a schematic diagram of a partially completed integrated circuit following metallization deposition according to an embodiment of the invention.
  • FIG. 5 is a schematic diagram of a partially completed integrated circuit following polishing according to a first embodiment of the invention.
  • FIG. 6 is a schematic diagram of a partially completed integrated circuit being exposed to ultraviolet rays according to a first embodiment of the invention
  • FIG. 7 is a flow diagram illustrating a preferred method according to a first embodiment of the invention.
  • FIG. 8 is a schematic diagram of a partially completed integrated circuit following polishing according to a second embodiment of the invention.
  • FIG. 9 is a schematic diagram of a partially completed integrated circuit being exposed to ultraviolet light according to a second embodiment of the invention.
  • FIG. 10 is a flow diagram illustrating a preferred method according to a second embodiment of the invention.
  • FIGS. 1 through 10 where similar reference characters denote corresponding features consistently throughout the figures, there are shown preferred embodiments of the invention.
  • FIG. 1 illustrates an integrated circuit 5 embodied as a damascene stack, which comprises a substrate 10 , which may comprise a single-crystal silicon layer, or alternatively, the substrate 10 may comprise any appropriate semiconducting material, including, but not limited to silicon (Si), germanium (Ge), gallium phosphide (GaP), indium arsenide (InAs), indium phosphide (InP), silicon germanium (SiGe), gallium arsenide (GaAs), or other semiconductors.
  • an interlevel dielectric layer 20 is deposited over the substrate 10 .
  • the dielectric layer 20 may comprise silicon oxide, FTEOS (silicon oxide with fluorine impurities), Silk® (available from Dow Chemical Company, Midland, Mich., USA), SiCOH (carbon-doped oxide), and with or without a hardmask layer (not shown).
  • a marker layer 30 is deposited on top of dielectric layer 20 .
  • the marker layer 30 comprises a fluorescent or phosphorescent material, such as phosphor, which is detectable upon exposing the marker layer 30 to an ultraviolet light.
  • the damascene stack 5 is patterned using any typical lithography and etching techniques known in the art, thereby creating a void 35 in the damascene stack 5 .
  • the damascene stack 5 undergoes a metallization process, which involves the deposition of a liner 40 over all exposed surfaces of the damascene stack 5 including the exposed surfaces in the void 35 .
  • the liner film 40 may comprise tungsten (W), titanium nitride (TiN) tantalum (Ta), and tantalum nitride (TaN).
  • a plating metal 50 such as copper (Cu) is deposited over the liner 40 thereby filling the void 35 .
  • the next step involves performing a CMP process on the metal layer 50 and liner film 40 as shown in FIG. 5 .
  • the CMP is endpointed by using the phosphor concentration in the slurry (not shown).
  • an overpolishing process is performed. Alternatively, one may endpoint when the slurry is no longer fluorescing.
  • the overpolishing process is designed to stop on the marker layer 30 .
  • the damascene stack 5 can be quickly examined with ultraviolet light (ray) to look for fluorescence or phosphorescence in the damascene stack 5 as indicated in FIG. 6 . If there are areas with no fluorescence or phosphorescence, then this indicates that there is still residual metal 50 or liner 40 (i.e., incomplete CMP) over the marker layer 30 .
  • the damascene structure 5 i.e., wafer
  • the damascene structure 5 should be reworked with a touch up CMP process and can be re-examined. This process can continue until no residual metal 50 or liner 40 remains over the marker layer 30 .
  • FIG. 7 illustrates the process flow according to the first embodiment of the invention.
  • FIG. 7 illustrates, with reference to FIGS. 1 through 6 , a method of detecting whether post-CMP (chemical mechanical polishing) defects exist in an integrated circuit 5 , wherein the method comprises depositing ( 101 ) a dielectric layer 20 over and adjacent to a substrate 10 ; forming ( 103 ) a marker layer 30 over and adjacent to the dielectric layer 20 , wherein the marker layer 30 comprises an ultraviolet detectable material; patterning ( 105 ) the marker layer 30 and the dielectric layer 20 thereby creating exposed portions of the dielectric layer 20 ; depositing ( 107 ) a liner 40 over and adjacent to the marker layer 30 and the exposed portions of the dielectric layer 20 ; depositing ( 109 ) a metal layer 50 over and adjacent to the liner 40 ; polishing ( 111 ) the metal layer 50 and the liner 40 ; and exposing ( 113 ) the marker layer 30 to an ultraviolet ray, wherein detection of the ultraviolet detectable material
  • the method further comprises configuring the marker layer 30 as a separate layer from the dielectric layer 20 .
  • the ultraviolet detectable material comprises fluorescent material or phosphorescent material.
  • the marker layer 30 signals an endpoint for CMP processing during fabrication of the integrated circuit 5 .
  • the method further comprises analyzing polishing slurry effluent (not shown) generated from the polishing process ( 111 ) for a presence of the ultraviolet detectable material, wherein detection of the ultraviolet detectable material in the polishing slurry effluent signals an endpoint for CMP processing during fabrication of the integrated circuit 5 .
  • the method further comprises analyzing polishing slurry effluent (not shown) generated from the polishing process ( 111 ) for an absence of the ultraviolet detectable material, wherein non-detection of the ultraviolet detectable material in the polishing slurry effluent signals an endpoint for CMP processing during fabrication of the integrated circuit 5 .
  • FIGS. 8 through 10 A second embodiment of the invention is illustrated in FIGS. 8 through 10 .
  • the first and second embodiments are similar up through FIG. 4 , which is the end of the metallization process.
  • the marker layer 30 does not act as a polishing stop layer, but instead, is polished away completely as shown in FIG. 8 .
  • the sudden presence or, alternatively, absence of phosphor in the slurry can also be used as a reference point for endpointing the process.
  • ultraviolet light is used to check for the presence or absence of fluorescence or phosphorescence, as illustrated in FIG. 9 .
  • FIG. 10 illustrates the process flow according to the second embodiment of the invention.
  • FIG. 10 illustrates, with reference to FIGS. 1 through 4 and FIGS. 8 and 9 , a method of detecting whether post-CMP (chemical mechanical polishing) defects exist in an integrated circuit 5 , wherein the method comprises depositing ( 201 ) a dielectric layer 20 over and adjacent to a substrate 10 ; forming ( 203 ) a marker layer 30 comprising an ultraviolet detectable material over and adjacent to the dielectric layer 20 ; patterning ( 205 ) the marker layer 30 and the dielectric layer 20 thereby creating exposed portions of the dielectric layer 20 ; depositing ( 207 ) a liner 40 over the marker layer 30 ; depositing ( 209 ) a metal layer 50 over and adjacent to the liner 40 ; and polishing ( 211 ) the metal layer 50 , the liner 40 , and the marker layer 30 .
  • CMP chemical mechanical polishing
  • the method further comprises exposing ( 213 ) the dielectric layer 20 to an ultraviolet light, and detecting ( 215 ) whether the liner 40 and the marker layer 30 are present over the dielectric layer 20 , wherein detection of the ultraviolet detectable material by the ultraviolet light signals a presence of the liner 40 and the marker layer 30 over the dielectric layer 20 . Furthermore, the method comprises re-polishing ( 217 ) the liner 40 and the marker layer 30 upon detection of the ultraviolet detectable material by the ultraviolet light.
  • the method according to the second embodiment further comprises configuring the marker layer 30 as a separate layer from the dielectric layer 20 .
  • the ultraviolet detectable material comprises fluorescent material or phosphorescent material.
  • the method according to the second embodiment further comprises analyzing polishing slurry effluent (not shown) generated from the polishing process for a presence or, alternatively, an absence of the ultraviolet detectable material, wherein detection or, alternatively, non-detection of the ultraviolet detectable material in the polishing slurry effluent signals an endpoint for CMP processing during fabrication of the integrated circuit 5 .
  • the detection method provided by the embodiments of the invention is intended to determine whether metal 50 or liner 40 materials remain only over the marker layer 30 .
  • the liner 40 will remain in the integrated circuit 5 in areas protected by the metal layer 50 , which are generally referred to as the “damascene” regions of the integrated circuit 5 . It is in the “non-damascene” regions where shorting can occur if liner 40 or metal 50 remains, as such, it is in the “non-damascene” regions where the ultraviolet detection occurs.
  • the advantages afforded by the embodiments of the invention include improved process yield, performance, and reliability. Moreover, the embodiments of the invention also provide a low-cost improvement, which may reduce overall processing time by limiting the number of rework or CMP “touch-up” steps. By monitoring the CMP slurry for lack of marker material after the marker material is first detected, overpolishing of the damascene lines (which would result in higher resistance wires) can also be reduced.

Abstract

A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a division of U.S. application Ser. No. 10/904,329 filed Nov. 4, 2004.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The embodiments of the invention generally relate to integrated circuit manufacturing, and more particularly to techniques for identifying defects in integrated circuits during manufacturing.
  • 2. Description of the Related Art
  • Damascene processing typically involves the deposition of liner films between metal and insulating layers. These liner films should generally be completely removed in non-damascene areas in a subsequent chemical mechanical polishing (CMP) process. However, the CMP process typically does not adequately remove all of the liner material due to the local topography from circuit pattern factors and defects, which are both compounded by the general non-uniformity of the CMP process.
  • Usually, the residual liner films in between the metal layers in an integrated circuit device cannot be detected during standard inspections thereby causing metal shorting of various structures in the device, which cause significant major yield loss and reliability failure of the device. Undoubtedly, it would be quite advantageous if the residual liner films were easily detectable during a subsequent inspection process. However, typical residual films appear transparent when viewed by optical inspection. Thus, they generally cannot be detected by routine optical inspection. Therefore, there remains a need for a novel technique that allows for easier and more precise inspections of damascene structures.
    • SUMMARY OF THE INVENTION
  • In view of the foregoing, an embodiment of the invention provides an integrated circuit comprising a substrate; a dielectric layer over and adjacent to the substrate; a marker layer over and adjacent to the dielectric layer; a liner over and adjacent to the marker layer; and a metal layer over and adjacent to the liner, wherein the marker layer comprises an ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.
  • Another embodiment of the invention provides a method of detecting whether post-CMP (chemical mechanical polishing) defects exist in an integrated circuit, wherein the method comprises depositing a dielectric layer over a substrate; forming a marker layer over the dielectric layer, wherein the marker layer comprises an ultraviolet detectable material; patterning the marker layer and the dielectric layer thereby creating exposed portions of the dielectric layer; depositing a liner over the marker layer and the exposed portions of the dielectric layer; depositing a metal layer over the liner; polishing the metal layer and the liner; and exposing the marker layer to an ultraviolet ray, wherein detection of the ultraviolet detectable material by the ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. The method further comprises configuring the marker layer as a separate layer from the dielectric layer. In the step of forming, the ultraviolet detectable material comprises fluorescent material or phosphorescent material. Additionally, the method further comprises re-polishing the liner upon non-detection of the ultraviolet detectable material by the ultraviolet ray. Furthermore, the marker layer signals an endpoint for CMP processing during fabrication of the integrated circuit. The method further comprises analyzing polishing slurry effluent generated from the polishing process for a presence/absence of the ultraviolet detectable material, wherein detection/non-detection of the ultraviolet detectable material in the polishing slurry effluent signals an endpoint for CMP processing during fabrication of the integrated circuit.
  • Another aspect of the invention provides a method of detecting whether post-CMP (chemical mechanical polishing) defects exist in an integrated circuit, wherein the method comprises depositing a dielectric layer over a substrate; forming a marker layer comprising an ultraviolet detectable material over the dielectric layer; patterning the marker layer and the dielectric layer thereby creating exposed portions of the dielectric layer; depositing a liner over the marker layer and the exposed portions of the dielectric layer; depositing a metal layer over the liner; and polishing the metal layer and liner and the marker layer. The method further comprises exposing the dielectric layer to an ultraviolet light; and detecting whether the liner and the marker layer are present over the dielectric layer, wherein detection of the ultraviolet detectable material by the ultraviolet light signals a presence of the liner and the marker layer over the dielectric layer. Moreover, the method further comprises configuring the marker layer as a separate layer from the dielectric layer. In the step of forming, the ultraviolet detectable material comprises fluorescent material or phosphorescent material. Additionally, the method further comprises re-polishing the liner and the marker layer upon detection of the ultraviolet detectable material by the ultraviolet light; and analyzing polishing slurry effluent generated from the polishing process for a presence/absence of the ultraviolet detectable material, wherein detection/non-detection of the ultraviolet detectable material in the polishing slurry effluent signals an endpoint for CMP processing during fabrication of the integrated circuit.
  • The advantages afforded by the embodiments of the invention include improved process yield, performance, and reliability. Moreover, the embodiments of the invention also provide a low-cost improvement, which may reduce overall processing time by limiting the number of rework or CMP “touch-up” steps. By monitoring the CMP slurry for lack of marker material after the marker material is first detected, overpolishing of the damascene lines (which would result in higher resistance wires) can also be reduced.
  • These and other aspects of the embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments of the invention and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit thereof, and the embodiments of the invention include all such modifications.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The embodiments of the invention will be better understood from the following detailed description with reference to the drawings, in which:
  • FIG. 1 is a schematic diagram of a partially completed integrated circuit according to an embodiment of the invention;
  • FIG. 2 is a schematic diagram of a partially completed integrated circuit following dual-damascene patterning according to an embodiment of the invention;
  • FIG. 3 is a schematic diagram of a partially completed integrated circuit following liner deposition according to an embodiment of the invention;
  • FIG. 4 is a schematic diagram of a partially completed integrated circuit following metallization deposition according to an embodiment of the invention;
  • FIG. 5 is a schematic diagram of a partially completed integrated circuit following polishing according to a first embodiment of the invention;
  • FIG. 6 is a schematic diagram of a partially completed integrated circuit being exposed to ultraviolet rays according to a first embodiment of the invention;
  • FIG. 7 is a flow diagram illustrating a preferred method according to a first embodiment of the invention;
  • FIG. 8 is a schematic diagram of a partially completed integrated circuit following polishing according to a second embodiment of the invention;
  • FIG. 9 is a schematic diagram of a partially completed integrated circuit being exposed to ultraviolet light according to a second embodiment of the invention; and
  • FIG. 10 is a flow diagram illustrating a preferred method according to a second embodiment of the invention.
    • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION
  • The embodiments of the invention and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments of the invention. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments of the invention may be practiced and to further enable those of skill in the art to practice the embodiments of the invention. Accordingly, the examples should not be construed as limiting the scope of the embodiments of the invention.
  • As mentioned, there remains a need for a novel technique that allows for easier and more precise inspections of damascene structures. The embodiments of the invention achieve this need by providing a layer of fluorescent or phosphorescent material into a damascene structure. The layer, which can easily be picked up under UV light and/or by slurry concentration analysis, allows for easy in situ detection of residual liner defects and/or CMP endpoint detection. Referring now to the drawings and more particularly to FIGS. 1 through 10 where similar reference characters denote corresponding features consistently throughout the figures, there are shown preferred embodiments of the invention.
  • FIG. 1 illustrates an integrated circuit 5 embodied as a damascene stack, which comprises a substrate 10, which may comprise a single-crystal silicon layer, or alternatively, the substrate 10 may comprise any appropriate semiconducting material, including, but not limited to silicon (Si), germanium (Ge), gallium phosphide (GaP), indium arsenide (InAs), indium phosphide (InP), silicon germanium (SiGe), gallium arsenide (GaAs), or other semiconductors. Next, an interlevel dielectric layer 20 is deposited over the substrate 10. The dielectric layer 20 may comprise silicon oxide, FTEOS (silicon oxide with fluorine impurities), Silk® (available from Dow Chemical Company, Midland, Mich., USA), SiCOH (carbon-doped oxide), and with or without a hardmask layer (not shown). Next, a marker layer 30 is deposited on top of dielectric layer 20. The marker layer 30 comprises a fluorescent or phosphorescent material, such as phosphor, which is detectable upon exposing the marker layer 30 to an ultraviolet light.
  • Next, as shown in FIG. 2, the damascene stack 5 is patterned using any typical lithography and etching techniques known in the art, thereby creating a void 35 in the damascene stack 5. Then, as illustrated in FIGS. 3 and 4, the damascene stack 5 undergoes a metallization process, which involves the deposition of a liner 40 over all exposed surfaces of the damascene stack 5 including the exposed surfaces in the void 35. The liner film 40 may comprise tungsten (W), titanium nitride (TiN) tantalum (Ta), and tantalum nitride (TaN). Thereafter, a plating metal 50, such as copper (Cu) is deposited over the liner 40 thereby filling the void 35.
  • The next step involves performing a CMP process on the metal layer 50 and liner film 40 as shown in FIG. 5. The CMP is endpointed by using the phosphor concentration in the slurry (not shown). After endpoint, an overpolishing process is performed. Alternatively, one may endpoint when the slurry is no longer fluorescing. The overpolishing process is designed to stop on the marker layer 30. At this point, the damascene stack 5 can be quickly examined with ultraviolet light (ray) to look for fluorescence or phosphorescence in the damascene stack 5 as indicated in FIG. 6. If there are areas with no fluorescence or phosphorescence, then this indicates that there is still residual metal 50 or liner 40 (i.e., incomplete CMP) over the marker layer 30. If there remains residual metal 50 or liner 40 over the marker layer 30, then the damascene structure 5 (i.e., wafer) should be reworked with a touch up CMP process and can be re-examined. This process can continue until no residual metal 50 or liner 40 remains over the marker layer 30.
  • FIG. 7 illustrates the process flow according to the first embodiment of the invention. FIG. 7 illustrates, with reference to FIGS. 1 through 6, a method of detecting whether post-CMP (chemical mechanical polishing) defects exist in an integrated circuit 5, wherein the method comprises depositing (101) a dielectric layer 20 over and adjacent to a substrate 10; forming (103) a marker layer 30 over and adjacent to the dielectric layer 20, wherein the marker layer 30 comprises an ultraviolet detectable material; patterning (105) the marker layer 30 and the dielectric layer 20 thereby creating exposed portions of the dielectric layer 20; depositing (107) a liner 40 over and adjacent to the marker layer 30 and the exposed portions of the dielectric layer 20; depositing (109) a metal layer 50 over and adjacent to the liner 40; polishing (111) the metal layer 50 and the liner 40; and exposing (113) the marker layer 30 to an ultraviolet ray, wherein detection of the ultraviolet detectable material by the ultraviolet ray signals an absence of the metal layer 50 and the liner 40 over the marker layer 30. Additionally, the method further comprises re-polishing (115) the liner 40 upon non-detection of the ultraviolet detectable material by the ultraviolet ray.
  • The method further comprises configuring the marker layer 30 as a separate layer from the dielectric layer 20. In the step of forming (103) the marker layer 30, the ultraviolet detectable material comprises fluorescent material or phosphorescent material. Furthermore, the marker layer 30 signals an endpoint for CMP processing during fabrication of the integrated circuit 5. The method further comprises analyzing polishing slurry effluent (not shown) generated from the polishing process (111) for a presence of the ultraviolet detectable material, wherein detection of the ultraviolet detectable material in the polishing slurry effluent signals an endpoint for CMP processing during fabrication of the integrated circuit 5. Alternatively, the method further comprises analyzing polishing slurry effluent (not shown) generated from the polishing process (111) for an absence of the ultraviolet detectable material, wherein non-detection of the ultraviolet detectable material in the polishing slurry effluent signals an endpoint for CMP processing during fabrication of the integrated circuit 5.
  • A second embodiment of the invention is illustrated in FIGS. 8 through 10. Generally, the first and second embodiments are similar up through FIG. 4, which is the end of the metallization process. According to the second embodiment, the marker layer 30 does not act as a polishing stop layer, but instead, is polished away completely as shown in FIG. 8. The sudden presence or, alternatively, absence of phosphor in the slurry can also be used as a reference point for endpointing the process. According to the second embodiment, ultraviolet light is used to check for the presence or absence of fluorescence or phosphorescence, as illustrated in FIG. 9. Accordingly, if some of the liner 40 and marker layer 30 residuals remain after the CMP process in the area above the dielectric layer 20, then there will be a thickness variation from the areas with exposed residuals to the areas with the exposed marker layer 30 to the areas with the exposed dielectric layer 20. In other words, if fluorescence or phosphorescence is seen above the dielectric layer 20, then it is indicative of there being metal 50 or liner 40 residuals, which necessitates an additional CMP process to remove the remaining residual materials.
  • FIG. 10 illustrates the process flow according to the second embodiment of the invention. FIG. 10 illustrates, with reference to FIGS. 1 through 4 and FIGS. 8 and 9, a method of detecting whether post-CMP (chemical mechanical polishing) defects exist in an integrated circuit 5, wherein the method comprises depositing (201) a dielectric layer 20 over and adjacent to a substrate 10; forming (203) a marker layer 30 comprising an ultraviolet detectable material over and adjacent to the dielectric layer 20; patterning (205) the marker layer 30 and the dielectric layer 20 thereby creating exposed portions of the dielectric layer 20; depositing (207) a liner 40 over the marker layer 30; depositing (209) a metal layer 50 over and adjacent to the liner 40; and polishing (211) the metal layer 50, the liner 40, and the marker layer 30. The method further comprises exposing (213) the dielectric layer 20 to an ultraviolet light, and detecting (215) whether the liner 40 and the marker layer 30 are present over the dielectric layer 20, wherein detection of the ultraviolet detectable material by the ultraviolet light signals a presence of the liner 40 and the marker layer 30 over the dielectric layer 20. Furthermore, the method comprises re-polishing (217) the liner 40 and the marker layer 30 upon detection of the ultraviolet detectable material by the ultraviolet light.
  • As with the first embodiment, the method according to the second embodiment further comprises configuring the marker layer 30 as a separate layer from the dielectric layer 20. In the step of forming (203) the marker layer 30, the ultraviolet detectable material comprises fluorescent material or phosphorescent material. Additionally, the method according to the second embodiment further comprises analyzing polishing slurry effluent (not shown) generated from the polishing process for a presence or, alternatively, an absence of the ultraviolet detectable material, wherein detection or, alternatively, non-detection of the ultraviolet detectable material in the polishing slurry effluent signals an endpoint for CMP processing during fabrication of the integrated circuit 5.
  • The detection method provided by the embodiments of the invention is intended to determine whether metal 50 or liner 40 materials remain only over the marker layer 30. As illustrated in FIGS. 1 through 6 and 8 through 9, the liner 40 will remain in the integrated circuit 5 in areas protected by the metal layer 50, which are generally referred to as the “damascene” regions of the integrated circuit 5. It is in the “non-damascene” regions where shorting can occur if liner 40 or metal 50 remains, as such, it is in the “non-damascene” regions where the ultraviolet detection occurs.
  • The advantages afforded by the embodiments of the invention include improved process yield, performance, and reliability. Moreover, the embodiments of the invention also provide a low-cost improvement, which may reduce overall processing time by limiting the number of rework or CMP “touch-up” steps. By monitoring the CMP slurry for lack of marker material after the marker material is first detected, overpolishing of the damascene lines (which would result in higher resistance wires) can also be reduced.
  • The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments of the invention can be practiced with modification within the spirit and scope of the appended claims.

Claims (11)

1. An integrated circuit comprising:
a substrate;
a dielectric layer over said substrate;
a marker layer over said dielectric layer;
a liner over said marker layer and said dielectric layer; and
a metal layer over said liner,
wherein said marker layer comprises an ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of said metal layer and said liner over said marker layer.
2. The integrated circuit of claim 1, wherein said marker layer comprises a separate layer from said dielectric layer.
3. The integrated circuit of claim 1, wherein said ultraviolet detectable material comprises fluorescent material.
4. The integrated circuit of claim 1, wherein said ultraviolet detectable material comprises phosphorescent material.
5. An integrated circuit comprising:
a substrate;
a dielectric layer adjacent to said substrate;
a marker layer adjacent to said dielectric layer, wherein said marker layer comprises a separate layer from said dielectric layer;
a liner adjacent to said marker layer and said dielectric layer; and
a metal layer adjacent to said liner,
wherein said marker layer comprises an ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of said metal layer and said liner over said marker layer.
6. The integrated circuit of claim 5, wherein said ultraviolet detectable material comprises fluorescent material.
7. The integrated circuit of claim 5, wherein said ultraviolet detectable material comprises phosphorescent material.
8. An integrated circuit comprising:
a substrate;
a dielectric layer over said substrate;
a marker layer over said dielectric layer;
a liner over said marker layer and said dielectric layer; and
a metal layer over said liner.
9. The integrated circuit of claim 8, wherein said marker layer comprises a separate layer from said dielectric layer.
10. The integrated circuit of claim 8, wherein said ultraviolet detectable material comprises fluorescent material.
11. The integrated circuit of claim 8, wherein said ultraviolet detectable material comprises phosphorescent material.
US11/669,180 2004-11-04 2007-01-31 Detection of residual liner materials after polishing in damascene process Abandoned US20070120259A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/669,180 US20070120259A1 (en) 2004-11-04 2007-01-31 Detection of residual liner materials after polishing in damascene process

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/904,329 US7361584B2 (en) 2004-11-04 2004-11-04 Detection of residual liner materials after polishing in damascene process
US11/669,180 US20070120259A1 (en) 2004-11-04 2007-01-31 Detection of residual liner materials after polishing in damascene process

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/904,329 Division US7361584B2 (en) 2004-11-04 2004-11-04 Detection of residual liner materials after polishing in damascene process

Publications (1)

Publication Number Publication Date
US20070120259A1 true US20070120259A1 (en) 2007-05-31

Family

ID=36315500

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/904,329 Expired - Fee Related US7361584B2 (en) 2004-11-04 2004-11-04 Detection of residual liner materials after polishing in damascene process
US11/669,180 Abandoned US20070120259A1 (en) 2004-11-04 2007-01-31 Detection of residual liner materials after polishing in damascene process

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/904,329 Expired - Fee Related US7361584B2 (en) 2004-11-04 2004-11-04 Detection of residual liner materials after polishing in damascene process

Country Status (2)

Country Link
US (2) US7361584B2 (en)
CN (1) CN100428469C (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8877083B2 (en) * 2012-11-16 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Surface treatment in the formation of interconnect structure
JP6691504B2 (en) * 2016-05-12 2020-04-28 信越化学工業株式会社 Wafer processed body, method for manufacturing the same, and method for confirming coatability of organic film on wafer
US11901304B2 (en) * 2021-05-18 2024-02-13 Globalfoundries U.S. Inc. Integrated circuit structure with fluorescent material, and related methods

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5667424A (en) * 1996-09-25 1997-09-16 Chartered Semiconductor Manufacturing Pte Ltd. New chemical mechanical planarization (CMP) end point detection apparatus
US5710069A (en) * 1996-08-26 1998-01-20 Motorola, Inc. Measuring slurry particle size during substrate polishing
US6110831A (en) * 1997-09-04 2000-08-29 Lucent Technologies Inc. Method of mechanical polishing
US6187417B1 (en) * 1998-02-18 2001-02-13 International Business Machines Corporation Substrate having high optical contrast and method of making same
US6307628B1 (en) * 2000-08-18 2001-10-23 Taiwan Semiconductor Manufacturing Company, Ltd Method and apparatus for CMP end point detection using confocal optics
US6329118B1 (en) * 1999-06-21 2001-12-11 Intel Corporation Method for patterning dual damascene interconnects using a sacrificial light absorbing material
US6361923B1 (en) * 1999-08-17 2002-03-26 International Business Machines Corporation Laser ablatable material and its use
US6723639B1 (en) * 2001-05-24 2004-04-20 Taiwan Semiconductor Manufacturing Company Prevention of post CMP defects in Cu/FSG process
US7052924B2 (en) * 2004-03-29 2006-05-30 Articulated Technologies, Llc Light active sheet and methods for making the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2665024B1 (en) 1990-07-20 1994-02-18 Jean Galvier METHOD FOR DETERMINING THE COMPLETE REMOVAL OF A THIN FILM FROM A NON-PLANAR SUBSTRATE.
US6974766B1 (en) * 1998-10-01 2005-12-13 Applied Materials, Inc. In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application
US6251781B1 (en) * 1999-08-16 2001-06-26 Chartered Semiconductor Manufacturing Ltd. Method to deposit a platinum seed layer for use in selective copper plating
US20040082169A1 (en) * 2002-10-29 2004-04-29 Chartered Semiconductor Manufacturing Ltd. Deposition of barrier metal in damascene interconnects using metal carbonyl
KR100641502B1 (en) * 2002-12-30 2006-10-31 동부일렉트로닉스 주식회사 Method for forming a contact using dual damascene process in semiconductor fabrication
JP4461215B2 (en) * 2003-09-08 2010-05-12 独立行政法人産業技術総合研究所 Low dielectric constant insulating material and semiconductor device using the same
US7088003B2 (en) * 2004-02-19 2006-08-08 International Business Machines Corporation Structures and methods for integration of ultralow-k dielectrics with improved reliability
JP2005244031A (en) * 2004-02-27 2005-09-08 Nec Electronics Corp Semiconductor device and its manufacturing method

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5710069A (en) * 1996-08-26 1998-01-20 Motorola, Inc. Measuring slurry particle size during substrate polishing
US5667424A (en) * 1996-09-25 1997-09-16 Chartered Semiconductor Manufacturing Pte Ltd. New chemical mechanical planarization (CMP) end point detection apparatus
US6110831A (en) * 1997-09-04 2000-08-29 Lucent Technologies Inc. Method of mechanical polishing
US6187417B1 (en) * 1998-02-18 2001-02-13 International Business Machines Corporation Substrate having high optical contrast and method of making same
US6190759B1 (en) * 1998-02-18 2001-02-20 International Business Machines Corporation High optical contrast resin composition and electronic package utilizing same
US6337375B1 (en) * 1998-02-18 2002-01-08 International Business Machines Corporation High optical contrast resin composition and electronic package utilizing same
US6329118B1 (en) * 1999-06-21 2001-12-11 Intel Corporation Method for patterning dual damascene interconnects using a sacrificial light absorbing material
US6361923B1 (en) * 1999-08-17 2002-03-26 International Business Machines Corporation Laser ablatable material and its use
US6307628B1 (en) * 2000-08-18 2001-10-23 Taiwan Semiconductor Manufacturing Company, Ltd Method and apparatus for CMP end point detection using confocal optics
US6723639B1 (en) * 2001-05-24 2004-04-20 Taiwan Semiconductor Manufacturing Company Prevention of post CMP defects in Cu/FSG process
US20060292860A1 (en) * 2001-05-24 2006-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. Prevention of post cmp defects in cu/fsg process
US7052924B2 (en) * 2004-03-29 2006-05-30 Articulated Technologies, Llc Light active sheet and methods for making the same

Also Published As

Publication number Publication date
US7361584B2 (en) 2008-04-22
US20060097394A1 (en) 2006-05-11
CN1808715A (en) 2006-07-26
CN100428469C (en) 2008-10-22

Similar Documents

Publication Publication Date Title
JP5067039B2 (en) Manufacturing method of semiconductor device
US7541276B2 (en) Methods for forming dual damascene wiring for semiconductor devices using protective via capping layer
US6350694B1 (en) Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials
US20040127016A1 (en) Dual cap layer in damascene interconnection processes
US6433436B1 (en) Dual-RIE structure for via/line interconnections
US6806193B2 (en) CMP in-situ conditioning with pad and retaining ring clean
US8143138B2 (en) Method for fabricating interconnect structures for semiconductor devices
US20070120259A1 (en) Detection of residual liner materials after polishing in damascene process
US7368397B2 (en) Method for monitoring edge bead removal process of copper metal interconnection
US7172962B2 (en) Method of manufacturing a semiconductor device
US20090170305A1 (en) Method for improving electromigration lifetime for cu interconnect systems
US6723626B2 (en) Method of manufacturing semiconductor device
TW201705221A (en) Using electroless deposition as a metrology tool to highlight contamination, residue, and incomplete via etch
US20070123034A1 (en) Method for removing a passivation layer prior to depositing a barrier layer in a copper metallization layer
US9941214B2 (en) Semiconductor devices, methods of manufacture thereof, and inter-metal dielectric (IMD) structures
US20150221547A1 (en) Hardmask faceting for enhancing metal fill in trenches
US7638424B2 (en) Technique for non-destructive metal delamination monitoring in semiconductor devices
US6541286B1 (en) Imaging of integrated circuit interconnects
US6800548B2 (en) Method to avoid via poisoning in dual damascene process
US9018097B2 (en) Semiconductor device processing with reduced wiring puddle formation
Tada et al. Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners
Khatkhatay et al. Impact of scribe line (kerf) defectivity on wafer yield
Khatkhatay et al. Scribe line defect-induced yield loss in FINFET technology
Pallinti et al. An overview of stress free polishing of Cu with ultra low-k (k< 2.0) films
Vilmay et al. Key Process steps for High Reliable SiOCH Low-k Dielectrics for the sub 45nm technology nodes

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION