CN106448742B - Semiconductor device, test device and test macro - Google Patents
Semiconductor device, test device and test macro Download PDFInfo
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- CN106448742B CN106448742B CN201510900736.9A CN201510900736A CN106448742B CN 106448742 B CN106448742 B CN 106448742B CN 201510900736 A CN201510900736 A CN 201510900736A CN 106448742 B CN106448742 B CN 106448742B
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Abstract
There is provided a kind of circuit compared with prior art constitute it is simple and can pinpoint accuracy observation builtin voltage waveform semiconductor device, the semiconductor device includes: the control circuit of test pattern, detect semiconductor device during set observation in builtin voltage when being acted and carry out waveform observation；And comparing unit, its during the observation in the builtin voltage is compared with set reference voltage and exports comparison result signal, so that the reference voltage is changed and is carried out the comparison, and the comparison result signal of the voltage waveform of the builtin voltage during the observation is output to test device.
Description
Technical field
The present invention is, for example, the semiconductor device of semiconductor storage etc., and is about one kind for carrying out waveform observation
Deng the semiconductor device of test, the test device for testing the semiconductor device and have the test device and institute
State the test macro of semiconductor device.
Background technique
In the non-volatile memory of flash memory etc., it has been produced as reading, be written and eliminating number in inside
According to multiple voltages, trimming circuit (trimming circuit) adjusts these voltages.These voltages other than its correctness,
The accuracy of its waveform is also extremely important.
Fig. 9 is to indicate the test macro comprising test device 101 and NAND type flash memory 102 related with conventional example
Configuration example block diagram (for example, referring to Figure 12 of patent document 1).
In Fig. 9, NAND type flash memory 102 related with conventional example has following and constitutes: having data register
The NAND type flash memory block (memory block) 10 of device 10R controls 102 entirety of NAND type flash memory
The movement controller 20 of movement, the reference voltage generator 30 for generating set reference voltage Vref30 boost supply voltage
For pump circuit (pump circuit) 31-1~pump circuit 31- of the given voltage of the set multiple of benchmark voltage Vref30
N, set builtin voltage is generated according to reference voltage Vref30 and from pump circuit 31-1~pump circuit 31-N voltage
V1~builtin voltage VN internal voltage generator 32-1~internal voltage generator 32-N and via multiple pin
(multi-pad) MP is connected to the in-building type of the test device 101 of the external device (ED) as the test for carrying out memory chip certainly
I tests (built-in self-test, BIST) circuit 3.Herein, BIST circuit 3 has following and constitutes: according to from micro-
Control the signal behavior reference voltage Vref30 and builtin voltage V1 of tune controller (trimming controller) 35~interior
One of portion voltage VN output carries out electricity for the multiplexer (multiplexer) 33 of builtin voltage Vin, by builtin voltage Vin
Resistance partial pressure and the voltage of the resistor voltage divider circuit 34 of voltage, self-resistance bleeder circuit in future 34 after output resistance partial pressure with via
The external reference voltages EVref for carrying out the contact b input of the switch SW of self-test device 101 is compared and exports comparison result
The comparator (Comparator) 36 and fine tuning controller 35 of signal, the fine tuning controller 35 is according to from action control
The control signal of device 20 is acted, the decision circuitry comprising judging the signal from comparator 36, generates control to multiplexer 33
Signal processed and voltage is carried out to reference voltage generator 30 and internal voltage generator 32-1~internal voltage generator 32-N
Control.
In addition, switching to the side contact a and via multiple pin MP self-resistance in future bleeder circuit 34 by by switch SW
Builtin voltage is input to test device 101, and can carry out waveform observation with test device 101.
[existing technical literature]
[patent document]
[patent document 1] Japanese Patent Laid-Open 2014-10877 bulletin
[patent document 2] Japanese Patent Laid-Open 2006-234616 bulletin
[patent document 3] Japanese Patent Laid-Open 2006-090727 bulletin
Summary of the invention
[problem to be solved by the invention]
However, the method for the conventional example of observation builtin voltage waveform, as following, especially with the driving of so-called voltage
The weak very big problem of power.
The builtin voltage of flash memory 102 is monitored via multiple pin MP by test device 101.However, in inside
In the case that voltage is connected to test device 101, high parasitic capacitance Cp is also deposited in addition to the parasitic capacitance inside test device 101
It is in the cable between flash memory 102 and test device 101.This parasitic capacitance especially to the rising of builtin voltage and
Fall time has an impact.
Figure 10 is builtin voltage waveform in the NAND type flash memory 102 for indicate Fig. 9 and observes in test device 101
The waveform diagram of the observation voltage waveform arrived.As Figure 10 significantly shown in, the builtin voltage waveform observed actually with anticipation
Builtin voltage waveform is compared, and is risen or fallen much relatively slow.Therefore, verify so whether observe waveform by external loading effect
The specification value (specification value) for reaching set is very difficult.
For example, patent document 2 in order to provide can state observation internal signal to approach actual waveform state, and
And the semiconductor device of the difference of the signal waveform quality as caused by experimental situation or the difference of experimental provision can be grasped, it is described
Semiconductor device is to have for internal signal to be exported the test circuit observed to the outside of semiconductor device as feature.
Test circuit has output switching circuit and memory circuit, and the output switching circuit can correspond to defeated via the 1st test
Enter the 1st control signal of pin (Input Pin) input and switch regular event mode and test action mode, is normally moving
Set value is exported when operation mode, and exports internal signal in test action mode, and the memory circuit is corresponding via the 2nd
2nd control signal of test input pin input and keep the output signal of output switching circuit and self-test output pin is defeated
Out.
In particular, in the test pattern of patent document 2, corresponding tripping voltage (trip voltage) high level or low
After 16 output signals of level are by control signal latch (latch), via monitoring pin output.If preparing multiple electricity
16 tripping voltages may be selected in road.In the case, there are the problem of so-called circuit composition becomes larger and complicates and tripping electricity
Pressure be according to circuit determine fixed value and do not changed after the completion of device freedom degree the problem of.
In addition, when patent document 3 uses logic analyzer (logic analyzer) outside connection, in order to solve to cause
Record the insufficient memory capacity when state value of the inside large scale integration (Large Scale Integration, LSI)
Deng, and the problem of the main reason for lead to misarrangement (debug) operation poor efficiency, and providing, there is the core of following composition to carry
(on-chip) logic analyzer.Herein, when the Wave data of monitoring signal exports different state values, by storage address
(memory address) incremental count (count up) and by this state value be written memory.Export continuous same state value
When, by this state value compression processing, and the count value weight for the data amount check for keeping count value, the value of same Data duplication number different
It folds to record.In addition, during generation in Wave data without triggering (trigger), it is repeatedly multiple in memory effective address
Memory write address, memory data.The counter of count signal generation circuit is reduced if generating triggering
(decrement), memory write activity just stops and notifies the state of end signal if counter clear.According to this state
The memory of information migration memory storage data reads (memory read).
Also that is, in patent document 3, proposing the logic analyzer being arranged in LSI chip.Herein, test data is stored up
There are static random access memory (Static Random Access Memories, SRAM), and by chip outside center
Processor (Central Processing Unit, CPU) is read.Whereby, the waveform of readable data, but having the waveform is 1
Or 0 logical waveform and can not with pinpoint accuracy carry out waveform observation the problem of.
Present invention aim to address above-mentioned problems, and provide a kind of circuit compared with prior art constitute it is simple and
Can be observed with pinpoint accuracy the semiconductor device of builtin voltage waveform, the test device for testing the semiconductor device and
The test macro for having the test device and the semiconductor device.
[means solved the problems, such as]
The semiconductor device of first aspect for the present invention is a kind of semiconductor of control circuit for having test pattern
Device, wherein the control circuit detection semiconductor device of the test pattern is middle during set observation to carry out set movement
When builtin voltage and carry out waveform observation, the semiconductor device is characterized in that: have comparing unit,
The comparing unit during the set observation in the builtin voltage and set reference voltage are carried out
Compare and export comparison result signal, and so that the reference voltage is changed and is carried out the comparison, and will be during the observation
The comparison result signal of the voltage waveform of builtin voltage is output to test device.
In the semiconductor device, it is characterised in that the control circuit directly exports the comparison result signal
To the test device.
In addition, in the semiconductor device, it is characterised in that have:
Sample circuit, by the comparison result signal with according to the internal clocking of the semiconductor device it is set when
Between interval be sampled and be converted into binaryzation data；And
The binaryzation data of the conversion are only temporarily stored set delay time and exported by output latch.
In turn, in the semiconductor device, it is characterised in that the control circuit is set according to the supplemental characteristic of input
It is fixed:
(A) temporal resolution of the time interval of the corresponding sample circuit；
(B) clock number of the binaryzation data number of the corresponding sampling for being temporarily stored in the output latch.
And then in the semiconductor device, it is characterised in that the control circuit be directed to the test device
Trigger signal it is synchronous and export the binaryzation data of above-mentioned conversion.
Herein, it is characterized in that the trigger signal is the status signal R/B of the semiconductor device.
And then in the semiconductor device, it is characterised in that the control circuit is according to from the test device
The data in the pause point of input start after temporarily ceasing the comparison of the comparing unit.
In addition, in the semiconductor device, it is characterised in that more standby:
Sample circuit, to the comparison result signal according to the set time of the internal clocking of the test device
Interval is sampled and is converted into binaryzation data；And
The binaryzation data of the conversion are only temporarily stored set delay time and exported by output latch.
Herein, be characterized in that the clock of the test device as reading enable signal/RE or output enable signal/OE and
It is input to the semiconductor device.
In the semiconductor device, which is characterized in that
The semiconductor device has multiple builtin voltages, and
The control circuit selects a builtin voltage from the multiple builtin voltage according to the selection instruction of input
And it is output to the comparing unit.
In addition, in the semiconductor device, it is characterised in that more for resistor voltage divider circuit, the electric resistance partial pressure electricity
Road is inserted between the circuit and the comparing unit for exporting the builtin voltage, by the builtin voltage with set intrinsic standoff ratio into
Row electric resistance partial pressure and export.
In turn, in the semiconductor device, it is characterised in that the comparing unit dual-purpose is to finely tune the internal electricity
The comparing unit of pressure.
And then in the semiconductor device, it is characterised in that the reference voltage is inputted from the test device
To the semiconductor device.
In addition, in the semiconductor device, it is characterised in that more standby to be produced under the control of the control circuit
The voltage generation circuit of the raw reference voltage.
In turn, in the semiconductor device, it is characterised in that the semiconductor device is deposited for non-volatility semiconductor
Storage device.
The test device of second aspect for the present invention is the test device for the semiconductor device, feature
It is:
Has a display unit, the display unit receives the comparison result signal of the output or binaryzation data and shows
Observation voltage waveform as builtin voltage.
In the test device, it is characterised in that the more standby data for storing the received comparison result signal or
The storage unit of binaryzation data.
The test macro of the third aspect of the present invention, it is characterised in that have the semiconductor device and the test
Device.
[The effect of invention]
Therefore, semiconductor device according to the present invention etc., circuit composition is simple compared with prior art and can be with height
Accuracy observes builtin voltage waveform.
Detailed description of the invention
Fig. 1 is the test system comprising test device 1 and NAND type flash memory 2 for indicating an implementation kenel of the invention
The block diagram of system.
Fig. 2 is the time diagram for indicating an example for the builtin voltage observation data observed with the test macro of Fig. 1.
Fig. 3 is the flow chart by mode test processes for indicating the test macro of Fig. 1.
Fig. 4 is the flow chart of the internal clocking synchronous mode test processes for the test macro for indicating Fig. 1.
Fig. 5 is the flow chart of the test clock synchronous mode test processes for the test macro for indicating Fig. 1.
Fig. 6 is the flow chart of the park mode test processes for the test macro for indicating Fig. 1.
Fig. 7 (a)~Fig. 7 (d) is the time diagram of each signal of the movement for the test macro for indicating Fig. 1.
Fig. 8 is the test macro comprising test device 1A and NAND type flash memory 2A for indicating variation of the invention
Configuration example block diagram.
Fig. 9 is the composition for indicating the test macro comprising test device 101 and NAND type flash memory 102 of conventional example
The block diagram of example.
Figure 10 is to indicate to be observed by the builtin voltage waveform and test device 101 of the NAND type flash memory 102 of Fig. 9
Observe the waveform diagram of voltage waveform.
Accompanying drawings symbol description
1,1A, 101: test device
2,2A, 102:NAND type flash memory
3: built-in self test circuit
5,5A: test mode circuit
10:NAND type flash memory block
10R: data register
11:NAND type flash memory array
12: page buffer
13:X decoder
14:Y decoder
20: movement controller
21: control signal logic circuit
22: input and output controller
22L: output latch
23: command register
24: address register
25: inputoutput data register
30: reference voltage generator
31-1~31-N: pump circuit
32-1~32-N: internal voltage generator
32: high voltage and medium voltage generation circuit
33: multiplexer
34: resistor voltage divider circuit
35: fine tuning controller
36: comparator
37: scratchpad register circuit
37S: sample circuit
38: test pattern logic circuit
39,46: voltage generation circuit
40: central processing unit
41: working storage
42: input unit
43: display unit
44: interface portion
45: hard disk drive
47: determination data memory
MP: multiple pin
P0~P13: user's pin
R1~R6: scratchpad register
201: trigger signal
202~205: step
SW: switch
Scomp: comparison result signal
TP: test pin
Vref30, Vref: reference voltage
Vin, V1~VN: builtin voltage
EVref: external reference voltages
A, b: contact
Cp: parasitic capacitance
IO [0]~IO [7]: inputoutput data
R/B ,/CE, CLE, ALE ,/WE ,/RE: enable signal
S1~S5, S5A, S5B, S6~S8, S11, S12, S12A, S13~S18: step
Specific embodiment
Hereinafter, illustrating implementation kenel of the invention in following referring to attached drawing.In attached drawing, same element is enclosed same
Symbol.
Fig. 1 is the test system comprising test device 1 and NAND type flash memory 2 for indicating an implementation kenel of the invention
The block diagram of the configuration example of system.In Fig. 1, NAND type flash memory 2 be semiconductor chip, especially it is characterized by: in addition to
User's pin (user pad) P0~user pin P13 is also equipped with the comparison reference voltage Vref that input carrys out self-test device 1
Test pin TP, and have for builtin voltage waveform observation test mode circuit 5.
In Fig. 1, test device 1 has following and constitutes: the central processing unit of the controller as control test processes
(CPU) 40 the work of the control flow of test processes and the dynamic random access memory (DRAM) of data, is executed as storage
The input unit 42 of keyboard, the mouse of memory (work memory) 41, input input instruction and input data etc., display waveform
The display unit 43 of the output data of observed result etc., connect with user's pin P0~user's pin P13 of flash memory 2 and into
Portion interface (interface) (portion I/F) 44 of the conversion of row input/output signal, storage are stored comprising temporary through/failure
(pass/fail) determination data of the voltage and current data of the measurement result of the dead-file (fail memory) of data
Memory 47 saves storage test program (test program) or observes hard disk drive (the Hard Disk of data
Drive, HDD) it 45 and generates the voltage of set comparison reference voltage (referring to the critical voltage for comparing) Vref and generates
Circuit 46.Herein, each circuit 41~47 is connected with CPU40.In test device 1, test processes of aftermentioned Fig. 3~Fig. 6 etc.
Program is stored into hard disk drive 45 in advance, is loaded into (load) when in use and arrives working storage 41.Test device 1 is by fast
Flash memory 2 executes the test processes of aftermentioned Fig. 3~Fig. 6, observes and is obtained in flash memory 2 in the form of two-value data
Builtin voltage (refer to high voltage and medium voltage generation circuit 32 from Fig. 1 high voltage and medium voltage etc. inside electricity
Pressure) voltage waveform (Fig. 2).Herein, the binaryzation data for observing Wave data are for example stored into determination data storage at the beginning
Device 47, and duplication is stored into hard disk drive 45 when being saved.
Flash memory 2 has following and constitutes: NAND quick-flash memory block 10, user's pin P0~user's pin
P13, test pin TP, movement controller 20, control signal logic circuit 21, input and output controller 22, command register
(command register) 23, address register 24, inputoutput data register 25, high voltage and medium voltage generate electricity
Road 32 and test mode circuit 5.Herein, NAND quick-flash memory block 10 has following and constitutes: NAND type flash
Device array 11, page buffer (page buffer) 12, X-decoder (decoder) 13 and Y-decoder 14.In addition, test
Mode circuit 5 has following and constitutes: having scratchpad register R1~scratchpad register circuit 37 of scratchpad register R6, conduct
Test pattern logic circuit 38, multiplexer 33, resistor voltage divider circuit 34 and the comparator 36 of the control circuit of test pattern.
In the test macro of this implementation form, user's pin P0~user's pin P13 is connected to the interface of test device 1
It portion 44 and is set for input and output signal below.
(1) the inputoutput data IO [0] of address, data or instruction of P0~P7:8 bit (bit) etc.~IO [7]；
(2) P8: indicate that chip is the status signal R/B of ready (ready, R) state or busy (busy ,/B) state；
(3) P9: in order to make chip enable the chip enable signal/CE of (enable) state；
(4) P10: enable signal CLE is latched in order to make instruction latch enabled instruction；
(5) P11: for the address latch enable signal ALE for keeping address latch enabled；
(6) P12: for write-in enable signal (write enable signal)/WE to chip write-in data；And
(7) P13: reading enable signal/RE in order to read data from chip.
Furthermore the "/" before signal name indicates low enable signal (low enable signal).
It controls signal logic circuit 21 and controls input according to from each control signal of user's pin P9~user's pin P13
The input and output movement of o controller 22 and memory write-in, elimination, verifying (verify) and the reading of movement controller 20
It acts out.Input and output controller 22 is according to the control signal from control signal logic circuit 21, via inputoutput data
The data inputted from user's pin P0~user's pin P7 are written to flash memory block 10 by register 25, and via defeated
Enter output data register 25 and the data from flash memory block 10 are output to user's pin P0~user's pin P7.Separately
Outside, input and output controller 22, will be from via address register 24 according to the control signal from control signal logic circuit 21
User's pin P0~user's pin P7 input address is output to flash memory block 10.In turn, input and output controller 22
It, will be from user's pin P0~user's pin via command register 23 according to the control signal from control signal logic circuit 21
The instruction of P7 input is output to movement controller 20.Test pattern logic circuit 38 is by the sampling in scratchpad register circuit 37
(sampling) circuit 37S, by the data of the comparison result signal Scomp exported from comparator 36 with set sampling rate
After (sampling rate) is sampled and is converted into binaryzation data, it is output to input and output controller 22, then, use is defeated
Latch 22L latch or is not latched and be output to test device 1 via user's pin P0 etc. out.Herein, sample circuit
37S is sampled under internal clocking (clock) synchronous mode by the clock determined according to the internal clocking of flash memory 2,
In addition, being sampled under test clock synchronous mode, such as according to enable signal/RE is read.
Movement controller 20 is believed according to the instruction from command register 23, the control from control signal logic circuit 21
Number and carry out the control signal of self-testing mode logic circuit 38, control flash memory block 10 and high voltage and medium voltage
The movement of generation circuit 32.High voltage and medium voltage generation circuit 32 generate necessary set in flash memory block 10
High voltage and medium voltage (collectively referred to as builtin voltage) and be output to flash memory block 10, and via in a test mode
The multiplexer 33 of the selection control of logic circuit 38 is output to resistor voltage divider circuit 34.
After scratchpad register circuit 37 temporarily stores the instruction from command register 23 or input and output controller 22,
It is output to test pattern logic circuit 38.In addition, scratchpad register circuit 37 temporarily stores the comparison knot from comparator 36
After the binaryzation data of fruit signal Scomp, test device 1 is output to via input and output controller 22.Herein, scratchpad register
Circuit 37 has register below.
(1) register R1: being that will select should to monitor the instruction of the multiplexer 33 of the builtin voltage of (monitor) temporarily
The register of storage.
(2) register R2: being the resistance that will select the intrinsic standoff ratio (for example, 1/2,1/4,1/8 etc.) of resistor voltage divider circuit 34
The register that the instruction of bleeder circuit 34 temporarily stores.
(3) register R3: being the binaryzation data for temporarily storing the comparison result signal Scomp from comparator 36
Register.
(4) register R4: being that will set internal clocking synchronous mode, test clock synchronous mode or park mode (break
) etc. mode the register that the instruction of test pattern (being described in detail later about each test pattern) temporarily stores.
(5) register R5: be temporarily storage time resolution ratio (time resolution) (for example, 10ns, 50ns,
100ns, 200ns, 300ns etc.) and output latch store clock number (be and output in input and output controller 22 latched
The corresponding clock number of latched bit number in device 22L, for example, 0 (passing through mode (Through mode)), 1,8,16,32 etc.)
Register.
(6) register R6: be will change builtin voltage, temporal resolution or output latch store clock number instruction it is temporary
When the register that stores.
The instruction of the multiplexer 33 for the builtin voltage that test pattern logic circuit 38 should be monitored according to the selection of register R1,
It indicates the builtin voltage that multiplexer 33 should select and controls switching.In addition, test pattern logic circuit 38 is according to register R2's
The instruction of resistor voltage divider circuit 34, sets the electric resistance partial pressure ratio that resistor voltage divider circuit 34 should be set and carries out setting control.Compare
Device 36 is by the builtin voltage exported from resistor voltage divider circuit 34 or from the voltage of builtin voltage electric resistance partial pressure, and via test pin
Reference voltage (critical voltage) Vref that TP is inputted from test device 1 is compared, and by the two-value of comparison result signal Scomp
Change data and is output to the register R3 in scratchpad register circuit 37.
Fig. 2 is the time diagram for indicating an example for the builtin voltage observation data observed with the test macro of Fig. 1.Test pattern
Logic circuit 38 selects the set builtin voltage in multiplexer 33, and the resistance being set in resistor voltage divider circuit 34 first
Partial pressure.Test device 1 sets the reference voltage Vr1 of first time, with set time interval (corresponding aftermentioned temporal resolution)
The builtin voltage of during set observation (t0~t24) is observed, and by the binaryzation number of comparison result signal Scomp at this time
Scratchpad register circuit 37 is arrived according to storage.It repeats following processing: reference voltage Vref being made sequentially only to be incremented by set be incremented by one side
Voltage (Vr2~Vr16), observes the builtin voltage of during the observation (t0~t24) on one side, and by comparison result at this time
The binaryzation data of signal Scomp are stored to scratchpad register circuit 37.Whereby, referred to as " Shi Mutu (shmoo can be obtained
Plot the binaryzation data of Fig. 2) ".Herein, the binaryzation data of comparison result signal Scomp can be transmitted by four modes
It shows to test device 1 and is output to display unit 43.
Herein, for example, the waveform of the high voltage of the 20V of observation memory write-in is set as, if the supply voltage of comparator 36
For 3.3V, then resistor voltage divider circuit 34 is set to 1/8, if assuming to use boost voltage 7V to supply voltage, by electric resistance partial pressure
Circuit 34 is set as 1/4.Also two comparators are ready for as the circuit for switching over selection.
Then, four test patterns of this implementation kenel are described in detail.
(1) pass through mode
Fig. 3 is the flow chart by mode test processes for indicating the test macro of Fig. 1.
Test device 1 is set as so-called waveform monitoring mode and is carried out through mode test processes.At this point, from than
Comparison result signal Scomp compared with device 36 is for example output to test dress as continuous signal via user's pin P0 (IO [0])
Set 1.Test device 1 reads comparison result signal Scomp in its period for reading circulation (read cycle) and obtains waveform and see
Measured data (Fig. 7 (b)).In this case, comparison result signal Scomp is not latched in register R3 by scratchpad register circuit 37,
But input and output controller 22 is carried out by and is transmitted to, and directly exported from user's pin P0.
In the step S1 of Fig. 3, the instruction input for the builtin voltage that should be monitored will be selected to scratchpad register R1, and in step
In rapid S2, the instruction input of the intrinsic standoff ratio of resistor voltage divider circuit 34 will be selected to scratchpad register R2.Then, it passes through in step s3
Apply initial stage reference voltage from test device 1 by test pin TP, input makes the action launching of memory chip in step s 4
Set observation during instruction, address, data.In turn, in step s 5 from scratchpad register R3 to be read by mode
Comparison result signal Scomp, and the instruction that input terminates the movement of memory chip in step s 6.Judge in the step s 7
Whether reference voltage reaches end voltage, and YES when terminates the test processes, on the other hand, toward before step 8 when NO
Into.In step s 8, after being incremented by reference voltage, step S4 is returned to, and repeat above-mentioned processing.
(2) internal clocking synchronous mode
Fig. 4 is the flow chart of the internal clocking synchronous mode test processes for the test macro for indicating Fig. 1.
In passing through mode, for comparing with for the voltage near reference voltage, it is possible to can become and come from comparator
36 comparison result signal Scomp frequently repeats the state of high level and low level switching, and above situation also has generation
A possibility that serious noise and it is more bad.Then, characterized by as follows: temporarily latching height by with the clock of chip interior
Level or low level and be sampled (digitlization (digitize)), and determine the cycling rate (frequency) of output, inhibit institute whereby
The noise stated.It is accompanied by this, additional following two parameter.
(1) parameter of temporal resolution: under 1 times, 2 times, 4 times, 8 times etc. of internal fundamental clock of setting, with described
After frequency is sampled by binaryzation data of the sample circuit 37S to the comparison result signal Scomp from comparator 36, by posting
Storage R3 and output latch 22L is latched and is output to test device 1.
(2) parameter (the corresponding sampled binaryzation number for being stored temporarily in output latch 22L of output latch 22L
According to several clock numbers): only latch it is N number of (output latch store clock number N=0 (passing through mode), 1,8,16 ...) from comparing
The binaryzation data of the comparison result signal Scomp of device 36 export if becoming N number of from such as user's pin P0.In order to survey
The 1 capture output data is set in trial assembly, and the status signal R/B as synchronization signal is made to trigger (toggle).It but, is not state
Signal R/B is also possible to such as user's pin P7 (IO [7]), but is intended to due to involving output latch store clock number
User's pin P0~P7 is used to export comparison result signal Scomp, therefore status signal R/B is suitble to the most.
If test device 1 detects rising of the status signal R/B from low level to high level, just by temporal resolution and
Waveform, which is read in, from such as user's pin P0 in the time that the parameter of output latch 22L determines observes data.For example, in sequencing
In the waveform monitoring of (data write-in) mode, if acting into sequencing, status signal R/B will become low level, and every
Status signal R/B is triggered to low level, high level, low level from high level in the fixed cycle of a internal clocking, therefore tests
Device 1 captures the waveform observation data using the status signal R/B as trigger signal.(Fig. 7 (c)) is if in the set time
Status signal R/B does not become low level from high level, then it represents that sequencing movement terminates.
In the step S1 of Fig. 4, the instruction input for the builtin voltage that should be monitored will be selected to scratchpad register R1, and in step
The instruction input of the intrinsic standoff ratio of resistor voltage divider circuit 34 will be selected to scratchpad register R2 in S2, and in step s 11 will setting
The instruction input of internal clocking synchronous mode is to scratchpad register R4.Then, in step s 12 by setting time resolution ratio and defeated
The instruction input of latch store clock number is to scratchpad register R5 out, in step s3 via test pin TP from test device
1 applies initial stage reference voltage.Then, during inputting the set observation of action launching for making memory chip in step s 4
Instruction, address, data supply synchronous state signal R/B triggering from output latch 22L in step S5A and read and compare
Consequential signal Scomp, the instruction that input terminates the movement of memory chip in step s 6.Then, judge in the step s 7
Whether reference voltage reaches end voltage, and YES when terminates the test processes, on the other hand, toward before step 8 when NO
Into.In step s 8, after being incremented by reference voltage, step S4 is returned to, and repeat above-mentioned processing.
The flow chart of Fig. 4 and the flow chart of Fig. 3 the difference is that: insertion internal clocking synchronous mode instruction input
With the setting (step S11, step S12) of described two parameters, in addition, the triggering of insert state signal R/B and captured and
With the readout process (step S5A) of test device 1.
(3) test clock synchronous mode
Fig. 5 is the flow chart of the test clock synchronous mode test processes for the test macro for indicating Fig. 1.
The movement of chip interior is progress synchronous with chip interior clock, but the comparison result signal from comparator 36
The digitlization (sampling) of Scomp is and comes from toward the input of output latch 22L, from the output for inputting user's pin P0 etc.
The clock input of test device 1 is synchronous and carries out.The clock of test device 1 is input to such as user's pin P13 and (reads enabled letter
Number/input terminal of RE), because reading rising of the enable signal/RE from low level to high level, and the comparison from comparator 36
Consequential signal Scomp is input to output latch 22L, and because reading enable signal/RE decline from high to low level,
And (Fig. 7 (d)) is exported from such as user's pin P0.
In test clock synchronous mode, enable signal/RE high level/low level circulation is read by suitably changing
(period) can change temporal resolution with time shaft, therefore can accomplish the part of rough (rough) simultaneously and observe in detail
Part.Furthermore status signal R/B can also be used without utilizing user's pin P0 in the output of waveform observation data.
The instruction input for the builtin voltage that should be monitored will be selected to scratchpad register R1 in the step S1 of Fig. 5, and in step
The instruction input of the intrinsic standoff ratio of resistor voltage divider circuit 34 will be selected to scratchpad register R2 in S2, and in step s 13 will setting
The instruction input of test clock synchronous mode is to scratchpad register R4.Then, in step s3 via test pin TP from test
Device 1 applies initial stage reference voltage, during inputting the set observation of action launching for making memory chip in step s 4
Instruction, address, data, and the comparison result in/RE clock synchronism detection mode is read from scratchpad register R3 in step S5B
Signal Scomp, and the instruction that input terminates the movement of memory chip in step s 6.Then, base is judged in the step s 7
Whether quasi- voltage reaches end voltage, and YES when terminates the test processes, on the other hand, toward before step 8 when NO
Into.In step s 8, after being incremented by reference voltage, step S4 is returned to, and repeat above-mentioned processing.
Compared with the flow chart of Fig. 3, the processing of the instruction input of additional test clock synchronous mode in the flow chart of Fig. 5
(step S13).In addition, in order to determine to be sampled (digitlization) to the comparison result signal Scomp from comparator 36 and defeated
Opportunity out carrys out input clock from test device 1 using enable signal/RE is read.Such as (the shape after the action launching of sequencing
State signal R/B becomes low level) make to read that enable signal/RE clock is synchronous, and read in/low level period the output of RE=
Data.
(4) park mode
Fig. 6 is the flow chart of the park mode test processes for the test macro for indicating Fig. 1.
Park mode is to be independent mode compared with 3 test patterns, but mainly in internal clock synchronization module
Middle use.The park mode is one of test pattern, and is stopped in the certain point of sequencing, elimination, reading acted on the way
The function that stop is made can act in this time point change or change operation condition.In the park mode of Fig. 6, when indicating internal
The processing example of park mode in clock synchronous mode.In the park mode, for example, can be altered to from rough temporal resolution
Detailed temporal resolution, or the change of voltage being observed.In addition, change chip operation condition and how waveform changes
Deng observation be also possible.
The instruction input for the builtin voltage that should be monitored will be selected to scratchpad register R1 in the step S1 of Fig. 6, and in step
The instruction input of the intrinsic standoff ratio of resistor voltage divider circuit 34 will be selected to scratchpad register R2 in S2, and will setting in step S12A
Temporal resolution and the instruction input of output latch store clock number will be set to scratchpad register R5, and in step S14
The instruction input of park mode is to scratchpad register R4.Then, apply just via test pin TP from test device 1 in step S3
Phase reference voltage.Then, in step s 4 input make memory chip action launching set observation during instruction,
Location, data, and the comparison result signal Scomp in status signal R/B triggering mode is read from register R3 in step S5A.
Then, the movement of memory chip is temporarily ceased in pause point in step S15, and will become in step s 16
The instruction input of more builtin voltage, temporal resolution or output latch store clock number is to scratchpad register R6, and in step
The movement of memory chip is again started up from pause point in S17.
In turn, the comparison result signal in status signal R/B triggering mode is read from scratchpad register R3 in step S18
Scomp, and the instruction that input terminates the movement of memory chip in step s 6.Then, benchmark electricity is judged in the step s 7
Whether pressure reaches end voltage, and YES when terminates the test processes, and on the other hand, NO when advances toward step 8.In
In step S8, after being incremented by reference voltage, step S4 is returned to, and repeat above-mentioned processing.
Fig. 7 (a)~Fig. 7 (d) is the time of each signal of the movement for the test macro for indicating the Fig. 1 as above constituted
Figure.Herein, Fig. 7 (a) is the waveform diagram for indicating the relationship of builtin voltage waveform and reference voltage during set observation.Again
Person, in Fig. 7 (a)~Fig. 7 (d), Stester indicates the binaryzation of the comparison result signal Scomp inputted by test device 1
Data (waveform observation data).In addition, herein, except mode, by the binaryzation data of comparison result signal Scomp
Be transmitted to the delay that output latch circuit 22L at least needs 1 clock part from scratchpad register R3, but this for easy understanding and
The relationship of waveform and omit.Moreover, the store clock number of output latch 22L is set as 1.
Fig. 7 (b) is the time diagram for indicating each signal of the movement by mode, without register R3 and output latch
The delay of 22L, therefore become IO [0]=Scomp, compared with being inputted with input trigger signal 201 synchronization of the data of test device 1
The data of consequential signal Scomp.
Fig. 7 (c) is the time diagram for indicating each signal of movement of internal clocking synchronous mode, via output latch 22L,
It exports from IO [0] by internal clocking (rising slave low level to high level of=status signal R/B) compared result signal
Scomp (Fig. 7 (a)) is sampled the waveform of (digitlization).1 detecting state signal R/B of test device slave low level to height
Trigger signal of the rising of level as the input of data.Test device 1 just inputs after seeing the signal intensity of status signal R/B
Data, therefore input and output controller 22 is slightly delayed output comparison result signal Scomp (step 202) from status signal R/B,
The trigger signal of test device 1 and the rising synchronous slave low level to high level of status signal R/B and input comparison result letter
Binaryzation data (the step 203) of number Scomp.
Herein, illustrate the case where output latch store clock number is set as 8.In the mode, when with inside
The comparison result signal Scomp that clock is synchronous and samples is the 8 bit parts for sequentially storing 8 sampling parts every time to output latch 22L
Latch and from input and output IO [0]~IO [7] output.1 detecting state signal R/B of test device and carry out 8 bit datas
Input.Also that is, status signal R/B and the frequency of data output become 1/8.The operating frequency of test device 1 than to be observed when
Between resolution ratio slow situation when be effective model.Furthermore the maximum value of output latch store clock number is substantially with described fast
The input and output IO number of flash memory 2 determines.
Fig. 7 (d) is the time diagram for indicating each signal of movement of test clock synchronous mode, by defeated from test device 1
Rising of the reading enable signal/RE slave low level to high level entered, input and output controller 22 latch comparison result signal
Scomp (step 204), by reading enable signal/RE decline from high to low level as inputoutput data IO
To carry out output comparison result signal Scomp (Fig. 7 (a)) (step 205).The input of test device 1 is by reading enable signal/RE
Decline from high to low level output comparison result signal Scomp binaryzation data.
If very quick with the sampling frequency of test device 1 according to the test macro of this implementation state as described above,
Due to using 1 reference voltage to be compared, the time of the builtin voltage waveform of comparator 36 risen or fallen is utilized
Hurriedly, it and can correctly capture very much.Since the comparator 36 in portion in the chip observes builtin voltage waveform, with test
The parasitic capacitance of cable between device 1 and flash memory 2 and input parasitic capacitance in test device 1 are unrelated, and existing
Technology is compared, can be with a simple configuration and with the builtin voltage of pinpoint accuracy measurement memory chip.
Variation
Fig. 8 is the survey comprising test device 1A and NAND type flash memory 2A indicated about variation of the invention
The block diagram of the configuration example of test system.The test macro of Fig. 8 and the test macro of Fig. 1 are compared and have following difference.
(1) has the test device 1A of no-voltage generation circuit 46 to replace test device 1.
(2) has the flash memory 2A with test mode circuit 5A to replace flash memory 2.Herein, mould is tested
Formula circuit 5A, which has, generates set comparison reference voltage Vref according to the control signal for carrying out self-testing mode logic circuit 38
Voltage generation circuit 39.Also that is, in variation, voltage generation circuit 39 is located inside semiconductor chip as special
Sign, due to using as DC voltage, can supply correct voltage by fine tuning (trimming), therefore Observable fills
Divide correct waveform.
In above implementation kenel, the comparator of the waveform observation by comparator 36 as builtin voltage, however this hair
It is bright to be not limited to this, can also dual-purpose be as Fig. 9 conventional example for finely tune adjust comparator.About multiplexer 33, resistance
Bleeder circuit 34 similarly can dual-purpose.
In above implementation kenel, illustrate about the test mode circuit 5 for NAND type flash memory, however this hair
It is bright to be not limited to this, be also applied for include or the semiconductor storage of non-(NOR) type flash memory, DRAM, SRAM etc. etc.
Semiconductor device.Furthermore it as the trigger signal for test device 1 in the case where NAND type flash memory 2, and uses
Enable signal/RE is read, however then replaces it using enable signal/OE is exported when the case where NOR type flash memory.
[industrial availability]
As detailed above, semiconductor device according to the present invention etc., circuit is constituted simple and can be with compared with prior art
Pinpoint accuracy observes builtin voltage waveform.
Claims (17)
1. a kind of semiconductor device, comprising:
The control circuit of test pattern, the test pattern control circuit detection semiconductor device during set observation in
Builtin voltage when carrying out set movement and carry out waveform observation；
Comparing unit, the comparing unit during the observation in the builtin voltage and set reference voltage are compared
Compared with and export comparison result signal, and change the reference voltage and carry out the comparison, and will be in during the observation
The comparison result signal of the voltage waveform of portion's voltage is output to test device；
Sample circuit, by the comparison result signal between the set time according to the internal clocking of the semiconductor device
Binaryzation data are converted into every being sampled；And
The binaryzation data converted only temporarily are stored set delay time and exported by output latch.
2. semiconductor device as described in claim 1, wherein the control circuit directly exports the comparison result signal
To the test device.
3. semiconductor device as described in claim 1, wherein the control circuit is set according to the supplemental characteristic of input:
(A) temporal resolution of the time interval of the corresponding sample circuit；And
(B) clock number of the corresponding binaryzation data number sampled for being temporarily stored in the output latch.
4. semiconductor device as described in claim 1, wherein the control circuit is believed with the triggering of the corresponding test device
It is number synchronous and export converted binaryzation data.
5. semiconductor device as claimed in claim 4, wherein the trigger signal is the status signal of the semiconductor device
(R/B)。
6. semiconductor device as described in claim 1, wherein the control circuit is temporary according to inputting from the test device
The data of rest point start after temporarily ceasing the comparison of the comparing unit.
7. semiconductor device as described in claim 1, in which:
The sample circuit is by the comparison result signal between the set time according to the internal clocking of the test device
Binaryzation data are converted into every being sampled；And
The binaryzation data converted only temporarily are stored set delay time and exported by the output latch.
8. semiconductor device as claimed in claim 7, wherein the clock of the test device is as reading enable signal (/RE)
Or it exports enable signal and is input to the semiconductor device.
9. semiconductor device as described in claim 1, wherein
The semiconductor device has multiple builtin voltages, and
The control circuit selects in the multiple builtin voltage builtin voltage and exports according to the selection instruction of input
To the comparing unit.
10. semiconductor device as described in claim 1, further includes:
Resistor voltage divider circuit, the resistor voltage divider circuit be inserted in the circuit for exporting the builtin voltage and the comparing unit it
Between, and by the builtin voltage with set intrinsic standoff ratio carries out electric resistance partial pressure and exports.
11. semiconductor device as described in claim 1, wherein the comparing unit dual-purpose is the ratio for finely tuning the builtin voltage
Compared with unit.
12. semiconductor device as described in claim 1, wherein the reference voltage is input to described half from the test device
Conductor device.
13. semiconductor device as described in claim 1, further includes: voltage generation circuit, in the control of the control circuit
The reference voltage is generated under system.
14. semiconductor device as described in claim 1, wherein the semiconductor device is non-volatility semiconductor storage dress
It sets.
15. a kind of test device, comprising: it is used for semiconductor device according to any one of claims 1 to 14, packet
It includes:
Display unit, the display unit receive exported comparison result signal or binaryzation data and are shown as builtin voltage
Observation voltage waveform.
16. test device as claimed in claim 15, further includes: storage unit, the received comparison result signal of storage institute
Data or binaryzation data.
17. a kind of test macro, comprising: semiconductor device according to any one of claims 1 to 14 and such as right
It is required that test device described in 15 or 16.
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| CN111025132B (en) * | 2018-10-09 | 2022-02-15 | 瑞昱半导体股份有限公司 | System chip, built-in self-test circuit and self-test method thereof |
| CN112462248A (en) * | 2021-01-06 | 2021-03-09 | 浙江杭可仪器有限公司 | Test signal output system and use method thereof |
| CN115047307B (en) * | 2022-08-17 | 2022-11-25 | 浙江杭可仪器有限公司 | Semiconductor device aging test box |
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| JPH0688858A (en) * | 1992-09-07 | 1994-03-29 | Advantest Corp | Ic testing device with waveform fetching function |
| JP2003114253A (en) * | 2001-10-03 | 2003-04-18 | Nec Corp | Waveform measuring semiconductor integrated circuit |
| TW201111807A (en) * | 2009-09-30 | 2011-04-01 | Mstar Semiconductor Inc | IO circuit calibration method and related apparatus |
| CN103675633A (en) * | 2012-09-11 | 2014-03-26 | 华邦电子股份有限公司 | Semiconductor device and detection method thereof |
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| JPH05303889A (en) * | 1992-04-22 | 1993-11-16 | Mitsubishi Electric Corp | Semiconductor device |
| KR100859832B1 (en) * | 2006-09-21 | 2008-09-23 | 주식회사 하이닉스반도체 | Inner voltage monitoring device in semiconductor memory device and method for monitoring the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0688858A (en) * | 1992-09-07 | 1994-03-29 | Advantest Corp | Ic testing device with waveform fetching function |
| JP2003114253A (en) * | 2001-10-03 | 2003-04-18 | Nec Corp | Waveform measuring semiconductor integrated circuit |
| TW201111807A (en) * | 2009-09-30 | 2011-04-01 | Mstar Semiconductor Inc | IO circuit calibration method and related apparatus |
| CN103675633A (en) * | 2012-09-11 | 2014-03-26 | 华邦电子股份有限公司 | Semiconductor device and detection method thereof |
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