JPH05303889A - Semiconductor device - Google Patents

Abstract

PURPOSE:To measure an internal voltage after enclosed by resin in a semiconductor device provided with an internal voltage generation circuit stepping down or boosting a power source and generating an internal source. CONSTITUTION:The internal voltage measuring circuit 10 of a differential amplifier type whose drive is controlled by a control circuit 2 is provided and the internal voltage generation circuit 1 is connected to one side transistor 13 being the differential input of the circuit and a test signal being a comparison signal is inputted to the other transistor 14 and the output of the internal voltage generation circuit 1 is detected by a voltmeter connected to an external terminal 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a structure capable of measuring a voltage generated inside the device after resin sealing.

[0002]

2. Description of the Related Art FIG. 5 is a circuit configuration diagram of a conventional semiconductor device. This figure shows a conceptual diagram of potential connection centering on an internal voltage generation circuit of a DRAM.
It is provided with a step-down circuit for generating a substrate bias potential VSS of a negative voltage (about -3V) on the chip based on a single 5V power supply voltage VCC. In the figure, reference numeral 50 denotes a substrate, on which an internal circuit 52 and a step-down circuit 51 are formed. The step-down circuit 51 steps down a power supply voltage Vcc of about 5V connected to the circuit to obtain a substrate of about -3V. The bias potential VSS is output and applied to the substrate 50. The internal circuit 52 is driven by the substrate bias potential VSS and the power source potential VCC.

The above-mentioned device is sealed and mounted with resin or the like after completion, but after the resin is sealed, the operating state of the step-down circuit 51 cannot be confirmed from the outside, so that the circuit design is not possible. It was not possible to determine whether or not the potential obtained during device simulation was actually output, and it was not possible to perform device analysis after it was commercialized.

[0004]

The conventional semiconductor device is constructed as described above, and there is a problem that the internal voltage generated from the power supply voltage cannot be measured inside the device after resin sealing. It was

The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor device capable of measuring an internal voltage generated inside the device after resin sealing.

[0006]

A semiconductor device according to the present invention comprises internal voltage output means for outputting the output of an internal voltage generating circuit to the outside of the device.

Further, the internal voltage output means comprises a connection circuit for connecting the output of the internal voltage generation circuit to an external terminal and a control circuit for controlling the connection operation of the connection circuit.

[0008]

In the present invention, since the internal voltage output means is provided, the output of the internal voltage generating circuit can be output to the outside of the device even after the circuit is sealed with resin or the like.

Further, since the internal voltage output means has a function of controlling the output when the output of the internal voltage generating circuit is output to the outside of the device, the output of the internal voltage generating circuit is output to the outside of the device only when necessary. You can take it out.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to FIG. In FIG. 1 (a), 10
Is a differential amplifier type internal voltage measuring circuit composed of P-channel MOS transistors 11, 12 and N-channel MOS transistors 13, 14, 15;
Is used as an input, and an internal voltage generating circuit 2 for stepping up or stepping down this voltage and outputting it as an internal voltage VSS is used to drive and control the internal voltage measuring circuit 10 according to a potential level input to a predetermined external terminal (not shown). Control circuits, 3 and 4
Is an external terminal of the chip.

Next, the operation will be described with reference to FIG. First, a voltmeter is connected to the terminal 4, and a test signal serving as a comparison voltage for measuring the internal voltage is applied to the terminal 3. Since the control circuit 2 outputs an L level signal during normal operation, the internal voltage measuring circuit 10 is not activated, the transistors 11 and 12 are in an ON state, and the transistor 14 has an L level signal. Is applied and turned off, the H level signal is output to the external terminal 4.

When a start signal indicating the start of the test is input to the external terminal connected to the control circuit 2, it is detected that the internal voltage measurement state has been entered, and the circuit 2 outputs an H level signal to the transistor 15. To do. As a result, the internal voltage measuring circuit 10 is activated. In this state, when the voltage of the test signal applied to the external terminal 3 is gradually changed from the L level to the H level, the transistor 14 is gradually turned on, When the potential of the test signal becomes the same level as the output VSS of the internal voltage generating circuit 1, the potential of the output terminal 4 is inverted from H level to L level, and the test signal applied to the external terminal 3 at this time is inverted. By reading the potential, the output potential of the internal voltage generating circuit 1 can be calculated.

When the test signal applied to the external terminal 3 gradually changes from the H level to the L level, the potential level of the test signal when the voltage of the external terminal 4 is inverted from the L level to the H level. Read the internal voltage generation circuit 1
Will be calculated.

As described above, according to this embodiment, the control circuit 2
A differential amplifier type internal voltage measuring circuit 10 driven and controlled by the
Is connected to an internal voltage generation circuit, and in the internal voltage measurement state, a test signal serving as a comparison voltage is input to the other transistor 14 via the external terminal 3, and a voltmeter is connected to the external terminal 4, Change the voltage of the external terminal 4
Since the output voltage of is found to change from the H level to the L level or from the L level to the H level, the internal voltage is calculated from the voltage value of the external terminal 3 at that time,
Even after the device is sealed with resin, the internal voltage generated by the internal voltage generating circuit 1 can be measured, and it can be easily confirmed whether or not the voltage at the time of device simulation is actually output. .. Further, since the control circuit 2 controls the operation of the internal voltage measuring circuit 10, an unnecessary signal is not output from the external terminal 4 during a normal operation other than the internal voltage measuring state, and therefore the consumption is reduced. There are no problems such as an increase in current and generation of noise.

Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. In this embodiment, the output of the internal voltage generating circuit 1 is directly taken out of the device and measured in the internal voltage measuring state. That is, in FIG. 2, reference numeral 20 denotes an internal voltage measuring circuit, and the internal voltage generating circuit 1 is connected to the external terminal 5 through a transition gate composed of an N-channel MOS transistor 21 and a P-channel MOS transistor 22. The operation of the channel MOS transistor 21 and the P-channel MOS transistor 22 is controlled by the control circuit 2.
It is controlled by. 23 is the above P
An inverter circuit 23 for supplying an inverted signal of the control circuit 2 to the channel MOS transistor 22.

Next, the operation will be described. A method of connecting a voltmeter to the external terminal 5 in the internal voltage measurement state,
There are two methods of inputting the test signal to the external terminal 5. First, in the former case, the H level signal is output from the control circuit 2 to take the internal voltage measurement state, and the transistor 2
The output gate of the internal voltage generation circuit 1 is measured by measuring the voltage output to the external terminal 5 by outputting the output of the internal voltage generation circuit 1 to the external gate 5 by opening the transmission gate 1 and 2. I can know.

On the other hand, in the latter case, the voltage of the test signal supplied to the external terminal 5 is changed, and when this voltage becomes equal to the output of the internal voltage generating circuit 1, the current value at the external terminal 5 becomes zero. It is possible to know the output voltage of the internal voltage generating circuit 1 by reading the voltage of the test signal at this time. By doing so, the internal voltage can be measured with a simple circuit configuration.

Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. As shown in FIG.
The internal voltage measuring circuit 30 connects the output of the internal signal generating circuit 1 to the source of the N-channel MOS transistor 31,
The gate and drain of the transistor 31 are connected to the external terminal 6
It is designed to be connected to.

Next, the operation will be described. In the internal voltage measurement state, for example, the transistor 31 is connected to the external terminal 6.
The test signal having a voltage higher than the threshold voltage value of is supplied, the voltage is gradually dropped, the point where the current value becomes zero is found, and the threshold voltage of the transistor 31 is determined from the voltage value of the test signal at that time. The output voltage of the internal voltage generation circuit 1 can be known by calculating the value obtained by subtracting the value.

By doing so, the drive control of the internal voltage measuring circuit 30 can be simultaneously performed by the test signal applied to the external terminal 6, and the internal voltage can be measured with a simpler circuit configuration.

Next, a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG. As shown in FIG.
The internal voltage measuring circuit 40 connects the output of the internal signal generating circuit 1 to the gate of the N-channel MOS transistor 41,
The power source Vcc is connected to the source of the transistor 41, and the external terminal 7 is connected to the drain.

Next, the operation will be described. In the internal voltage measuring state, a voltmeter is connected to the external terminal 7 to measure the output voltage. By calculating the value obtained by adding the threshold voltage value of the transistor 41 to this voltage value, the output voltage of the internal voltage generation circuit 1 can be known.

In this case, the output of the internal voltage generating circuit 1 must be above the threshold voltage value of the transistor 41 and located between the power supply voltage Vcc and 0V.

[0024]

As described above, according to the semiconductor device of the present invention, since the internal voltage measuring circuit is added and the output thereof is connected to the external terminal, the power supply is provided inside the device after the resin sealing. The internal voltage generated from the voltage can be measured, and a semiconductor device suitable for process analysis can be obtained.

Further, since the control circuit controls the operation of the internal voltage measuring circuit, an unnecessary signal is not output from the external terminal during the normal operation other than the measurement, and the noise and current consumption are reduced. There is an effect that it is possible to prevent the increase of.

[Brief description of drawings]

FIG. 1 is a diagram showing an internal voltage measuring circuit and an operation waveform of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an internal voltage measuring circuit of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a diagram showing an internal voltage measuring circuit of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a diagram showing an internal voltage measuring circuit of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a diagram for explaining potential connection centering on an internal voltage generation circuit of a conventional semiconductor device.

[Explanation of symbols]

 1 Internal Voltage Generation Circuit 2 Control Circuit for Internal Voltage Measurement Circuit 3 to 7 External Terminal 10 Internal Voltage Measurement Circuit 20 Internal Voltage Measurement Circuit 30 Internal Voltage Measurement Circuit 40 Internal Voltage Measurement Circuit 11 P-Channel MOS Transistor 12 P-Channel MOS Transistor 22 P Channel MOS transistor 13 N-channel MOS transistor 14 N-channel MOS transistor 15 N-channel MOS transistor 21 N-channel MOS transistor 31 N-channel MOS transistor 41 N-channel MOS transistor 23 Inverter circuit VCC Power supply potential VSS Internal potential

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[Procedure amendment]

[Submission date] October 22, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art FIG. 5 is a circuit configuration diagram of a conventional semiconductor device. This figure shows a conceptual diagram of potential connection centering on an internal voltage generation circuit of a DRAM.
Negative voltage of approx. 5V on the chip based on a single power supply voltage VCC
3V internal step-down power supply voltage INT. It is provided with a step-down circuit for generating VCC . In the figure, 50 is a substrate, is on the substrate internal circuit 52 and the step-down circuit 51 is formed, the step-down circuit 51 is the internal step-down of about 3V by lowering the power supply voltage VCC of about 5V connected to the circuit Power supply voltage INT. V
Outputs CC, that is configured to apply it to the internal circuit 52.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to FIG. In FIG. 1 (a), 10
Are connected to the P-channel MOS transistors 11 , 12 and 16 and the N-channel MOS transistors 13 , 14 and 15.
A differential amplifier type internal voltage measuring circuit composed of an inverter circuit 17 ; 1 is an internal voltage generating circuit which receives the power supply voltage Vcc as an input and which steps up or down to output it as an internal voltage V XX ; Control circuits 3 and 4 for driving and controlling the internal voltage measuring circuit 10 according to a potential level input to a predetermined external terminal are external terminals of the chip.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

Next, the operation will be described with reference to FIG. First, a voltmeter is connected to the terminal 4, and a test signal serving as a comparison voltage for measuring the internal voltage is applied to the terminal 3. Because during normal operation the control circuit 2 outputs the L level signal, the internal voltage measuring circuit 10 has not been activated, the outer <br/> unit terminal 4 not output signals.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

When a start signal indicating the start of the test is input to the external terminal connected to the control circuit 2, it is detected that the internal voltage measurement state has been entered, and the circuit 2 outputs an H level signal to the transistor 15. To do. As a result, the internal voltage measuring circuit 10 is activated. In this state, when the voltage of the test signal applied to the external terminal 3 is gradually changed from the L level to the H level, the transistor 14 is gradually turned on, When the potential of the test signal becomes the same level as the output V XX of the internal voltage generating circuit 1, the potential of the output terminal 4 is inverted from the H level to the L level, and the test signal applied to the external terminal 3 at this time. The output potential of the internal voltage generating circuit 1 can be calculated by reading the potential.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction content]

Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. In this embodiment, the output of the internal voltage generating circuit 1 is directly taken out of the device and measured in the internal voltage measuring state. That is, in FIG. 2, reference numeral 20 denotes an internal voltage measuring circuit, and the internal voltage generating circuit 1 is connected to the external terminal 5 via a transition gate composed of an N-channel MOS transistor 21 and a P-channel MOS transistor 22. The operation of the channel MOS transistor 21 and the P-channel MOS transistor 22 is controlled by the control circuit 2.
It is controlled by. 23 is the above P
An inverter circuitry for supplying an inverted signal of the control circuit 2 to the channel MOS transistor 22.

[Procedure Amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

Next, the operation will be described. A method of connecting a voltmeter to the external terminal 5 in the internal voltage measurement state,
There are two methods of inputting the test signal to the external terminal 5. First the former case, Ri Do internal voltage measurement state is output control circuit 2 from the H-level signal, the transistor 2
The output gate of the internal voltage generation circuit 1 is measured by measuring the voltage output to the external terminal 5 by outputting the output of the internal voltage generation circuit 1 to the external gate 5 by opening the transmission gate 1 and 2. I can know.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0023

[Correction method] Change

[Correction content]

[0023]

As described above, the semiconductor device according to the present invention is used.
According to U.S.A., an internal voltage measurement circuit is added and its output is
Since it is configured to be connected to the terminal,
Measuring the internal voltage generated from the power supply voltage inside the equipment
And obtain a semiconductor device suitable for process analysis.
There is an effect that can be done.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0024

[Correction method] Change

[Correction content]

Further , the internal voltage measurement time is controlled by the control circuit.
Since the operation of the road is controlled, it is normally used except when measuring.
Do not output unnecessary signals from external terminals during operation.
It is possible to prevent noise and increase in current consumption.
There is an effect.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] Explanation of code

[Correction method] Change

[Correction content]

[Explanation of symbols] 1 internal voltage generating circuit 2 control circuit for internal voltage measuring circuit 3 to 7 external terminal 10 internal voltage measuring circuit 20 internal voltage measuring circuit 30 internal voltage measuring circuit 40 internal voltage measuring circuit 11 P-channel MOS transistor 12 P Channel MOS transistor 22 P-channel MOS transistor 13 N-channel MOS transistor 14 N-channel MOS transistor 15 N-channel MOS transistor 21 N-channel MOS transistor 31 N-channel MOS transistor 41 N-channel MOS transistor 23 Inverter circuit VCC power supply potential INT. VCC Internal step-down power supply voltage 16 P-channel MOS transistor 17 Inverter circuit

[Procedure Amendment 10]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

[Procedure Amendment 11]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

Claims (2)

[Claims] 1. A semiconductor device comprising an internal voltage generating circuit for boosting or lowering a power supply voltage to a predetermined potential, which is resin-sealed after the circuit is formed, wherein an internal voltage for outputting the output of the internal voltage generating circuit to the outside of the device. A semiconductor device comprising output means. 2. The semiconductor device according to claim 1, wherein the internal voltage output means includes a connection circuit for connecting an output of the internal voltage generation circuit to an external terminal, and a control for controlling a connection operation of the connection circuit. A semiconductor device comprising a circuit.