JP4472999B2 - Semiconductor integrated circuit test equipment - Google Patents

Description

  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit (IC) test apparatus, and more particularly to an apparatus for performing a test of a semiconductor integrated circuit to be enlarged without using a high-performance tester body having a large capacity memory.

  A semiconductor test apparatus called a tester is generally used for testing a semiconductor integrated circuit. In the production process of the semiconductor integrated circuit, the test apparatus is used to determine whether the semiconductor integrated circuit is non-defective or defective. A scan test is generally known as one of the methods for performing the determination of a good product and a defective product with a high detection rate.

  Recent semiconductor integrated circuits are highly integrated, and the amount of test patterns required for scan tests is steadily increasing. Old semiconductor test apparatuses often do not have the necessary functions.

  Even with this function, the load time of the scan test pattern in the semiconductor test apparatus is long, and as a result, the test time tends to be long and the test cost tends to increase.

  In addition to the scan test, there is a function test pattern for a function test in the semiconductor integrated circuit test. By increasing the scan pattern, both the scan pattern and the function test pattern are loaded into one semiconductor test apparatus. This is made difficult by the limitation of the pattern memory of the semiconductor test equipment.

  Therefore, even with an inexpensive tester main unit with limited memory capacity, it is possible to perform a test with a long serial pattern represented by, for example, a scan method, and a test method that does not require an optional function dedicated to serial test has been proposed. (For example, refer to Patent Document 1).

In the test method described above, the test input signal of the device under test is stored in the first storage unit on the test board, and the device under test operates normally in response to the input signal in the second storage unit on the test board. An expected value signal to be output in the case where the test is performed, a test input signal is input from the first storage unit to the device under measurement, and the output signal output from the device under test is compared with the expected value signal of the second storage unit . With this configuration, a long pattern can be tested even if the tester body does not have a large-capacity pattern memory.
JP 2001-243087 A

  The device described in Patent Document 1 described above stores scan data in a non-volatile memory and performs a scan test. However, addressing for the non-volatile memory is not described in detail.

  It is an object of the present invention to apply a semiconductor integrated circuit test apparatus capable of performing a semiconductor test of a scan circuit with a very simple operation even when the semiconductor test apparatus does not have a necessary scan test circuit.

  The present invention solves such a problem. In a test of a semiconductor integrated circuit having a built-in scan circuit, even if the semiconductor test apparatus does not have the necessary scan test circuit, the necessary scan test circuit is replaced with a nonvolatile memory and a counter. By separately configuring the circuit and controlling it from a semiconductor test apparatus, the semiconductor test of the scan circuit can be performed with a very simple operation.

  That is, the present invention provides a first non-volatile memory that stores a test input signal of a semiconductor integrated circuit under test, and an expectation that is output when the semiconductor integrated circuit under test operates normally in response to the input signal. A second non-volatile memory in which a value signal is stored, a comparison unit for comparing an expected value signal from the second non-volatile memory and an actual output signal from the semiconductor integrated circuit under test; The data stored in the nonvolatile memory 2 is read out by monotonically increasing addressing using a counter circuit.

  By configuring as described above, it is only necessary to repeatedly generate a simple waveform signal from the semiconductor test apparatus, and this makes it possible to effectively use a semiconductor test apparatus that cannot be used for a scan test as it is. .

  In addition, a huge amount of scan patterns are stored in advance in a non-volatile memory that is different from the semiconductor test equipment, and it is not necessary to load scan patterns into the semiconductor test equipment. Coexistence with the function test pattern for the loaded function test becomes possible.

  As a result, the total amount of test patterns controlled by the semiconductor test apparatus is reduced, and the test time is shortened.

  The present invention is characterized in that a multi-bit nonvolatile memory data output is formed into one scan data by arbitrarily selecting a plurality of data outputs of the first nonvolatile memory by a selector circuit. .

  Further, the present invention is characterized in that scan mask data is stored in the second non-volatile memory, a timing correction circuit is provided, and a scan output comparison result signal can be forcibly masked.

  Further, according to the present invention, the second non-volatile memory has both scan expected value data and scan mask data, the expected value data required in the semiconductor test apparatus is fixed logic of 0 or 1, and the same expected value The scan output result is determined only by repeating the pattern.

According to the first aspect of the present invention, there is an effect that a test of a semiconductor integrated circuit having a built-in scan circuit is performed by a semiconductor test apparatus having no scan function. Furthermore, the test time of the semiconductor integrated circuit can be shortened by reducing the amount of the function test pattern loaded in the semiconductor test apparatus.
Further, in order to efficiently use the nonvolatile memory, it is a function of collecting a plurality of memory bits into one scan data, and the capacity of the nonvolatile memory to be used can be reduced.
Furthermore, forcibly mask (ignore the determination result) on the result (pass / fail) signal that compares the scan output output from the semiconductor integrated circuit under test with the expected scan value stored in the non-volatile memory. Can do.

According to the invention described in claim 2, by providing both the expected scan value data and the scan mask data in the non-volatile memory, it is possible to reduce the expected value pattern amount necessary for the semiconductor test apparatus for controlling the scan expected value data. It is possible to reduce the test control ease and test time.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a scan input signal circuit section in the test apparatus of the present invention, and FIG. 2 is a timing chart showing the operation of the circuit shown in FIG.

  A semiconductor test apparatus called a tester is generally used for testing a semiconductor integrated circuit. A semiconductor test apparatus 1 used in the present invention is a general tester. In this embodiment, a control clock signal and an output data selection signal are generated, and these signals are supplied to a scan input signal circuit unit 2. .

  The scan input signal circuit unit 2 includes an address generation counter circuit 21, a nonvolatile memory 22, a memory output data selection circuit 23, a memory output data shaping circuit 24, and a scan input signal input voltage level adjustment circuit 25.

  The nonvolatile memory 22 is composed of EPROM, EEPROM, flash memory, etc., and stores scan pattern input data. The nonvolatile memory 22 is accessed by monotonically increasing addressing provided from the address generation counter circuit 21, and predetermined scan data, in this embodiment, data from D0 to D4 is output.

  Since a large amount of scan pattern input data is written in the nonvolatile memory 22 in advance, the semiconductor test apparatus 1 generates a control clock signal and a control signal selected by output data, and generates an address generation counter circuit 21. To the memory output data selection circuit 23. For this reason, the semiconductor test apparatus 1 can control an enormous number of scan patterns covering several tens of megabytes (M) vectors with only a few patterns.

  Table 1 shows examples of control patterns.

  The semiconductor test apparatus 1 only needs to repeat the pattern in Table 1 above (patterns 2 to 5 are LOOP). For this reason, the address generation counter circuit 21 automatically continues incrementing the address of the nonvolatile memory 22. The reset signal is first executed only once in order to initialize the address generation counter circuit 21.

  Further, since the semiconductor memory is usually configured with a multi-bit memory output, when one memory output bit is applied to one scan input, the memory use efficiency is deteriorated. In order to solve this problem, in the present invention, a plurality of memory bits are selected by the memory output data selection circuit 23, and a waveform is generated by the memory output data shaping circuit 24 at the next stage, thereby enabling the nonvolatile memory 22 to be effective. It is used for. For example, in the case of an 8-bit 16M memory, there is only 2M per bit, but it is possible to index up to the maximum capacity of the memory by using multiple bits. Of course, it is possible to use only one bit.

  In this embodiment, a 4-bit memory output [D0] [D1] [D2] [D3] is used. For this purpose, [D0 selection signal], [D1 selection signal], [D2 selection signal], and [D3 selection signal] are generated as output data control signals from the semiconductor test apparatus 1 and supplied to the memory output data selection circuit 23. The memory output data selection circuit 23 sequentially selects [D0] [D1] [D2] [D3] for each clock based on the output data control signal. This signal is added by the memory output data shaping circuit 24 at the next stage to generate a signal waveform in which [D0] [D1] [D2] [D3] are synthesized (see FIG. 2).

  This signal is further supplied to the scan input signal input voltage level adjustment circuit 25 in the next stage. The scan input signal input voltage level adjusting circuit 25 forms a voltage level suitable for the scan input of the semiconductor integrated circuit 4 to be tested, and supplies the voltage to the semiconductor integrated circuit 4 to be tested.

  In the example shown in FIG. 2, one address of the nonvolatile memory 22 is incremented by 4 clocks of the control clock signal. This can be easily realized by removing the lower 2 bits of the address generation counter circuit 21 generated by the control clock signal and allocating the third bit to the least significant bit of the memory address.

  Next, FIG. 3 shows a configuration example of the pass / fail judgment circuit in the test apparatus of the present invention for comparing the scan-out signal output from the semiconductor integrated circuit 4 to be tested with the expected output value.

  The pass / fail judgment circuit 3 includes a non-volatile memory 31 that stores scan expected value data and scan mask data, a scan expected value data selection circuit 32, a scan mask data selection circuit 33, and a scan expected value data shaping circuit 34. A scan mask data shaping circuit 35, an expected scan value signal timing adjustment circuit 36, a scan mask signal timing adjustment circuit 37, a scan result determination circuit 38, and a pass / fail determination mask circuit 39.

  As shown in the example of expected value pattern in Table 2, the above-described nonvolatile memory 31 only needs to repeat a pattern. For this reason, the address generation counter circuit 21 automatically continues incrementing the address of the nonvolatile memory 31.

  The expected scan value data selection circuit 32 and the scan mask data selection circuit 33 in this embodiment have the same functions as the memory output data selection circuit 23 shown in FIG. That is, [D0 selection signal] or the like is generated as an output data control signal from the semiconductor test apparatus 1 and supplied to the data selection circuits 32 and 33. The output data selection circuit 32 sequentially selects [D0] [D1] [D2] [D3] for each clock based on the output data control signal. This signal is subjected to addition processing by the scan data expected value data generation circuit 34 in the next stage, thereby generating a signal waveform in which [D0] [D1] [D2] [D3] are synthesized. The output data selection circuit 33 sequentially selects [D4] [D5] [D6] [D7] for each clock based on the output data control signal. This signal is added by the scan mask data generation circuit 35 in the next stage, thereby generating a signal waveform in which [D4] [D5] [D6] [D7] are synthesized.

  Further, the expected scan value data molding circuit 36 and the scan mask data molding circuit 37 have the same functions as the memory output data molding circuit 24 shown in FIG.

  Since the scan output output from the semiconductor integrated circuit 4 and the scan expected value data generated from the nonvolatile memory 31 are not synchronized, the two logical signals cannot be compared as they are. In order to synchronize this signal, the scan expectation value signal timing adjustment circuit 36 synchronizes the timings of the two signals.

  The comparison result between the two signals can be arbitrarily forcedly masked by a scan mask signal. In order to synchronize the timing of this signal, a timing adjustment circuit 37 is also provided for the scan mask signal.

  With these circuit configurations, the scan test result of the semiconductor integrated circuit 4 to be tested always has a fixed logic (ex. Pass = 0, Fail = 1) regardless of the expected scan output value 0/1. As a result, the semiconductor test The expected value pattern prepared by the apparatus 1 can be implemented as a simple repeating pattern. In the example shown in Table 2, the expected value is always 0, and even with a scan expected value of several tens of M patterns, the test can be performed by simply repeating these four patterns with the loop (LOOP) instruction of the semiconductor test apparatus 1. As a result, the number of test patterns is reduced and control is facilitated.

It is a block diagram which shows the structure of the scan input signal circuit part in the test apparatus of this invention. 2 is a timing chart showing the operation of the circuit shown in FIG. It is a block diagram which shows the structure of the quality determination circuit in the testing apparatus of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor test apparatus 2 Scan input signal circuit part 3 Pass / fail judgment circuit 4 Semiconductor integrated circuit under test 21 Counter circuit for address generation 22 Non-volatile memory 23 Memory output data selection circuit 24 Memory output data shaping circuit 25 Scan input signal input voltage level adjustment Circuit 31 Non-volatile memory 32 Scan expected value data selection circuit 33 Scan mask data selection circuit 34 Scan expected value data shaping circuit 35 Scan mask data shaping circuit 36 Scan expected value signal timing adjustment circuit 37 Scan mask signal timing adjustment circuit 38 Scan result determination Circuit 38,
39 Pass / fail judgment mask circuit

Claims (2)

A first non-volatile memory storing a test input signal of the semiconductor integrated circuit under test and an expected value signal output when the semiconductor integrated circuit under normal operation corresponding to the input signal are stored a second non-volatile memory, and a comparator for comparing the actual output signal from the expected value signal and the tested semiconductor integrated circuit from the second non-volatile memory, said first and second non-volatile memory The data stored in is read by monotonically increasing addressing with a counter circuit, and a plurality of data outputs of the first non-volatile memory are arbitrarily selected with a selector circuit, so that a multi-bit non-volatile memory data output is scanned in one scan A test apparatus for a semiconductor integrated circuit for forming data, further comprising a timing correction circuit, wherein the second nonvolatile memory is formed. Lee in stores the scan mask data, test apparatus for a semiconductor integrated circuit, characterized in that the possible forced mask scan output comparison result signal. A first non-volatile memory storing a test input signal of the semiconductor integrated circuit under test and an expected value signal output when the semiconductor integrated circuit under normal operation corresponding to the input signal are stored A first non-volatile memory comprising: a second non-volatile memory; and a comparator for comparing an expected value signal from the second non-volatile memory with an actual output signal from the semiconductor integrated circuit under test. The data stored in is read by monotonically increasing addressing with a counter circuit, and a plurality of data outputs of the first non-volatile memory are arbitrarily selected with a selector circuit, so that a multi-bit non-volatile memory data output is scanned in one scan A semiconductor integrated circuit testing apparatus that forms data,
The second non-volatile memory has both scan expected value data and scan mask data, the expected value data necessary for the semiconductor test equipment is set to 0 or 1 fixed logic, and scan output is performed simply by repeating the same expected value pattern. A test apparatus for a semiconductor integrated circuit, characterized by determining a result .

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