CN106373931A - 一种高密度芯片重布线封装结构及其制作方法 - Google Patents

一种高密度芯片重布线封装结构及其制作方法 Download PDF

Info

Publication number
CN106373931A
CN106373931A CN201610886307.5A CN201610886307A CN106373931A CN 106373931 A CN106373931 A CN 106373931A CN 201610886307 A CN201610886307 A CN 201610886307A CN 106373931 A CN106373931 A CN 106373931A
Authority
CN
China
Prior art keywords
chip
layer
salient point
insulant
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610886307.5A
Other languages
English (en)
Other versions
CN106373931B (zh
Inventor
陈灵芝
张凯
郁科锋
邹建安
王新潮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangyin Xinzhilian Electronics Technology Co ltd
Original Assignee
Jiangyin Xinzhilian Electronics Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangyin Xinzhilian Electronics Technology Co ltd filed Critical Jiangyin Xinzhilian Electronics Technology Co ltd
Priority to CN201610886307.5A priority Critical patent/CN106373931B/zh
Publication of CN106373931A publication Critical patent/CN106373931A/zh
Application granted granted Critical
Publication of CN106373931B publication Critical patent/CN106373931B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/11001Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/11001Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/111Manufacture and pre-treatment of the bump connector preform
    • H01L2224/1111Shaping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本发明涉及一种高密度芯片重布线封装结构及其制作方法,所述结构包括金属线路层(4),所述金属线路层(4)正面设置有凸点(1),所述凸点(1)上贴装有芯片(2),所述芯片(2)的pad与凸点相连接,所述凸点(1)和芯片(2)外围填充有绝缘材料(3),所述金属线路层(4)背面设置有引脚线路层(5),所述金属线路层(4)和引脚线路层(5)外围填充有绝缘材料(3),所述引脚线路层(5)背面露出绝缘材料(3),所述引脚线路层(5)露出绝缘材料(3)的植球区域设置有金属球(6)。本发明一种高密度芯片重布线封装结构及其制作方法,它实现高性能的电性连接与良好的可靠性保证,形成高密度重布线封装工艺。

Description

一种高密度芯片重布线封装结构及其制作方法
技术领域
本发明涉及一种高密度芯片重布线封装结构及其制作方法,属于半导体封装技术领域。
背景技术
当前芯片尺寸封装(CSP)工艺主要有:
一、芯片先贴装在引线框架或者基板上后在芯片表面引线键合,或者芯片表面二次布线制作凸点后倒装在引线框架或者基板上再进行模塑包封及后工序;
二、芯片表面二次布线后在布线层Pad处制作焊球,再进行模塑包封(或裸芯片)及后工序。
当前芯片尺寸封装(CSP)工艺存在以下不足和缺陷:
1、随着封装产品小型化、超薄化、高密度的要求不断提高,对引线框架或者基板制作要求也小型化、超薄化、高密度,引线框架或基板制作过程易变形、翘曲,难度越大,进而导致封装工艺难度大,成本高;
2、采用引线键合工艺的产品,受焊线弧高和弧长的限制,产品的厚度和尺寸大小都不可能做到更小,同时引线键合无法做到超高密度,且打线效率低下;
3、采用倒装工艺或者圆片级封装的产品,芯片需要二次布线制作凸点,前期制造成本较高;
4、随着芯片引脚数的增多以及对芯片尺寸缩小要求的提高,芯片倒装时与基板的对位精度要求非常高;
5、绝大多数的倒装产品中都采用了底部填充剂,其作用是缓解芯片和基板之间由热膨胀系数(CTE)差所引起的剪切应力,但存在填充不满、空洞的问题;
6、芯片与基板FC焊接,存在多种材料,各材料之间的CTE不一,易造成封装过程中的翘曲问题。
发明内容
本发明所要解决的技术问题是针对上述现有技术提供一种高密度芯片重布线封装结构及其制作方法,它在金属载板表面先制作凸点,压绝缘材料后减薄,露出所需的凸点,再贴装芯片使其与凸点一端相连,对芯片压绝缘材料后去除载板,使凸点另一端露出后通过重布线工艺与外引脚相连,从而实现高性能的电性连接与良好的可靠性保证,形成高密度重布线封装工艺。
本发明解决上述问题所采用的技术方案为:一种高密度芯片重布线封装结构,它包括金属线路层,所述金属线路层正面设置有凸点,所述凸点上贴装有芯片,所述芯片的pad与凸点相连接,所述凸点和芯片外围填充有绝缘材料,所述金属线路层背面设置有引脚线路层,所述金属线路层和引脚线路层外围填充有绝缘材料,所述引脚线路层背面露出绝缘材料,所述引脚线路层露出绝缘材料的植球区域设置有金属球。
一种高密度芯片重布线封装结构的制作方法,所述方法包括如下步骤:
步骤一、取一金属载板;
步骤二、金属载板表面预镀铜材;
步骤三、形成凸点
在完成预镀铜材的金属载板表面形成所需的凸点;
步骤四、填充绝缘材料
在凸点外围填充绝缘材料,并通过减薄工艺使凸点露出绝缘材料;
步骤五、贴装芯片
通过倒装使芯片贴装于露出的凸点上,并使芯片pad与凸点相连接;
步骤六、填充绝缘材料
在芯片外围填充绝缘材料,对芯片形成保护;
步骤七、去除金属载板
步骤八、形成金属导电层
在去除金属载板的绝缘材料表面形成一层金属导电层;
步骤九、电镀金属线路层
在金属导电层表面通过电镀形成金属线路层;
步骤十、电镀引脚线路层
在金属线路层表面通过电镀形成引脚线路层;
步骤十一、快速蚀刻
将金属线路层和引脚线路层外的金属导电层去除;
步骤十二、填充绝缘材料
在金属线路层与引脚线路层外围填充绝缘材料,并通过减薄工艺使引脚线路层露出绝缘材料;
步骤十三、植球
在引脚线路层露出的植球区域植入金属球;
步骤十四、切割
将植好金属球的半成品品切割成单颗产品。
所述步骤八到步骤十二可以在步骤七到步骤十三之间重复多次。
与现有技术相比,本发明的优点在于:
1、本发明采用在普通的载板上电镀凸点后再直接贴装芯片,不需要定制引线框架或者基板,且可以根据需要进行多芯片的混装,降低了制造成本;
2、本发明采用载板电镀凸点的方式直接使芯片PAD与重布线线路相连,实现了芯片上二次布线制作凸点的过程,大大降低了前期芯片上制作凸点成本,提高了生产效率;
3、本发明的组装方式不需要芯片的倒装和倒装以后的底填工序,避免了因此产生的倒装对位和底填空洞的风险性;
4、本发明使用的绝缘材料单一,材料之间的CTE差异小,翘曲小,封装可靠性等级高。
附图说明
图1~图14为本发明一种高密度芯片重布线封装结构的制作方法的各工序流程图。
图15为本发明一种高密度芯片重布线封装结构的示意图。
其中:
凸点1
芯片2
绝缘材料3
金属线路层4
引脚线路层5
金属球6。
具体实施方式
以下结合附图实施例对本发明作进一步详细描述。
如图15所示,本实施例中的一种高密度芯片重布线封装结构,它包括金属线路层4,所述金属线路层4正面设置有凸点1,所述凸点1上贴装有芯片2,所述芯片2的pad与凸点相连接,所述凸点1和芯片2外围填充有绝缘材料3,所述金属线路层4背面设置有引脚线路层5,所述金属线路层4和引脚线路层5外围填充有绝缘材料3,所述引脚线路层5背面露出绝缘材料3,所述引脚线路层5露出绝缘材料3的植球区域设置有金属球6。
其制作方法如下:
步骤一、取一金属载板;
参见图1,取一片厚度合适的金属载板,金属载板的材质可以依据芯片的功能与特性进行变换,例如:铜材、铁材、镍铁材或锌铁材等;
步骤二、金属载板表面预镀铜材;
参见图2,在金属载板表面电镀一层铜材,目的是为后续电镀作基础,所述电镀的方式可以采用化学镀或是电解电镀;
步骤三、形成凸点
参见图3,在完成预镀铜材的金属载板表面通过电镀或蚀刻等方法形成所需的凸点;
步骤四、凸点外围填充绝缘材料
参见图4,利用压膜、包封、印刷等工艺在凸点外围填充绝缘材料,通过减薄等工艺使凸点露出绝缘材料;
步骤五、贴装芯片
参见图5,通过倒装使芯片贴装于露出的凸点上,并使芯片pad与凸点相连接;
步骤六、芯片外围填充绝缘材料
参见图6,利用压膜、包封、印刷等工艺在芯片之间填充绝缘材料,对芯片形成保护;
步骤七、去除金属载板
参见图7,通过蚀刻、peeling等方式去除金属载板;
步骤八、形成金属导电层
参见图8,在去除金属载板的绝缘材料表面通过化学沉铜的形成一层薄的金属导电层;
步骤九、电镀金属线路层
参见图9,在金属导电层表面通过电镀形成金属线路层;
步骤十、电镀引脚线路层
参见图10,在金属线路层表面通过电镀形成引脚线路层;
步骤十一、快速蚀刻
参见图11,将金属线路层和引脚线路层外的金属导电层去除;
步骤十二、金属线路层和引脚线路层外围填充绝缘材料
参见图12,利用压膜、包封、印刷等工艺在金属线路层与引脚线路层外围填充绝缘材料,通过减薄等工艺使引脚线路层露出绝缘材料;
步骤十三、植球
参见图13,在引脚线路层露出的植球区域植入金属球;
步骤十四、切割
参见图14,将植好金属球的半成品切割成单颗产品;
所述步骤八到步骤十二可以在步骤七到步骤十三之间重复多次,以形成多层金属线路层。
所述步骤十三的植球可以采用其他表面处理方式(如NiAu,PPF,OSP)替代。
除上述实施例外,本发明还包括有其他实施方式,凡采用等同变换或者等效替换方式形成的技术方案,均应落入本发明权利要求的保护范围之内。

Claims (3)

1.一种高密度芯片重布线封装结构,其特征在于:它包括金属线路层(4),所述金属线路层(4)正面设置有凸点(1),所述凸点(1)上贴装有芯片(2),所述芯片(2)的pad与凸点相连接,所述凸点(1)和芯片(2)外围填充有绝缘材料(3),所述金属线路层(4)背面设置有引脚线路层(5),所述金属线路层(4)和引脚线路层(5)外围填充有绝缘材料(3),所述引脚线路层(5)背面露出绝缘材料(3),所述引脚线路层(5)露出绝缘材料(3)的植球区域设置有金属球(6)。
2.一种高密度芯片重布线封装结构的制作方法,其特征在于所述方法包括如下步骤:
步骤一、取一金属载板;
步骤二、金属载板表面预镀铜材;
步骤三、形成凸点
在完成预镀铜材的金属载板表面形成所需的凸点;
步骤四、填充绝缘材料
在凸点外围填充绝缘材料,并通过减薄工艺使凸点露出绝缘材料;
步骤五、贴装芯片
通过倒装使芯片贴装于露出的凸点上,并使芯片pad与凸点相连接;
步骤六、填充绝缘材料
在芯片外围填充绝缘材料,对芯片形成保护;
步骤七、去除金属载板
步骤八、形成金属导电层
在去除金属载板的绝缘材料表面形成一层金属导电层;
步骤九、电镀金属线路层
在金属导电层表面通过电镀形成金属线路层;
步骤十、电镀引脚线路层
在金属线路层表面通过电镀形成引脚线路层;
步骤十一、快速蚀刻
将金属线路层和引脚线路层外的金属导电层去除;
步骤十二、填充绝缘材料
在金属线路层与引脚线路层外围填充绝缘材料,并通过减薄工艺使引脚线路层露出绝缘材料;
步骤十三、植球
在引脚线路层露出的植球区域植入金属球;
步骤十四、切割
将植好金属球的半成品品切割成单颗产品。
3.根据权利要求1所述的一种高密度芯片重布线封装结构的制作方法,其特征在于:所述步骤八到步骤十二可以在步骤七到步骤十三之间重复多次。
CN201610886307.5A 2016-10-11 2016-10-11 一种高密度芯片重布线封装结构及其制作方法 Active CN106373931B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610886307.5A CN106373931B (zh) 2016-10-11 2016-10-11 一种高密度芯片重布线封装结构及其制作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610886307.5A CN106373931B (zh) 2016-10-11 2016-10-11 一种高密度芯片重布线封装结构及其制作方法

Publications (2)

Publication Number Publication Date
CN106373931A true CN106373931A (zh) 2017-02-01
CN106373931B CN106373931B (zh) 2019-05-17

Family

ID=57896186

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610886307.5A Active CN106373931B (zh) 2016-10-11 2016-10-11 一种高密度芯片重布线封装结构及其制作方法

Country Status (1)

Country Link
CN (1) CN106373931B (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110175213A1 (en) * 2008-10-10 2011-07-21 Kentaro Mori Semiconductor device and manufacturing method thereof
CN102820276A (zh) * 2011-06-10 2012-12-12 南茂科技股份有限公司 四方扁平无接脚封装及其制造方法
CN103367180A (zh) * 2012-03-27 2013-10-23 南茂科技股份有限公司 半导体封装结构及其制作方法
CN105810659A (zh) * 2014-12-30 2016-07-27 恒劲科技股份有限公司 封装装置及其制作方法
CN206179856U (zh) * 2016-10-11 2017-05-17 江阴芯智联电子科技有限公司 一种高密度芯片重布线封装结构

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110175213A1 (en) * 2008-10-10 2011-07-21 Kentaro Mori Semiconductor device and manufacturing method thereof
CN102820276A (zh) * 2011-06-10 2012-12-12 南茂科技股份有限公司 四方扁平无接脚封装及其制造方法
CN103367180A (zh) * 2012-03-27 2013-10-23 南茂科技股份有限公司 半导体封装结构及其制作方法
CN105810659A (zh) * 2014-12-30 2016-07-27 恒劲科技股份有限公司 封装装置及其制作方法
CN206179856U (zh) * 2016-10-11 2017-05-17 江阴芯智联电子科技有限公司 一种高密度芯片重布线封装结构

Also Published As

Publication number Publication date
CN106373931B (zh) 2019-05-17

Similar Documents

Publication Publication Date Title
CN101335262B (zh) 叠层封装及其制造方法
CN102456677B (zh) 球栅阵列封装结构及其制造方法
CN103794587B (zh) 一种高散热芯片嵌入式重布线封装结构及其制作方法
TW201104797A (en) Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
CN104538318B (zh) 一种扇出型圆片级芯片封装方法
CN104505382A (zh) 一种圆片级扇出PoP封装结构及其制造方法
CN113257778B (zh) 一种3d堆叠且背部导出的扇出型封装结构及其制造方法
CN102263070A (zh) 一种基于基板封装的wlcsp封装件
CN102263078A (zh) 一种wlcsp封装件
CN103887256B (zh) 一种高散热芯片嵌入式电磁屏蔽封装结构及其制作方法
US10229891B2 (en) Chip embedding package with solderable electric contact
CN106531642A (zh) 一种芯片封装结构及其制备方法
CN106783796B (zh) 一种芯片封装结构及其制备方法
CN105845585A (zh) 一种芯片封装方法及芯片封装结构
CN102842558A (zh) 一种基于锡膏层的wlcsp多芯片堆叠式封装件及其封装方法
KR100843705B1 (ko) 금속 범프를 갖는 반도체 칩 패키지 및 그 제조방법
CN206179856U (zh) 一种高密度芯片重布线封装结构
CN102842560A (zh) 一种wlcsp多芯片堆叠式封装件及其封装方法
CN216413054U (zh) 一种多芯片晶圆级扇出封装结构
CN106373931B (zh) 一种高密度芯片重布线封装结构及其制作方法
CN103824820B (zh) 引线框区域阵列封装技术
CN203787410U (zh) 一种高散热芯片嵌入式电磁屏蔽封装结构
CN102842551A (zh) 一种基于基板、锡膏层的wlcsp多芯片堆叠式封装件及其封装方法
CN204375727U (zh) 一种高散热芯片嵌入式重布线封装结构
CN104659021A (zh) 一种三维圆片级扇出PoP封装结构及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant