CN106328776B - A kind of preparation method of vertical structure purple LED chip - Google Patents

A kind of preparation method of vertical structure purple LED chip Download PDF

Info

Publication number
CN106328776B
CN106328776B CN201610796255.2A CN201610796255A CN106328776B CN 106328776 B CN106328776 B CN 106328776B CN 201610796255 A CN201610796255 A CN 201610796255A CN 106328776 B CN106328776 B CN 106328776B
Authority
CN
China
Prior art keywords
gan
layer
substrate
thickness
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610796255.2A
Other languages
Chinese (zh)
Other versions
CN106328776A (en
Inventor
田伟
刘波波
田进
赵俊
李谊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Middle Northwest Co Ltd Of Study On Engineering Design Institute
Original Assignee
Middle Northwest Co Ltd Of Study On Engineering Design Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Middle Northwest Co Ltd Of Study On Engineering Design Institute filed Critical Middle Northwest Co Ltd Of Study On Engineering Design Institute
Priority to CN201610796255.2A priority Critical patent/CN106328776B/en
Publication of CN106328776A publication Critical patent/CN106328776A/en
Application granted granted Critical
Publication of CN106328776B publication Critical patent/CN106328776B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/641—Heat extraction or cooling elements characterized by the materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

The invention discloses a kind of preparation method of vertical structure purple LED chip using the substrate with low temperature u-GaN repair layer and substrate as growth basis, then, other each layer extensions is successively grown on the smooth surface u-GaN, purple LED epitaxial wafer is prepared；Vertical structure LED finally is made in purple LED epitaxial wafer, it mainly includes the following links: depositing to form reflecting mirror on LED epitaxial wafer surface, and produce metal electrode figure, metal electrode patterned surface is bonded on metallic substrates using high-temperature metal bonding technology, and utilizes laser lift-off technique peeling liner bottom；Another pole metal electrode figure is produced on the surface u-GaN.Vertical structure LED single chip power prepared by the present invention is larger, reduces series-parallel LED quantity, may be implemented to meet user demand with single-chip, while simplifying driving circuit design, greatly improves the reliability and service life of LED product.

Description

A kind of preparation method of vertical structure purple LED chip
[technical field]
The invention belongs to technical field of semiconductors, and in particular to a kind of preparation method of vertical structure purple LED chip.
[background technique]
The application of semiconductor lighting is significantly accelerated in recent years, and effect has obtained market approval, but it is entirely being illuminated The permeability in market is still lower.Domestic LED illumination application market not yet becomes the leading force of industry development.Semiconductor lighting The initial stage that application market, especially function lighting market are in development, future space are huge.
Traditional formal dress structure LED chip, p-type GaN doping difficulty cause hole lowly and are not easy long thickness And electric current is caused to be not easy to spread, it currently generallys use and is reached in the method that the surface p-type GaN prepares super thin metal film or ito thin film It obtains to electric current and uniformly spreads.But metal film electrode layer will absorb part light and reduce light extraction efficiency, if anti-mistake is thinned in thickness To limit current-diffusion layer again and realizes uniform reliable current spread on p-type GaN layer surface.Although ITO light transmittance is up to 90%, but conductivity, not as good as metal, the diffusion effect of electric current is also limited.And the electrode and lead of this structure accomplish light out Face, when work, can block some light.Therefore, this p-type contact structures constrain the operating current size of LED chip.It is another The PN junction heat of aspect, this structure is exported by Sapphire Substrate, very low in view of sapphire thermal coefficient, to large-sized Thermally conductive pathways are longer for power cake core, and the thermal resistance of this LED chip is larger, and operating current is also restrained.
Core technology of the vertical structure high-power chip technology as front end, it is domestic basic also in industrialization initial stage Still belong to blank.It is more than tens billion of market scales that domestic only semiconductor lighting, which had had every year, over the past two years, with product skill The maturation of art and market, market scale from now on will also continue to increase, therefore the Project Product market development prospect is extremely wide, Commercial value is huge.
[summary of the invention]
In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is that.
The invention adopts the following technical scheme:
A kind of preparation method of vertical structure purple LED chip is made with the substrate with low temperature u-GaN repair layer and substrate Then layer surface is repaired in smooth u-GaN and successively grows other each layer extensions, is prepared outside purple LED for growth basis Prolong piece；Light emitting diode (LED) chip with vertical structure finally is made in purple LED epitaxial wafer, comprising the following steps:
2.1) after the P-GaN surface clean of purple LED epitaxial wafer, substrate is polished directly, is carried out on the surface P-GaN Gluing and laser scribing, then the oxide layer on the surface P-GaN is removed, it is cleaned up, is dried with nitrogen with deionized water PM；
2.2) PM being carried out on the surface P-GaN and mirror electrodes being deposited, then make P electrode exposure mask with photoresist, it is rotten to carry out PM It loses and removes photoresist, then deposited by electron beam evaporation platform forms the metal layer for doubling as ohmic contact layer and reflecting mirror with glue hydatogenesis, then With glue-dispenser stripping photoresist to form p-type metal electrode figure, short annealing is then carried out, annealing temperature is 350~450 ℃；
2.3) high-temperature metal bonding technology is utilized, in N2The face P-GaN is bonded in silicon or copper by pressurization under environment or tungsten copper closes On gold base；
2.4) laser lift-off technique peeling liner bottom is utilized, is cleaned after removing；
2.5) processing first is performed etching to u-GaN, roughening treatment is carried out using soda acid to the face u-GaN, then again to u-GaN Surface treatment first makees N electrode using photoresist deposition earth silicon mask, then carries out scribe line photoetching, right after overexposure Scribing trench etch carries out silica deposition after the silica that removes photoresist again, then carries out electrode photoetching, etches dioxy after exposure SiClx；
2.6) the glue hydatogenesis of deposited by electron beam evaporation platform band forms N-type electrode metal again, then with glue-dispenser stripping photoresist To form N-type metal electrode figure, the LED of vertical structure is finally obtained.
Further, in 2.3), in the surface P-GaN, silicon or the copper or tungsten-copper alloy substrate surface point of purple LED epitaxial wafer Not Zheng Du one layer of 1~2um bond wire, then the sample being bonded in advance is put into wafer bonding machine, in N2Under protection according to The temperature and pressure parameter of setting are bonded.
Further, bonding temperature is 200~800 DEG C, bonding pressure 300N in the wafer bonding machine, and the time is 1h。
Further, substrate is cleaned on one side in the bonding process, POD steaming degree is carried out to the purple LED chip on one side, Then substrate and chip epitaxial layer are bonded.
Further, in 2.5), the etching is specially to etch u-GaN epitaxial wafer table using inductively coupled plasma body Face, the power of ICP are 400~700W, and reaction pressure is 500~800Pa, and reaction gas is the Cl of 50sccm2With 50sccm's Oxygen, etch period 3200s, the u-GaN surface roughness RMS after etching is 0.15~0.18nm, then carries out roughening treatment.
Further, the roughening treatment specifically:
3.1) u-GaN epitaxial wafer is cleaned: is sequentially placed into acetone and is cleaned by ultrasonic 2~5 minutes, 2~3 points of alcohol ultrasonic cleaning Clock carries out ultrasonic cleaning 2~3 minutes in deionized water；
3.2) u-GaN epitaxial wafer use is heated to 200~260 DEG C, after would be heated to the KOH of molten condition and uniformly smear On GaN epitaxy piece surface, stablizes temperature at 250 DEG C microwave heating, persistently corrode 8~10 minutes；
3.3) heating is closed, naturally cools to after room temperature and cleans the KOH on GaN epitaxy piece surface with deionized water again.
Further, the laser lift-off technique specifically: use point-by-point stripping technology, wavelength 248nm, spot size are The square hot spot of 2mm × 2mm, the KrF excimer laser that energy density is 500mJ/cm2 laser make radiation source, from Entire sample is scanned in sapphire side, movement speed 1.55mm/s, and after the complete sample of laser scanning, Sapphire Substrate falls off, and uses The HCI of 1:1 impregnates sample, removes the metal Ga on GaN.
Further, the purple LED epitaxial wafer preparation the following steps are included:
1.1) at a temperature of 1070~1090 DEG C, pressure be 150torr under lead to N210~30min of baking, nitridation sapphire, SiC or Si substrate, substrate thickness are 430~450 μm；
1.2) sapphire, SiC the or Si substrate after step 1 nitridation are cooled to 515~535 DEG C, pressure 800torr, Then on substrate growth thickness be 15~35nm substrate, then raise temperature to 1030~1050 DEG C, pressure be 400torr make base Bottom recrystallizes, 1.8~2.5 μm of regrowth of u-GaN repair layer；
1.3) be warming up to 1070~1090 DEG C, pressure be n-GaN layer that 200torr first grows light Si doping, with a thickness of 500 ~600nm, the n-GaN layer of regrowth weight Si doping, with a thickness of 300~400nm；
1.4) n-AlGaN current extending is grown on the basis of the heavy Si doped n-gan layer, with a thickness of 80~ 240nm；
1.5) the n+GaN layer of Si doping is grown on the basis of n-AlGaN layers, with a thickness of 2~4 μm, then growth is not mixed 500~600nm of n-GaN layer of Si；
1.6) at 740~760 DEG C of the growth temperature of trap, the growth temperature at base is 820-840 DEG C, pressure is under 200torr Grow the InGaN/GaN superlattices of the Al that undopes in 10~20 periods, the InGaN/AlGaN of 8 periods Al of regrowth doping； The multiple quantum well layer is with a thickness of 250~350nm；
1.7) 960~980 DEG C are warming up to, pressure is that 150torr grows PAlGaN layers, with a thickness of 1~200nm；It is cooled to 920~940 DEG C, pressure is the P+GaN layer that 150torr grows light Mg doping, with a thickness of 0.1~0.2 μm；Grow weight Mg doping P++GaN layers, with a thickness of 5~20nm；
1.8) CTL layers are grown, with a thickness of 10~30nm, after growth, 700~730 DEG C is cooled to and carries out annealing 60- 120min, later furnace cooling.
Further, in 1.6), 10~20 periodic thicknesses of the first growth undope Al's for 80~120nm InGaN/GaN superlattices, specifically: the first GaN-cap layer of 30~40nm of growth, the barrierGaN layer of 5~15nm of regrowth, Finally grow the InGaN well layer of 1.5~5nm；The InGaN/ that the Al that 8 periodic thicknesses of the regrowth are 100~150nm is adulterated AlGaN, specifically: the barrierInGaN layer of 5~15nm is first grown, the AlGaN well layer of 1.5~5nm of regrowth is finally grown The GaN-cap layer of 30~40nm.
Compared with prior art, the present invention at least has the advantages that
A kind of preparation method of vertical structure purple LED chip is made with the substrate with low temperature u-GaN repair layer and substrate For growth basis, then, other each layer extensions is successively grown on the smooth surface u-GaN, LED epitaxial wafer is prepared；Finally Vertical structure LED is made in purple LED epitaxial wafer, is mainly included the following links: depositing to form reflection on LED epitaxial wafer surface Mirror, and metal electrode figure is produced, metal electrode patterned surface is bonded on metallic substrates using high-temperature metal bonding technology, And utilize laser lift-off technique peeling liner bottom；Another pole metal electrode figure is produced on the surface u-GaN.
Further, the preferable substrate of conductive capability is used, operating current meets and exceeds 1A/mm2, under pulse mode Even up to 2.5-3A/mm2, like products dimension orthogonal fabric chip significantly promotes than the operating current of horizontal chip.It adopts With wafer bonding technique, uses the good silicon substrate of heating conduction or metal material to replace sapphire as substrate, can effectively solve Certainly heat dissipation problem makes the heat dissipation performance of product obtain significant improvement, to thoroughly solve the problems, such as that heat dissipation is difficult.
Further, it prepares using wafer bonding technique in vertical structure LED, low stress eutectic bonding technology is realized high Reliability substrate bonding is used the good silicon substrate of heating conduction or metal material to replace sapphire as substrate, can effectively be solved Certainly heat dissipation problem makes the heat dissipation performance of product obtain significant improvement, to thoroughly solve the problems, such as that heat dissipation is difficult.
Further, it by wafer bonding to silicon or copper or tungsten-copper alloy substrate, can be saved in chip manufacture processing procedure Back segment grinding technics, after forming vertical structure, U-GaN becomes light-emitting surface, is rough surface, will increase LED light emission rate, into one Step improves device photoelectric efficiency.
Further, dry method ICP etching has first been carried out, anisotropic, controllability is good, and the surface after dry etching has had Certain roughness, as long as but the short time can be obtained outside the u-GaN for meeting roughening requirement on the basis of this rough surface Prolong piece, etching precision is high.
Further, LED component etch step is simplified, while improving electric current transmission, reduces electric current stacking effect； Vertical structure LED is in conjunction with metal bonding, it will plays greater advantages, such as unidirectionally goes out light, technique simplifies, and device efficiency is further It improves.
Further, using the technology removed point by point, good peeling effect can be obtained.In order to which moment generation will be removed High pressure nitrogen is effectively exported and is discharged, and company takes the technology path of implementation laser lift-off after first progress chip area segmentation, The influences of the shock effects to functional area material such as removing instantaneous pressure nitrogen can be effectively reduced.Simultaneously to laser lift-off energy Adjustment is optimized in the technological parameters such as amount, pulse width, process velocity, in addition equipment itself has stable excellent performance, So that vertical chip product photoelectric properties and yields are substantially improved, it is ensured that light emitting diode (LED) chip with vertical structure industrialization it is implementable Property.
Further, epitaxial wafer using repair layer epitaxial structure design, between substrate and epitaxial layer be inserted into repair layer and Substrate effectively reduces the collocation degree between epitaxial layer and substrate, while further discharging extension ply stress to extension structure optimization. Angularity is less than 250km-1.Low-dislocation-density extension, it is brilliant in being formed on substrate before epitaxial growth by pre-nucleating method The preferable nucleus of weight, provides the basis of subsequent epitaxial high-quality growth, and dislocation density is lower than 5E108/cm2。
Further, multiple quantum well layer is asymmetric chirp band structure, loads asymmetric chirp energy band in LED active layer Structure is reduced the carrier wave function mismatch generated based on LED quantum well layer due to polarity effect, keeps its distribution proportion more equal It is even.The internal quantum efficiency of LED component is improved, chip light emitting efficiency is promoted.
In conclusion it is larger using vertical structure LED single chip power prepared by this method, reduce series-parallel LED Quantity, it might even be possible to realize and user demand is met with single-chip, while simplify driving circuit design, greatly improve LED product Reliability and service life.
Below by drawings and examples, technical scheme of the present invention will be described in further detail.
[Detailed description of the invention]
Fig. 1 is preparation method flow chart of the present invention；
Fig. 2 is preparation method bonding technology structural profile illustration of the present invention；
Fig. 3 is preparation method laser lift-off structural profile illustration of the present invention；
Fig. 4 is preparation method etching technics structural profile illustration of the present invention；
Fig. 5 is preparation method roughening process structural profile illustration of the present invention；
Fig. 6 is SEM figure in interface after preparation method of the present invention bonding.
[specific embodiment]
Refering to Figure 1, the invention discloses a kind of preparation method of vertical structure purple LED chip, with low Then warm u-GaN repair layer and the substrate of substrate, successively grow other each layers on the smooth surface u-GaN as growth basis Purple LED epitaxial wafer is prepared in extension；Vertical structure LED finally is made in purple LED epitaxial wafer, mainly includes following ring Section: depositing to form reflecting mirror on LED epitaxial wafer surface, and produce metal electrode figure, will be golden using high-temperature metal bonding technology Belong to electrode pattern surface bond on metallic substrates, and utilizes laser lift-off technique peeling liner bottom；It is produced on the surface u-GaN another Pole metal electrode figure.
Bonding technology is after crystal column surface to be bonded to be prepared to bonding layer material, two wafers to be fit together and utilized External energy makes formation covalent bond between the atom of material interface form unified material, and it is strong which has preferable tool Degree, it is ensured that the implementation of subsequent process flow.
Prepare vertical structure purple LED chip specific steps are as follows:
2.1) after the P-GaN surface clean of purple LED epitaxial wafer, substrate is polished directly, is carried out on the surface P-GaN Gluing and laser scribing, then the oxide layer on the surface P-GaN is removed, it is cleaned up, is dried with nitrogen with deionized water PM；
2.2) PM being carried out on the surface P-GaN and mirror electrodes being deposited, then make P electrode exposure mask with photoresist, it is rotten to carry out PM It loses and removes photoresist, then deposited by electron beam evaporation platform forms the metal layer for doubling as ohmic contact layer and reflecting mirror with glue hydatogenesis, then With glue-dispenser stripping photoresist to form p-type metal electrode figure, short annealing is then carried out, annealing temperature is 350~450 ℃；
2.3) high-temperature metal bonding technology is utilized, in N2The face P-GaN is bonded in silicon or copper by pressurization under environment or tungsten copper closes On gold base；It please refers to shown in Fig. 2, in the surface P-GaN, silicon or the copper or tungsten-copper alloy substrate surface point of purple LED epitaxial wafer Not Zheng Du one layer of 1~2um bond wire, then the sample being bonded in advance is put into wafer bonding machine, in wafer bonding machine Bonding temperature is 200~800 DEG C, bonding pressure 300N, time 1h, in N2Join under protection according to the temperature of setting and pressure Number is bonded, and in the bonding process, cleans substrate on one side, carries out chip POD steaming degree on one side, then will be outside substrate and chip Prolong layer to be bonded.
2.4) laser lift-off technique peeling liner bottom is utilized, is cleaned, is please referred to shown in Fig. 3, using wavelength after removing 248nm, square hot spot, the energy density 500mJ/cm that spot size is 2mm × 2mm2KrF excimer laser swash Light makees radiation source, scans entire sample from sapphire side, movement speed 1.55mm/s, blue after the complete sample of laser scanning Jewel substrate falls off, and impregnates sample with the HCI of 1:1, removes the metal Ga on GaN；
2.5) processing first is performed etching to u-GaN, please referred to shown in Fig. 4, the face u-GaN is carried out at roughening using soda acid Then reason is surface-treated u-GaN, first make N electrode using photoresist deposition earth silicon mask, then carry out scribe line light It carves, to scribing trench etch after overexposure, carries out silica deposition again after the silica that removes photoresist, then carry out electrode light It carves, etches silica after exposure；
The etching processing specifically uses inductively coupled plasma body to etch u-GaN epitaxial wafer surface, the power 400 of ICP ~700W, reaction pressure be 500~800Pa, reaction gas be 50sccm Cl2 and 50sccm O2, etch period 3200s, The roughness RMS on the surface u-GaN after etching is 0.15~0.18nm, then carries out roughening treatment, is please referred to shown in Fig. 5, specifically Are as follows:
3.1) u-GaN epitaxial wafer is cleaned: is sequentially placed into acetone and is cleaned by ultrasonic 2~5 minutes, 2~3 points of alcohol ultrasonic cleaning Clock carries out ultrasonic cleaning 2~3 minutes in deionized water；
3.2) u-GaN epitaxial wafer is heated to 200~260 DEG C, after would be heated to the KOH of molten condition and be uniformly applied to Microwave heating is stablized temperature at 250 DEG C, is persistently corroded 8~10 minutes by GaN epitaxy piece surface；
3.3) heating is closed, naturally cools to after room temperature and cleans the KOH on GaN epitaxy piece surface with deionized water again.
2.6) the glue hydatogenesis of deposited by electron beam evaporation platform band forms N-type electrode metal again, then with glue-dispenser stripping photoresist To form N-type metal electrode figure, the LED of vertical structure is finally obtained.
Wherein, the purple LED epitaxial wafer preparation the following steps are included:
1.1) at a temperature of 1070~1090 DEG C, pressure be 150torr under lead to N210~30min of baking, nitridation sapphire, SiC or Si substrate, substrate thickness are 430~450 μm；
1.2) sapphire, SiC the or Si substrate after step 1 nitridation are cooled to 515~535 DEG C, pressure 800torr, Then on substrate growth thickness be 15~35nm substrate, then raise temperature to 1030~1050 DEG C, pressure be 400torr make base Bottom recrystallizes, 1.8~2.5 μm of regrowth of u-GaN repair layer；
1.3) be warming up to 1070~1090 DEG C, pressure be n-GaN layer that 200torr first grows light Si doping, with a thickness of 500 ~600nm, the n-GaN layer of regrowth weight Si doping, with a thickness of 300~400nm；
1.4) n-AlGaN current extending is grown on the basis of the heavy Si doped n-gan layer, with a thickness of 80~ 240nm；
1.5) the n+GaN layer of Si doping is grown on the basis of n-AlGaN layers, with a thickness of 2~4 μm, then growth is not mixed 500~600nm of n-GaN layer of Si；
1.6) at 740~760 DEG C of the growth temperature of trap, the growth temperature at base is 820-840 DEG C, pressure is under 200torr The InGaN/GaN superlattices of the Al that undopes in 10~20 periods are grown, specifically: the GaN-cap layer of 30~40nm is first grown, The barrierGaN layer of 5~15nm of regrowth finally grows the InGaN well layer of 1.5~5nm；
The InGaN/AlGaN of 8 periods Al of regrowth doping；Specifically: first grow the barrierInGaN of 5~15nm Layer, the AlGaN well layer of 1.5~5nm of regrowth, finally grow 30~40nm GaN-cap layer, the multiple quantum well layer with a thickness of 250~350nm；
1.7) 960~980 DEG C are warming up to, pressure is that 150torr grows PAlGaN layers, with a thickness of 1~200nm；It is cooled to 920~940 DEG C, pressure is the P+GaN layer that 150torr grows light Mg doping, with a thickness of 0.1~0.2 μm；Grow weight Mg doping P++GaN layers, with a thickness of 5~20nm；
1.8) CTL layers are grown, with a thickness of 10~30nm, after growth, 700~730 DEG C is cooled to and carries out annealing 60- 120min, later furnace cooling.
Embodiment 1
First prepare purple LED epitaxial wafer, comprising the following steps:
1.1) at a temperature of 1070 DEG C, pressure be 150torr under lead to N2Toast 10min, nitridation sapphire, SiC or Si lining Bottom, substrate thickness are 430 μm；
1.2) sapphire, SiC the or Si substrate after step 1.1 nitridation are cooled to 515 DEG C, pressure 800torr, then On substrate growth thickness be 15nm substrate, then raise temperature to 1030 DEG C, pressure be 400torr recrystallize substrate, then The u-GaN repair layer of 1.8 μm of growth；
1.3) be warming up to 1070 DEG C, pressure be n-GaN layer that 200torr first grows light Si doping, with a thickness of 500nm, then The n-GaN layer of weight Si doping is grown, with a thickness of 300nm；
1.4) n-AlGaN current extending is grown, on the basis of the heavy Si doped n-gan layer with a thickness of 80nm；
1.5) the n+GaN layer of Si doping is grown on the basis of n-AlGaN layers, with a thickness of 2 μm, then growth does not mix Si's N-GaN layers of 500nm；
1.6) at 740 DEG C of the growth temperature of trap, the growth temperature at base is 820 DEG C, pressure is that 10 are first grown under 200torr Periodic thickness is the InGaN/GaN superlattices of the Al that undopes of 80nm, comprising: first grows the GaN-cap layer of 30nm, regrowth The barrierGaN layer of 5nm finally grows the InGaN well layer of 1.5nm；
The InGaN/AlGaN that the Al that 8 periodic thicknesses of regrowth are 100nm is adulterated, comprising: first grow 5nm's BarrierInGaN layers, the AlGaN well layer of regrowth 1.5nm finally grows the GaN-cap layer of 30nm；
1.7) 960 DEG C are warming up to, pressure is that 150torr grows PAlGaN layers, with a thickness of 1nm；920 DEG C are cooled to, pressure The P+GaN layer of light Mg doping is grown, for 150torr with a thickness of 0.1 μm；The P++GaN layer of weight Mg doping is grown, with a thickness of 5nm；
1.8) CTL layers are grown, with a thickness of 10nm, after growth, 700 DEG C is cooled to and carries out annealing 60min, later with furnace It is cooling.
Vertical structure purple LED chip, specific steps are prepared again are as follows:
2.1) after to the P-GaN surface clean of purple LED epitaxial wafer, substrate is polished directly, the surface P-GaN into Row gluing and laser scribing, then the oxide layer on the surface P-GaN is removed, it is cleaned up, is dried with nitrogen with deionized water PM；
2.2) PM being carried out on the surface P-GaN and mirror electrodes being deposited, then make P electrode exposure mask with photoresist, it is rotten to carry out PM It loses and removes photoresist, then deposited by electron beam evaporation platform forms the metal layer for doubling as ohmic contact layer and reflecting mirror with glue hydatogenesis, then With glue-dispenser stripping photoresist to form p-type metal electrode figure, short annealing is then carried out, annealing temperature is 350 DEG C；
2.3) high-temperature metal bonding technology is utilized, in N2The face P-GaN is bonded in silicon or copper by pressurization under environment or tungsten copper closes It is deposited one layer of 1um's respectively in the surface P-GaN, silicon or the copper of purple LED epitaxial wafer or tungsten-copper alloy substrate surface on gold base Then the sample being bonded in advance is put into wafer bonding machine by bond wire, bonding temperature is 200 DEG C, bonding pressure 300N, when Between be 1h, in N2It is bonded under protection according to the temperature of setting and pressure parameter；
2.4) utilize laser lift-off technique peeling liner bottom, cleaned after removing, use wavelength 248nm, spot size for The square hot spot of 2mm × 2mm, the KrF excimer laser that energy density is 500mJ/cm2 laser make radiation source, from Entire sample is scanned in sapphire side, movement speed 1.55mm/s, and after the complete sample of laser scanning, Sapphire Substrate falls off, and uses The HCI of 1:1 impregnates sample, removes the metal Ga on GaN；
2.5) processing first is performed etching to u-GaN, roughening treatment is carried out using soda acid to the face u-GaN, then to u-GaN table Surface treatment, first using photoresist deposition earth silicon mask make N electrode, then carry out scribe line photoetching, after overexposure to draw Piece trench etch carries out silica deposition after the silica that removes photoresist again, then carries out electrode photoetching, etches titanium dioxide after exposure Silicon；
The etching processing specifically uses inductively coupled plasma body to etch u-GaN epitaxial wafer surface, the power of ICP 400W, reaction pressure 500Pa, reaction gas are the Cl of 50sccm2With the oxygen of 50sccm, etch period 3200s, etching The roughness RMS on the surface u-GaN afterwards is 0.15nm, then carries out roughening treatment, specifically:
3.1) u-GaN epitaxial wafer is cleaned: it is sequentially placed into acetone and is cleaned by ultrasonic 2 minutes, alcohol ultrasonic cleaning 2 minutes, go Ultrasonic cleaning 2 minutes is carried out in ionized water；
3.2) u-GaN epitaxial wafer is heated to 200 DEG C, after would be heated to the KOH of molten condition and be uniformly applied to GaN epitaxy Microwave heating is stablized temperature at 250 DEG C, is persistently corroded 8 minutes by piece surface；
3.3) heating is closed, naturally cools to after room temperature and cleans the KOH on GaN epitaxy piece surface with deionized water again.
2.6) the glue hydatogenesis of deposited by electron beam evaporation platform band forms N-type electrode metal again, then with glue-dispenser stripping photoresist To form N-type metal electrode figure, the purple LED of vertical structure is finally obtained.
Embodiment 2
First prepare purple LED epitaxial wafer, comprising the following steps:
1.1) at a temperature of 1080 DEG C, pressure be 150torr under lead to N2Toast 20min, nitridation sapphire, SiC or Si lining Bottom, substrate thickness are 440 μm；
1.2) sapphire, SiC the or Si substrate after step 1 nitridation are cooled to 525 DEG C, pressure 800torr, then existed On substrate growth thickness be 25nm substrate, then raise temperature to 1040 DEG C, pressure be 400torr recrystallize substrate, regenerate Long 2.1 μm of u-GaN repair layer；
1.3) be warming up to 1080 DEG C, pressure be n-GaN layer that 200torr first grows light Si doping, with a thickness of 550nm, then The n-GaN layer of weight Si doping is grown, with a thickness of 350nm；
1.4) n-AlGaN current extending is grown, on the basis of the heavy Si doped n-gan layer with a thickness of 160nm；
1.5) the n+GaN layer of Si doping is grown on the basis of n-AlGaN layers, with a thickness of 3 μm, then growth does not mix Si's N-GaN layers of 550nm；
1.6) at 750 DEG C of the growth temperature of trap, the growth temperature at base is 830 DEG C, pressure is that 15 are first grown under 200torr Periodic thickness is the InGaN/GaN superlattices of the Al that undopes of 100nm, comprising: first grows the GaN-cap layer of 35nm, regrowth The barrierGaN layer of 10nm finally grows the InGaN well layer of 3.5nm；
The InGaN/AlGaN that the Al that 8 periodic thicknesses of regrowth are 130nm is adulterated, comprising: first grow 10nm's BarrierInGaN layers, the AlGaN well layer of regrowth 3.5nm finally grows the GaN-cap layer of 35nm.
1.7) 970 DEG C are warming up to, pressure is that 150torr grows PAlGaN layers, with a thickness of 100nm；930 DEG C are cooled to, pressure Power is the P+GaN layer that 150torr grows light Mg doping, with a thickness of 0.15 μm；The P++GaN layer of weight Mg doping is grown, with a thickness of 10nm；
1.8) CTL layers of growth, with a thickness of 20nm, after growth, it is cooled to 720 DEG C and carries out annealing 90min, later with furnace It is cooling.
Vertical structure purple LED chip, specific steps are prepared again are as follows:
2.1) after to the P-GaN surface clean of purple LED epitaxial wafer, substrate is polished directly, the surface P-GaN into Row gluing and laser scribing, then the oxide layer on the surface P-GaN is removed, it is cleaned up, is dried with nitrogen with deionized water PM；
2.2) PM being carried out on the surface P-GaN and mirror electrodes being deposited, then make P electrode exposure mask with photoresist, it is rotten to carry out PM It loses and removes photoresist, then deposited by electron beam evaporation platform forms the metal layer for doubling as ohmic contact layer and reflecting mirror with glue hydatogenesis, then With glue-dispenser stripping photoresist to form p-type metal electrode figure, short annealing is then carried out, annealing temperature is 400 DEG C；
2.3) high-temperature metal bonding technology is utilized, in N2The face P-GaN is bonded in silicon or copper by pressurization under environment or tungsten copper closes One layer of 1.5um is deposited respectively in the surface P-GaN, silicon or the copper of purple LED epitaxial wafer or tungsten-copper alloy substrate surface on gold base Bond wire, then the sample being bonded in advance is put into wafer bonding machine, bonding temperature be 500 DEG C, bonding pressure 300N, Time is 1h, in N2It is bonded under protection according to the temperature of setting and pressure parameter；
2.4) utilize laser lift-off technique peeling liner bottom, cleaned after removing, use wavelength 248nm, spot size for The square hot spot of 2mm × 2mm, the KrF excimer laser that energy density is 500mJ/cm2 laser make radiation source, from Entire sample is scanned in sapphire side, movement speed 1.55mm/s, and after the complete sample of laser scanning, Sapphire Substrate falls off, and uses The HCI of 1:1 impregnates sample, removes the metal Ga on GaN；
2.5) processing first is performed etching to u-GaN, roughening treatment is carried out using soda acid to the face u-GaN, then to u-GaN table Surface treatment, first using photoresist deposition earth silicon mask make N electrode, then carry out scribe line photoetching, after overexposure to draw Piece trench etch carries out silica deposition after the silica that removes photoresist again, then carries out electrode photoetching, etches titanium dioxide after exposure Silicon；
The etching processing specifically uses inductively coupled plasma body to etch u-GaN epitaxial wafer surface, the power of ICP 550W, reaction pressure 650Pa, reaction gas are the Cl of 50sccm2With the oxygen of 50sccm, etch period 3200s, etching The roughness RMS on the surface u-GaN afterwards is 0.17nm, then carries out roughening treatment, specifically:
3.1) u-GaN epitaxial wafer is cleaned: is sequentially placed into acetone and is cleaned by ultrasonic 3.5 minutes, 2.5 points of alcohol ultrasonic cleaning Clock carries out ultrasonic cleaning 2.5 minutes in deionized water；
3.2) u-GaN epitaxial wafer is heated to 230 DEG C, after would be heated to the KOH of molten condition and be uniformly applied to GaN epitaxy Microwave heating is stablized temperature at 250 DEG C, is persistently corroded 9 minutes by piece surface；
3.3) heating is closed, naturally cools to after room temperature and cleans the KOH on GaN epitaxy piece surface with deionized water again.
2.6) again the glue hydatogenesis of deposited by electron beam evaporation platform band form N-type electrode metal, then with glue-dispenser stripping photoresist To form N-type metal electrode figure, the purple LED of vertical structure is finally obtained.
Embodiment 3
First prepare purple LED epitaxial wafer, comprising the following steps:
1.1) at a temperature of 1090 DEG C, pressure be 150torr under lead to N2Toast 30min, nitridation sapphire, SiC or Si lining Bottom, substrate thickness are 450 μm；
1.2) sapphire, SiC the or Si substrate after step 1 nitridation are cooled to 535 DEG C, pressure 800torr, then existed On substrate growth thickness be 35nm substrate, then raise temperature to 1050 DEG C, pressure be 400torr recrystallize substrate, regenerate Long 2.5 μm of u-GaN repair layer；
1.3) be warming up to 1090 DEG C, pressure be n-GaN layer that 200torr first grows light Si doping, with a thickness of 600nm, then The n-GaN layer of weight Si doping is grown, with a thickness of 400nm；
1.4) n-AlGaN current extending is grown, on the basis of the heavy Si doped n-gan layer with a thickness of 240nm；
1.5) the n+GaN layer of Si doping is grown on the basis of n-AlGaN layers, with a thickness of 4 μm, then growth does not mix Si's N-GaN layers of 600nm；
1.6) at 760 DEG C of the growth temperature of trap, the growth temperature at base is 840 DEG C, pressure is that 20 are first grown under 200torr Periodic thickness is the InGaN/GaN superlattices of the Al that undopes of 120nm, comprising: first grows the GaN-cap layer of 40nm, regrowth The barrierGaN layer of 15nm finally grows the InGaN well layer of 5nm；
The InGaN/AlGaN that the Al that 8 periodic thicknesses of regrowth are 150nm is adulterated, comprising: first grow 15nm's BarrierInGaN layers, the AlGaN well layer of regrowth 5nm finally grows the GaN-cap layer of 40nm.
1.7) 980 DEG C are warming up to, pressure is that 150torr grows PAlGaN layers, with a thickness of 200nm；940 DEG C are cooled to, pressure Power is the P+GaN layer that 150torr grows light Mg doping, with a thickness of 0.2 μm；AN layers of P++G of weight Mg doping are grown, with a thickness of 20nm；
1.8) CTL layers are grown, with a thickness of 30nm, after growth, 730 DEG C is cooled to and carries out annealing 120min, Zhi Housui Furnace is cooling.
Vertical structure purple LED chip, specific steps are prepared again are as follows:
2.1) after to the P-GaN surface clean of purple LED epitaxial wafer, substrate is polished directly, the surface P-GaN into Row gluing and laser scribing, then the oxide layer on the surface P-GaN is removed, it is cleaned up, is dried with nitrogen with deionized water PM；
2.2) PM being carried out on the surface P-GaN and mirror electrodes being deposited, then make P electrode exposure mask with photoresist, it is rotten to carry out PM It loses and removes photoresist, then deposited by electron beam evaporation platform forms the metal layer for doubling as ohmic contact layer and reflecting mirror with glue hydatogenesis, then With glue-dispenser stripping photoresist to form p-type metal electrode figure, short annealing is then carried out, annealing temperature is 450 DEG C；
2.3) high-temperature metal bonding technology is utilized, in N2The face P-GaN is bonded in silicon or copper by pressurization under environment or tungsten copper closes It is deposited one layer of 2um's respectively in the surface P-GaN, silicon or the copper of purple LED epitaxial wafer or tungsten-copper alloy substrate surface on gold base Then the sample being bonded in advance is put into wafer bonding machine by bond wire, bonding temperature is 800 DEG C, bonding pressure 300N, when Between be 1h, in N2It is bonded under protection according to the temperature of setting and pressure parameter；
2.4) utilize laser lift-off technique peeling liner bottom, cleaned after removing, use wavelength 248nm, spot size for The square hot spot of 2mm × 2mm, the KrF excimer laser that energy density is 500mJ/cm2 laser make radiation source, from Entire sample is scanned in sapphire side, movement speed 1.55mm/s, and after the complete sample of laser scanning, Sapphire Substrate falls off, and uses The HCI of 1:1 impregnates sample, removes the metal Ga on GaN；
2.5) processing first is performed etching to u-GaN, roughening treatment is carried out using soda acid to the face u-GaN, then to u-GaN table Surface treatment, first using photoresist deposition earth silicon mask make N electrode, then carry out scribe line photoetching, after overexposure to draw Piece trench etch carries out silica deposition after the silica that removes photoresist again, then carries out electrode photoetching, etches titanium dioxide after exposure Silicon；
The etching processing specifically uses inductively coupled plasma body to etch u-GaN epitaxial wafer surface, the power of ICP 700W, reaction pressure 800Pa, reaction gas are the Cl of 50sccm2With the oxygen of 50sccm, etch period 3200s, etching The roughness RMS on the surface u-GaN afterwards is 0.18nm, then carries out roughening treatment, specifically:
3.1) u-GaN epitaxial wafer is cleaned: it is sequentially placed into acetone and is cleaned by ultrasonic 5 minutes, alcohol ultrasonic cleaning 3 minutes, go Ultrasonic cleaning 3 minutes is carried out in ionized water；
3.2) u-GaN epitaxial wafer is heated to 260 DEG C, after would be heated to the KOH of molten condition and be uniformly applied to GaN epitaxy Microwave heating is stablized temperature at 250 DEG C, is persistently corroded 10 minutes by piece surface；
3.3) heating is closed, naturally cools to after room temperature and cleans the KOH on GaN epitaxy piece surface with deionized water again.
2.6) the glue hydatogenesis of deposited by electron beam evaporation platform band forms N-type electrode metal again, then with glue-dispenser stripping photoresist To form N-type metal electrode figure, the purple LED of vertical structure is finally obtained.
It please refers to shown in Fig. 6, makes to shift substrate (such as Si, CuW, CuMo etc.) and epitaxial wafer using impressed pressure and temperature Physical chemistry bonding reaction occurs at contact interface, generates covalent bond and forms integral structure, and has excellent conductive, thermally conductive And mechanical performance, while realizing epitaxial material and shifting the thermal expansion coefficient matched between substrate, shear stress and direct stress It is smaller.The bonded layer is close uniformly, without hole and slight crack.Critical technical parameter includes bonding temperature, pressure, annealing conditions, crystalline substance Circle flatness and scaling powder, alloy ratio etc..The characteristics of for vertical gallium nitride LED core blade technolgy and material itself, in 200- In 500 DEG C, the purpose for shifting gallium nitride based LED epitaxial layer from Sapphire Substrate is realized.
It is bonded from can be seen that in SEM picture at 3D wafer surface flatness picture after the above bonding and bonded interface Wafer surface flatness is good afterwards, and bonded layer is completely embedded, it is ensured that light emitting diode (LED) chip with vertical structure has high heat conductance and good machine Tool strength characteristics.
The 1.0mm prepared using the method for the present invention2Light emitting diode (LED) chip with vertical structure performance indicator is as shown in the table
With thicker N-GaN layer as light-emitting surface, rough surface out easy to process or utilization micro-nano technology technology obtain light Light extraction efficiency can be increased to 90% or more from existing 60% by sub- crystal structure.
Using the preferable substrate of conductive capability, operating current meets and exceeds 1A/mm2, under pulse mode even up to 2.5-3A/mm2, like products dimension orthogonal fabric chip significantly promotes than the operating current of horizontal chip.
Using wafer bonding technique, the good silicon substrate of heating conduction or metal material is used to replace sapphire as substrate, it can With effective solution heat dissipation problem, the heat dissipation performance of product is made to obtain significant improvement, to thoroughly solve difficult ask of radiating Topic.
Vertical structure purple LED single chip power prepared by the present invention is larger, reduces series-parallel LED quantity, can be with It realizes and user demand is met with single-chip, while simplifying driving circuit design, greatly improve the reliability of LED product and use the longevity Life.
The above content is merely illustrative of the invention's technical idea, and this does not limit the scope of protection of the present invention, all to press According to technical idea proposed by the present invention, any changes made on the basis of the technical scheme each falls within claims of the present invention Protection scope within.

Claims (5)

1. a kind of preparation method of vertical structure purple LED chip, which is characterized in that have low temperature u-GaN repair layer and base The substrate at bottom is as growth basis, then, repairs layer surface in smooth u-GaN and successively grows other each layer extensions, be prepared into To purple LED epitaxial wafer；Light emitting diode (LED) chip with vertical structure finally is made in purple LED epitaxial wafer, comprising the following steps:
2.1) after the P-GaN surface clean of purple LED epitaxial wafer, substrate is polished directly, carries out gluing on the surface P-GaN And laser scribing, then the oxide layer on the surface P-GaN is removed, it is cleaned up, is dried with nitrogen with deionized water PM；
2.2) carry out PM on the surface P-GaN and mirror electrodes be deposited, then make P electrode exposure mask with photoresist, carry out PM corrosion and It removes photoresist, then deposited by electron beam evaporation platform forms the metal layer for doubling as ohmic contact layer and reflecting mirror with glue hydatogenesis, then spends Then jelly stripping photoresist carries out short annealing to form p-type metal electrode figure, annealing temperature is 350~450 DEG C；
2.3) high-temperature metal bonding technology is utilized, in N2The face P-GaN is bonded in silicon or copper or tungsten-copper alloy substrate by pressurization under environment On；
The key of one layer of 1~2um is deposited respectively in the surface P-GaN, silicon or the copper or tungsten-copper alloy substrate surface of purple LED epitaxial wafer Then the sample being bonded in advance is put into wafer bonding machine, in N by alloy category2According to the temperature of setting and pressure parameter under protection It is bonded, bonding temperature is 200~800 DEG C, bonding pressure 300N, time 1h in the wafer bonding machine；
2.4) laser lift-off technique peeling liner bottom is utilized, it is cleaned after removing；
2.5) processing first is performed etching to u-GaN, roughening treatment is carried out using soda acid to the face u-GaN, then again to the surface u-GaN Processing first makees N electrode using photoresist deposition earth silicon mask, scribe line photoetching is then carried out, to scribing after overexposure Trench etch carries out silica deposition after the silica that removes photoresist again, then carries out electrode photoetching, etches titanium dioxide after exposure Silicon, the etching are specially to etch u-GaN epitaxial wafer surface using inductively coupled plasma body, and the power of ICP is 400~ 700W, reaction pressure are 500~800Pa, and reaction gas is the Cl of 50sccm2With the oxygen of 50sccm, etch period is 3200s, the u-GaN surface roughness RMS after etching is 0.15~0.18nm, then carries out roughening treatment；
2.6) the glue hydatogenesis of deposited by electron beam evaporation platform band forms N-type electrode metal again, then with glue-dispenser stripping photoresist with shape At N-type metal electrode figure, the LED of vertical structure is finally obtained；
The preparation of the purple LED epitaxial wafer the following steps are included:
1.1) at a temperature of 1070~1090 DEG C, pressure be 150torr under lead to N2Toast 10~30min, nitridation sapphire, SiC or Si substrate, substrate thickness are 430~450 μm；
1.2) sapphire, SiC the or Si substrate after step 1.1 nitridation are cooled to 515~535 DEG C, pressure 800torr, so Afterwards on substrate growth thickness be 15~35nm substrate, then raise temperature to 1030~1050 DEG C, pressure be 400torr make substrate It recrystallizes, 1.8~2.5 μm of regrowth of u-GaN repair layer；
1.3) be warming up to 1070~1090 DEG C, pressure be n-GaN layer that 200torr first grows light Si doping, with a thickness of 500~ 600nm, the n-GaN layer of regrowth weight Si doping, with a thickness of 300~400nm；
1.4) n-AlGaN current extending is grown, on the basis of the heavy Si doped n-gan layer with a thickness of 80~240nm；
1.5) the n+GaN layer of Si doping is grown on the basis of n-AlGaN layers, with a thickness of 2~4 μm, then growth does not mix Si's 500~600nm of n-GaN layer；
1.6) at 740~760 DEG C of the growth temperature of trap, the growth temperature at base is 820-840 DEG C, pressure is grown under being 200torr The InGaN/GaN superlattices of the Al that undopes in 10~20 periods, the InGaN/AlGaN of 8 periods Al of regrowth doping；Volume Sub- well layer is with a thickness of 250~350nm；
1.7) 960~980 DEG C are warming up to, pressure is 150torr growing P-type AlGaN layer, with a thickness of 1~200nm；It is cooled to 920 ~940 DEG C, pressure is the P+GaN layer that 150torr grows light Mg doping, with a thickness of 0.1~0.2 μm；Grow the P++ of weight Mg doping GaN layer, with a thickness of 5~20nm；
1.8) growth CTL surface contact layer after growth, is cooled to 700~730 DEG C and anneals with a thickness of 10~30nm 60-120min, later furnace cooling.
2. a kind of preparation method of vertical structure purple LED chip according to claim 1, which is characterized in that the key Substrate is cleaned on one side during closing, and POD steaming degree is carried out to the purple LED chip on one side, then by substrate and chip epitaxial layer Bonding.
3. a kind of preparation method of vertical structure purple LED chip according to claim 1, which is characterized in that described thick Change processing specifically:
3.1) u-GaN epitaxial wafer is cleaned: is sequentially placed into acetone and is cleaned by ultrasonic 2~5 minutes, alcohol ultrasonic cleaning 2~3 minutes, It is carried out in deionized water ultrasonic cleaning 2~3 minutes；
3.2) u-GaN epitaxial wafer use is heated to 200~260 DEG C, after would be heated to the KOH of molten condition and be uniformly applied to Microwave heating is stablized temperature at 250 DEG C, is persistently corroded 8~10 minutes by GaN epitaxy piece surface；
3.3) heating is closed, naturally cools to after room temperature and cleans the KOH on GaN epitaxy piece surface with deionized water again.
4. a kind of preparation method of vertical structure purple LED chip according to claim 1, which is characterized in that described to swash Photospallation technology specifically: use point-by-point stripping technology, wavelength 248nm, square hot spot, the energy that spot size is 2mm × 2mm Metric density is that the laser of the KrF excimer laser of 500mJ/cm2 makees radiation source, scans entire sample from sapphire side, Movement speed is 1.55mm/s, and after the complete sample of laser scanning, Sapphire Substrate falls off, and impregnates sample with the HCI of 1:1, removes GaN On metal Ga.
5. a kind of preparation method of vertical structure purple LED chip according to claim 1, which is characterized in that 1.6) in, The InGaN/GaN superlattices for the Al that undopes that 10~20 periodic thicknesses are 80~120nm are first grown, specifically: first grow 30 The GaN-cap layer of~40nm, the barrierGaN layer of 5~15nm of regrowth finally grow the InGaN well layer of 1.5~5nm；
The InGaN/AlGaN that the Al that 8 periodic thicknesses of the regrowth are 100~150nm is adulterated, specifically: first growth 5~ The barrierInGaN layer of 15nm, the AlGaN well layer of 1.5~5nm of regrowth finally grow the GaN-cap layer of 30~40nm.
CN201610796255.2A 2016-08-31 2016-08-31 A kind of preparation method of vertical structure purple LED chip Active CN106328776B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610796255.2A CN106328776B (en) 2016-08-31 2016-08-31 A kind of preparation method of vertical structure purple LED chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610796255.2A CN106328776B (en) 2016-08-31 2016-08-31 A kind of preparation method of vertical structure purple LED chip

Publications (2)

Publication Number Publication Date
CN106328776A CN106328776A (en) 2017-01-11
CN106328776B true CN106328776B (en) 2019-04-09

Family

ID=57786455

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610796255.2A Active CN106328776B (en) 2016-08-31 2016-08-31 A kind of preparation method of vertical structure purple LED chip

Country Status (1)

Country Link
CN (1) CN106328776B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112164672B (en) * 2020-09-09 2023-07-11 广东省科学院半导体研究所 Substrate stripping method
CN114122227A (en) * 2022-01-26 2022-03-01 山东省科学院激光研究所 Inverted flexible GaN-based LED and preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006082687A1 (en) * 2005-02-07 2006-08-10 Mitsubishi Cable Industries, Ltd. GaN LIGHT EMITTING DIODE AND LIGHT EMITTING DEVICE
CN104638069A (en) * 2015-02-04 2015-05-20 映瑞光电科技(上海)有限公司 Vertical LED (Light-Emitting Diode) chip structure and manufacturing method thereof
CN104701427A (en) * 2015-02-13 2015-06-10 西安神光皓瑞光电科技有限公司 Vertical LED chip preparation method
CN104882517A (en) * 2015-03-30 2015-09-02 映瑞光电科技(上海)有限公司 Method for manufacturing LED chip of vertical structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006082687A1 (en) * 2005-02-07 2006-08-10 Mitsubishi Cable Industries, Ltd. GaN LIGHT EMITTING DIODE AND LIGHT EMITTING DEVICE
CN104638069A (en) * 2015-02-04 2015-05-20 映瑞光电科技(上海)有限公司 Vertical LED (Light-Emitting Diode) chip structure and manufacturing method thereof
CN104701427A (en) * 2015-02-13 2015-06-10 西安神光皓瑞光电科技有限公司 Vertical LED chip preparation method
CN104882517A (en) * 2015-03-30 2015-09-02 映瑞光电科技(上海)有限公司 Method for manufacturing LED chip of vertical structure

Also Published As

Publication number Publication date
CN106328776A (en) 2017-01-11

Similar Documents

Publication Publication Date Title
CN106449899B (en) A kind of preparation method of vertical structure blue-light LED chip
KR100735496B1 (en) Method for forming the vertically structured gan type light emitting diode device
CN101789473B (en) GaN-based vertical structure light-emitting diode and preparation method thereof
CN105826434B (en) A kind of production method of diamond heat-sink GaN base LED
CN103094434B (en) ICP etches the method that GaN base Multiple Quantum Well prepares nano-array figure
CN106784276B (en) A kind of diamond heat-sink GaN base heteropleural electrode LED production method
CN101673792B (en) Manufacturing method of GaN-based film LED based on maskless transfer photonic crystal structure
JP2008047860A (en) Method of forming rugged surface and method of manufacturing gallium nitride light-emitting diode device using the same
TW201216503A (en) Method for fabricating a vertical light-emitting diode with high brightness
CN101908587B (en) Manufacturing method of GaN-based LED by annealing to strip and inverse SiC substrate
JP4980616B2 (en) Method for fabricating a semiconductor chip
CN104701427A (en) Vertical LED chip preparation method
CN108389955B (en) Method for reducing voltage of 3D through hole superstructure LED chip by in-hole oxygen-free dry etching
CN104505445A (en) LED (Light Emitting Diode) chip for composite transparent conducting electrode and manufacturing method of LED chip
JP2002164570A (en) Gallium nitride compound semiconductor device
CN105023984A (en) GaN thick film-based vertical structure LED chip and manufacturing method thereof
CN107579139B (en) A kind of manufacturing method of vertical structure semiconductor devices
CN106328776B (en) A kind of preparation method of vertical structure purple LED chip
CN104393140B (en) A kind of vertical structure light-emitting diode chip of high reflectance and preparation method thereof
CN104465899A (en) Preparation method for LED perpendicular structure
CN103996764B (en) LED epitaxial wafer growing on Ag substrate and preparing method and application of LED epitaxial wafer
KR101428066B1 (en) vertical structured group 3 nitride-based light emitting diode and its fabrication methods
Li et al. Research progress in the postprocessing and application of GaN crystal
CN105047788A (en) Thin-film structure light-emitting diode (LED) chip based on silver-based metal bonding and preparation method of thin-film structure LED chip
KR101480551B1 (en) vertical structured group 3 nitride-based light emitting diode and its fabrication methods

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant