CN106328776A - Preparation method of vertical-structure purple light LED chip - Google Patents

Preparation method of vertical-structure purple light LED chip Download PDF

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CN106328776A
CN106328776A CN201610796255.2A CN201610796255A CN106328776A CN 106328776 A CN106328776 A CN 106328776A CN 201610796255 A CN201610796255 A CN 201610796255A CN 106328776 A CN106328776 A CN 106328776A
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layer
substrate
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temperature
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CN106328776B (en
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田伟
刘波波
田进
赵俊
李谊
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Middle Northwest Co Ltd Of Study On Engineering Design Institute
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
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    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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Abstract

The invention discloses a preparation method of a vertical-structure purple light LED chip. The preparation method is characterized by taking a substrate provided with a low-temperature u-GaN repairing layer and a base as a growth foundation, then sequentially growing epitaxies of other layers at the smooth surface of the u-GaN repairing layer so as to acquire a purple light LED epitaxial wafer; and finally preparing the purple light LED epitaxial wafer into a vertical-structure LED. The process of preparing the purple light LED epitaxial wafer into an LED with a vertical structure mainly comprises the steps of performing deposition at the surface of the LED epitaxial wafer to form a reflector, preparing a metal electrode pattern, bonding the surface of the metal electrode pattern to a metal base plate by using a high-temperature metal bonding technology, and de-bonding the substrate by using a laser de-bonding technology; preparing another metal electrode pattern at the surface of the u-GaN repairing layer. The prepared vertical-structure LED single chip is high in power, the number of series-parallel connection LEDs is reduced, and user requirements can be met by the single chip. Meanwhile, the design of a driving circuit is simplified, and reliability of an LED product is greatly improved, and the service life of the LED product is greatly prolonged.

Description

A kind of preparation method of vertical stratification purple LED chip
[technical field]
The invention belongs to technical field of semiconductors, be specifically related to the preparation method of a kind of vertical stratification purple LED chip.
[background technology]
The application of semiconductor lighting is the most significantly accelerated, and its effect has obtained market accreditation, but it is in whole illumination The permeability in market is the most relatively low.Domestic LED illumination application market not yet becomes the leading force of industry development.Semiconductor lighting Application market, particularly function lighting market are in the initial stage of development, and future space is huge.
Traditional formal dress structure LED chip, p-type GaN doping difficulty causes hole low and is difficult to long thickness And causing electric current to be difficult to diffusion, the most commonly used method preparing super thin metal thin film or ito thin film on p-type GaN surface reaches Obtain to electric current and uniformly spread.But metal film electrode layer part to be absorbed light reduces light extraction efficiency, if the thinning anti-mistake of thickness Limit again current-diffusion layer and realize the most even reliable current spread on p-type GaN layer surface.Although ITO light transmittance is up to 90%, but electrical conductivity is not as good as metal, and the diffusion effect of electric current is the most limited.And the electrode of this structure and lead-in wire are accomplished light Face, can block some light during work.Therefore, this p-type contact structures constrain the operating current size of LED chip.Another Aspect, the PN junction heat of this structure is derived by Sapphire Substrate, in view of sapphire heat conductivity is the lowest, to large-sized For power-type chip, thermally conductive pathways is longer, and the thermal resistance of this LED chip is relatively big, and operating current is also restrained.
Vertical stratification high-power chip technology is as core technology foremost, also in the industrialization initial stage, domestic substantially Still belong to blank.The most domestic only semiconductor lighting has had and has exceeded tens billion of market scales every year, along with product skill Art and the maturation in market, market scale from now on also will continue to increase, and therefore this Project Product market development prospect is the most wide, Commercial value is huge.
[summary of the invention]
The technical problem to be solved is for above-mentioned deficiency of the prior art,.
The present invention is by the following technical solutions:
The preparation method of a kind of vertical stratification purple LED chip, makees with the substrate with low temperature u-GaN repair layer and substrate For growth basis, then, grow other each layer extensions successively on smooth u-GaN repair layer surface, prepare outside purple LED Prolong sheet；Finally purple LED epitaxial wafer is made light emitting diode (LED) chip with vertical structure, comprises the following steps:
2.1), after the P-GaN surface clean of purple LED epitaxial wafer, substrate is ground polishing, carries out on P-GaN surface Gluing and laser scribing, then remove the oxide layer on P-GaN surface, cleaning up with deionized water PM, nitrogen dries up；
2.2) carry out PM on P-GaN surface and be deposited with mirror electrodes, make P electrode mask the most with photoresist, carry out PM rotten Losing and remove photoresist, then the glue hydatogenesis of deposited by electron beam evaporation platform band forms the metal level doubling as ohmic contact layer and reflecting mirror, then With glue-dispenser stripping photoresist to form p-type metal electrode figure, then carrying out short annealing, annealing temperature is 350～450 ℃；
2.3) high-temperature metal bonding technology is utilized, at N2Pressurize under environment and P-GaN face is bonded in silicon or copper or tungsten copper conjunction On gold base；
2.4) utilize at the bottom of laser lift-off technique peeling liner, be carried out after stripping；
2.5) first u-GaN is performed etching process, use soda acid to carry out roughening treatment, the most again to u-GaN in u-GaN face Surface processes, and first uses photoresist deposition earth silicon mask to make N electrode, then carries out scribe line photoetching, right after overexposure Scribe line etches, and carries out silica deposit after the silicon dioxide that removes photoresist again, then carries out electrode photoetching, exposes after etching dioxy SiClx；
2.6) the glue hydatogenesis of deposited by electron beam evaporation platform band forms N-type electrode metal again, then uses glue-dispenser stripping photoresist To form N-type metal electrode figure, finally give the LED of vertical stratification.
Further, 2.3) in, P-GaN surface, silicon or copper or tungsten-copper alloy substrate surface at purple LED epitaxial wafer divide Not Zheng Du one layer 1～the bond wire of 2um, then the sample being bonded in advance is put in wafer bonding machine, at N2Under protection according to The temperature and the pressure parameter that set are bonded.
Further, in described wafer bonding machine, bonding temperature is 200～800 DEG C, and bonding pressure is 300N, and the time is 1h。
Further, described bonding process cleans substrate, while described purple LED chip is carried out POD steaming degree, Then substrate and chip epitaxial layer are bonded.
Further, 2.5) in, described etching is specially and uses inductively coupled plasma etching u-GaN epitaxial wafer table Face, the power of ICP is 400～700W, and reaction pressure is 500～800Pa, and reacting gas is the Cl of 50sccm2With 50sccm's Oxygen, etch period is 3200s, and u-GaN surface roughness RMS after etching is 0.15～0.18nm, then carries out roughening treatment.
Further, described roughening treatment particularly as follows:
3.1) u-GaN epitaxial wafer is cleaned: be sequentially placed into acetone ultrasonic cleaning 2～5 minutes, ethanol ultrasonic cleaning 2～3 points Clock, carries out ultrasonic cleaning 2～3 minutes in deionized water；
3.2) u-GaN epitaxial wafer used be heated to 200～260 DEG C, after would be heated to the KOH uniform application of molten condition On GaN epitaxy sheet surface, microwave heating makes temperature stabilization at 250 DEG C, persistently corrodes 8～10 minutes；
3.3) close heating, after naturally cooling to room temperature, clean the KOH on GaN epitaxy sheet surface again with deionized water.
Further, described laser lift-off technique is particularly as follows: use pointwise stripping technology, and wavelength 248nm, spot size are The square hot spot of 2mm × 2mm, energy density are that the laser of the KrF excimer laser of 500mJ/cm2 makees radiation source, from Whole sample is scanned in sapphire side, and translational speed is 1.55mm/s, and after the complete sample of laser scanning, Sapphire Substrate comes off, and uses The HCI of 1:1 soaks sample, removes the metal Ga on GaN.
Further, the preparation of described purple LED epitaxial wafer comprises the following steps:
1.1) at a temperature of 1070～1090 DEG C, pressure be logical N under 150torr2Baking 10～30min, nitridation sapphire, SiC or Si substrate, substrate thickness is 430～450 μm；
1.2) sapphire after step 1 being nitrogenized, SiC or Si substrate be cooled to 515～535 DEG C, pressure be 800torr, Then in the substrate that Grown thickness is 15～35nm, then raise temperature to 1030～1050 DEG C, pressure be that 400torr makes base The end, recrystallizes, the u-GaN repair layer of regrowth 1.8～2.5 μm；
1.3) be warming up to 1070～1090 DEG C, pressure be 200torr first grow light Si doping n-GaN layer, thickness is 500 ～600nm, the n-GaN layer of regrowth weight Si doping, thickness is 300～400nm；
1.4) on the basis of described heavy Si doped n-gan layer grow n-AlGaN current extending, thickness be 80～ 240nm；
1.5) growing the n+GaN layer of Si doping on the basis of n-AlGaN layer, thickness is 2～4 μm, grows subsequently and does not mix The n-GaN layer 500～600nm of Si；
1.6) the growth temperature 740 of trap～760 DEG C, the growth temperature at base is 820-840 DEG C, pressure is under 200torr The InGaN/GaN superlattices of the Al that undopes in 10～20 cycles of growth, the InGaN/AlGaN of 8 cycle Al doping of regrowth； Described MQW layer thickness is 250～350nm；
1.7) being warming up to 960～980 DEG C, pressure is that 150torr grows PAlGaN layer, and thickness is 1～200nm；It is cooled to 920～940 DEG C, pressure is the P+GaN layer that 150torr grows light Mg doping, and thickness is 0.1～0.2 μm；Growth weight Mg doping P++GaN layer, thickness is 5～20nm；
1.8) growth CTL layer, thickness is 10～30nm, after growth, is cooled to 700～730 DEG C and carries out the 60-that anneals 120min, afterwards furnace cooling.
Further, 1.6) in, 10～20 periodic thicknesses of described first growth be 80～120nm undope Al's InGaN/GaN superlattices, particularly as follows: the GaN-cap layer of first growth 30～40nm, the barrierGaN layer of regrowth 5～15nm, The finally InGaN well layer of growth 1.5～5nm；8 periodic thicknesses of described regrowth are the InGaN/ of the Al doping of 100～150nm AlGaN, particularly as follows: the barrierInGaN layer of first growth 5～15nm, the AlGaN well layer of regrowth 1.5～5nm, finally grows The GaN-cap layer of 30～40nm.
Compared with prior art, the present invention at least has the advantages that
The preparation method of a kind of vertical stratification purple LED chip, makees with the substrate with low temperature u-GaN repair layer and substrate For growth basis, then, grow other each layer extensions on smooth u-GaN surface successively, prepare LED；Finally Purple LED epitaxial wafer is made vertical structure LED, mainly includes following link: reflect at LED surface formation of deposits Mirror, and make metal electrode figure, utilize high-temperature metal bonding technology to be bonded on metallic substrates by metal electrode patterned surface, And utilize at the bottom of laser lift-off technique peeling liner；Another pole metal electrode figure is made on u-GaN surface.
Further, have employed the preferable substrate of conductive capability, operating current meets and exceeds 1A/mm2, under pulse mode Even up to 2.5-3A/mm2, like products dimension orthogonal fabric chip significantly promotes than the operating current of horizontal chip.Adopt Use wafer bonding technique, replace sapphire as substrate with the good silica-based or metal material of heat conductivility, can effectively solve Certainly heat dissipation problem, makes the heat dispersion of product obtain and significantly improves, thus thoroughly solve the problem of heat radiation difficulty.
Further, employing wafer bonding technique, low stress eutectic bonding technology in vertical structure LED is prepared, it is achieved high Reliability substrate bonding, replaces sapphire as substrate with the good silica-based or metal material of heat conductivility, can effectively solve Certainly heat dissipation problem, makes the heat dispersion of product obtain and significantly improves, thus thoroughly solve the problem of heat radiation difficulty.
Further, by wafer bonding to silicon or copper or tungsten-copper alloy substrate, can save in chip manufacture processing procedure Back segment grinding technics, after forming vertical stratification, U-GaN becomes exiting surface, and it is rough surface, can increase LED light emission rate, enter one Step improves device photoelectric efficiency.
Further, first having carried out dry method ICP etching, anisotropic, controllability is good, and the surface after dry etching has had Certain roughness, but as long as the short time i.e. can obtain meeting outside the u-GaN that roughening requires on the basis of this rough surface Prolonging sheet, etching precision is high.
Further, simplify LED component etch step, improve electric current transmission simultaneously, reduce electric current stacking effect； Vertical structure LED is in conjunction with metal bonding, it will play greater advantages, as unidirectional go out light, technique simplify, device efficiency is further Improve.
Further, the technology that pointwise is peeled off is used, it is possible to obtain good peeling effect.In order to peel off what moment produced High pressure nitrogen is effectively derived and discharges, and company takes the technology path implementing laser lift-off after first carrying out chip area segmentation, Can effectively reduce the shock effect impacts on functional area material such as stripping instantaneous pressure nitrogen.Simultaneously to laser lift-off energy The technological parameters such as amount, pulse width, process velocity are all optimized adjustment, add that equipment itself possesses stable premium properties, Vertical chip product photoelectric properties and yields are substantially improved, it is ensured that implementing of light emitting diode (LED) chip with vertical structure industrialization Property.
Further, epitaxial wafer use repair layer epitaxial structure design, between substrate and epitaxial layer insert repair layer and Substrate, effectively reduces the fit between epitaxial layer and substrate, extension structure optimization is discharged epitaxial layer stress further simultaneously. Angularity is less than 250km-1.Low-dislocation-density extension, by pre-nucleating method, formed crystalline substance before epitaxial growth on substrate The preferable nucleus of weight, it is provided that the basis of subsequent epitaxial high-quality growth, dislocation density is less than 5E108/cm2。
Further, multiple quantum well layer is asymmetric band structure of warbling, and loading asymmetric warbling at LED active layer can carry Structure, reduces the carrier wave function mismatch produced based on LED quantum well layer due to polarity effect so that it is distribution proportion is more equal Even.Improve the internal quantum efficiency of LED component, promote chip light emitting efficiency.
In sum, the vertical structure LED list chips power using this method to prepare is relatively big, decreases connection in series-parallel LED Quantity, it might even be possible to realize meeting user's request with single-chip, simplify design of drive circuit simultaneously, be greatly improved LED product Reliability and service life.
Below by drawings and Examples, technical scheme is described in further detail.
[accompanying drawing explanation]
Fig. 1 is preparation method flow chart of the present invention；
Fig. 2 is preparation method bonding technology structural profile schematic diagram of the present invention；
Fig. 3 is preparation method laser lift-off structural profile schematic diagram of the present invention；
Fig. 4 is preparation method etching technics structural profile schematic diagram of the present invention；
Fig. 5 is preparation method roughening process structural profile schematic diagram of the present invention；
Fig. 6 is SEM figure at preparation method of the present invention bonding rear interface.
[detailed description of the invention]
Refer to shown in Fig. 1, the invention discloses the preparation method of a kind of vertical stratification purple LED chip, with low The substrate of temperature u-GaN repair layer and substrate, as growth basis, then, grows other each layers on smooth u-GaN surface successively Extension, prepares purple LED epitaxial wafer；Finally purple LED epitaxial wafer is made vertical structure LED, mainly include following ring Joint: at LED surface formation of deposits reflecting mirror, and make metal electrode figure, utilize high-temperature metal bonding technology by gold Belong to electrode pattern surface bond on metallic substrates, and utilize at the bottom of laser lift-off technique peeling liner；Another is made on u-GaN surface Pole metal electrode figure.
Bonding technology be crystal column surface to be bonded is prepared bonded layer material after, two wafer are fit together and utilize External energy makes to form covalent bond between the atom of material interface and forms unified material, and it is strong that this material possesses preferable tool Degree, it is ensured that the enforcement of subsequent process flow.
Prepare vertical stratification purple LED chip to concretely comprise the following steps:
2.1), after the P-GaN surface clean of purple LED epitaxial wafer, substrate is ground polishing, carries out on P-GaN surface Gluing and laser scribing, then remove the oxide layer on P-GaN surface, cleaning up with deionized water PM, nitrogen dries up；
2.2) carry out PM on P-GaN surface and be deposited with mirror electrodes, make P electrode mask the most with photoresist, carry out PM rotten Losing and remove photoresist, then the glue hydatogenesis of deposited by electron beam evaporation platform band forms the metal level doubling as ohmic contact layer and reflecting mirror, then With glue-dispenser stripping photoresist to form p-type metal electrode figure, then carrying out short annealing, annealing temperature is 350～450 ℃；
2.3) high-temperature metal bonding technology is utilized, at N2Pressurize under environment and P-GaN face is bonded in silicon or copper or tungsten copper conjunction On gold base；Referring to shown in Fig. 2, P-GaN surface, silicon or copper or tungsten-copper alloy substrate surface at purple LED epitaxial wafer divide Not Zheng Du one layer 1～the bond wire of 2um, then the sample being bonded in advance is put in wafer bonding machine, in wafer bonding machine Bonding temperature is 200～800 DEG C, and bonding pressure is 300N, and the time is 1h, at N2According to the temperature set and pressure ginseng under protection Number is bonded, and in described bonding process, cleans substrate, while carrying out chip POD steaming degree, then by outside substrate and chip Prolong layer to be bonded.
2.4) utilize at the bottom of laser lift-off technique peeling liner, be carried out after stripping, refer to shown in Fig. 3, use wavelength 248nm, spot size be the square hot spot of 2mm × 2mm, energy density be 500mJ/cm2KrF excimer laser swash Light makees radiation source, scans whole sample from sapphire side, and translational speed is 1.55mm/s, after the complete sample of laser scanning, blue Gem substrate comes off, and soaks sample with the HCI of 1:1, removes the metal Ga on GaN；
2.5) first u-GaN is performed etching process, refer to shown in Fig. 4, use soda acid to carry out at roughening in u-GaN face Reason, then processes u-GaN surface, first uses photoresist deposition earth silicon mask to make N electrode, then carries out scribe line light Carve, after overexposure, scribe line is etched, carry out silica deposit after the silicon dioxide that removes photoresist again, then carry out electrode light Carve, expose after etching silicon dioxide；
Described etching processing specifically uses inductively coupled plasma to etch u-GaN epitaxial wafer surface, the power 400 of ICP ～700W, reaction pressure is 500～800Pa, and reacting gas is 50sccm Cl2 and 50sccm O2, and etch period is 3200s, The roughness RMS on the u-GaN surface after etching is 0.15～0.18nm, then carries out roughening treatment, refers to shown in Fig. 5, specifically For:
3.1) u-GaN epitaxial wafer is cleaned: be sequentially placed into acetone ultrasonic cleaning 2～5 minutes, ethanol ultrasonic cleaning 2～3 points Clock, carries out ultrasonic cleaning 2～3 minutes in deionized water；
3.2) u-GaN epitaxial wafer is heated to 200～260 DEG C, after would be heated to the KOH uniform application of molten condition and exist GaN epitaxy sheet surface, makes microwave heating temperature stabilization at 250 DEG C, persistently corrodes 8～10 minutes；
3.3) close heating, after naturally cooling to room temperature, clean the KOH on GaN epitaxy sheet surface again with deionized water.
2.6) the glue hydatogenesis of deposited by electron beam evaporation platform band forms N-type electrode metal again, then uses glue-dispenser stripping photoresist To form N-type metal electrode figure, finally give the LED of vertical stratification.
Wherein, the preparation of described purple LED epitaxial wafer comprises the following steps:
1.1) at a temperature of 1070～1090 DEG C, pressure be logical N under 150torr2Baking 10～30min, nitridation sapphire, SiC or Si substrate, substrate thickness is 430～450 μm；
1.2) sapphire after step 1 being nitrogenized, SiC or Si substrate be cooled to 515～535 DEG C, pressure be 800torr, Then in the substrate that Grown thickness is 15～35nm, then raise temperature to 1030～1050 DEG C, pressure be that 400torr makes base The end, recrystallizes, the u-GaN repair layer of regrowth 1.8～2.5 μm；
1.3) be warming up to 1070～1090 DEG C, pressure be 200torr first grow light Si doping n-GaN layer, thickness is 500 ～600nm, the n-GaN layer of regrowth weight Si doping, thickness is 300～400nm；
1.4) on the basis of described heavy Si doped n-gan layer grow n-AlGaN current extending, thickness be 80～ 240nm；
1.5) growing the n+GaN layer of Si doping on the basis of n-AlGaN layer, thickness is 2～4 μm, grows subsequently and does not mix The n-GaN layer 500～600nm of Si；
1.6) the growth temperature 740 of trap～760 DEG C, the growth temperature at base is 820-840 DEG C, pressure is under 200torr The InGaN/GaN superlattices of the Al that undopes in 10～20 cycles of growth, particularly as follows: the GaN-cap layer of first growth 30～40nm, The barrierGaN layer of regrowth 5～15nm, finally the InGaN well layer of growth 1.5～5nm；
The InGaN/AlGaN of 8 cycle Al doping of regrowth；Particularly as follows: the barrierInGaN of first growth 5～15nm Layer, the AlGaN well layer of regrowth 1.5～5nm, finally the GaN-cap layer of growth 30～40nm, described MQW layer thickness is 250～350nm；
1.7) being warming up to 960～980 DEG C, pressure is that 150torr grows PAlGaN layer, and thickness is 1～200nm；It is cooled to 920～940 DEG C, pressure is the P+GaN layer that 150torr grows light Mg doping, and thickness is 0.1～0.2 μm；Growth weight Mg doping P++GaN layer, thickness is 5～20nm；
1.8) growth CTL layer, thickness is 10～30nm, after growth, is cooled to 700～730 DEG C and carries out the 60-that anneals 120min, afterwards furnace cooling.
Embodiment 1
First prepare purple LED epitaxial wafer, comprise the following steps:
1.1) at a temperature of 1070 DEG C, pressure be logical N under 150torr2Baking 10min, nitridation sapphire, SiC or Si lining The end, substrate thickness is 430 μm；
1.2) sapphire after step 1.1 being nitrogenized, SiC or Si substrate be cooled to 515 DEG C, pressure be 800torr, then Be the substrate of 15nm at Grown thickness, then raise temperature to 1030 DEG C, pressure be that 400torr makes substrate recrystallize, then Grow the u-GaN repair layer of 1.8 μm；
1.3) be warming up to 1070 DEG C, pressure be 200torr first grow light Si doping n-GaN layer, thickness is 500nm, then The n-GaN layer of growth weight Si doping, thickness is 300nm；
1.4) growing n-AlGaN current extending on the basis of described heavy Si doped n-gan layer, thickness is 80nm；
1.5) growing the n+GaN layer of Si doping on the basis of n-AlGaN layer, thickness is 2 μm, grows subsequently and does not mix Si's N-GaN layer 500nm；
1.6) in the growth temperature 740 DEG C of trap, the growth temperature at base is 820 DEG C, pressure is first to grow 10 under 200torr Periodic thickness is the InGaN/GaN superlattices of the Al that undopes of 80nm, including: first grow the GaN-cap layer of 30nm, regrowth The barrierGaN layer of 5nm, finally grows the InGaN well layer of 1.5nm；
8 periodic thicknesses of regrowth are the InGaN/AlGaN of the Al doping of 100nm, including: first grow 5nm's BarrierInGaN layer, the AlGaN well layer of regrowth 1.5nm, finally grow the GaN-cap layer of 30nm；
1.7) being warming up to 960 DEG C, pressure is that 150torr grows PAlGaN layer, and thickness is 1nm；It is cooled to 920 DEG C, pressure Grow the P+GaN layer of light Mg doping for 150torr, thickness is 0.1 μm；The P++GaN layer of growth weight Mg doping, thickness is 5nm；
1.8) growth CTL layer, thickness is 10nm, after growth, is cooled to 700 DEG C and carries out the 60min that anneals, afterwards with stove Cooling.
Prepare vertical stratification purple LED chip again, concretely comprise the following steps:
2.1), after to the P-GaN surface clean of purple LED epitaxial wafer, substrate is ground polishing, enters on P-GaN surface Row gluing and laser scribing, then remove the oxide layer on P-GaN surface, cleaning up with deionized water PM, nitrogen dries up；
2.2) carry out PM on P-GaN surface and be deposited with mirror electrodes, make P electrode mask the most with photoresist, carry out PM rotten Losing and remove photoresist, then the glue hydatogenesis of deposited by electron beam evaporation platform band forms the metal level doubling as ohmic contact layer and reflecting mirror, then With glue-dispenser stripping photoresist to form p-type metal electrode figure, then carrying out short annealing, annealing temperature is 350 DEG C；
2.3) high-temperature metal bonding technology is utilized, at N2Pressurize under environment and P-GaN face is bonded in silicon or copper or tungsten copper conjunction On gold base, P-GaN surface, silicon or copper or tungsten-copper alloy substrate surface at purple LED epitaxial wafer are deposited with one layer of 1um's respectively Bond wire, then puts in wafer bonding machine by the sample being bonded in advance, and bonding temperature is 200 DEG C, and bonding pressure is 300N, time Between be 1h, at N2It is bonded according to the temperature set and pressure parameter under protection；
2.4) utilizing at the bottom of laser lift-off technique peeling liner, be carried out after stripping, employing wavelength 248nm, spot size are The square hot spot of 2mm × 2mm, energy density are that the laser of the KrF excimer laser of 500mJ/cm2 makees radiation source, from Whole sample is scanned in sapphire side, and translational speed is 1.55mm/s, and after the complete sample of laser scanning, Sapphire Substrate comes off, and uses The HCI of 1:1 soaks sample, removes the metal Ga on GaN；
2.5) first u-GaN is performed etching process, use soda acid to carry out roughening treatment, then to u-GaN table in u-GaN face Face processes, and first uses photoresist deposition earth silicon mask to make N electrode, then carries out scribe line photoetching, to drawing after overexposure Sheet trench etch, carries out silica deposit again after the silicon dioxide that removes photoresist, then carry out electrode photoetching, exposes after etching titanium dioxide Silicon；
Described etching processing specifically uses inductively coupled plasma to etch u-GaN epitaxial wafer surface, the power of ICP 400W, reaction pressure is 500Pa, and reacting gas is the Cl of 50sccm2With the oxygen of 50sccm, etch period is 3200s, etching After the roughness RMS on u-GaN surface be 0.15nm, then carry out roughening treatment, particularly as follows:
3.1) u-GaN epitaxial wafer is cleaned: be sequentially placed into acetone ultrasonic cleaning 2 minutes, ethanol ultrasonic cleaning 2 minutes, go Ionized water carries out ultrasonic cleaning 2 minutes；
3.2) u-GaN epitaxial wafer is heated to 200 DEG C, after would be heated to the KOH uniform application of molten condition in GaN epitaxy Sheet surface, makes microwave heating temperature stabilization at 250 DEG C, persistently corrodes 8 minutes；
3.3) close heating, after naturally cooling to room temperature, clean the KOH on GaN epitaxy sheet surface again with deionized water.
2.6) the glue hydatogenesis of deposited by electron beam evaporation platform band forms N-type electrode metal again, then uses glue-dispenser stripping photoresist To form N-type metal electrode figure, finally give the purple LED of vertical stratification.
Embodiment 2
First prepare purple LED epitaxial wafer, comprise the following steps:
1.1) at a temperature of 1080 DEG C, pressure be logical N under 150torr2Baking 20min, nitridation sapphire, SiC or Si lining The end, substrate thickness is 440 μm；
1.2) sapphire after step 1 being nitrogenized, SiC or Si substrate be cooled to 525 DEG C, pressure be 800torr, then exist Grown thickness is the substrate of 25nm, then raise temperature to 1040 DEG C, pressure be that 400torr makes substrate recrystallize, regeneration The u-GaN repair layer of long 2.1 μm；
1.3) be warming up to 1080 DEG C, pressure be 200torr first grow light Si doping n-GaN layer, thickness is 550nm, then The n-GaN layer of growth weight Si doping, thickness is 350nm；
1.4) growing n-AlGaN current extending on the basis of described heavy Si doped n-gan layer, thickness is 160nm；
1.5) growing the n+GaN layer of Si doping on the basis of n-AlGaN layer, thickness is 3 μm, grows subsequently and does not mix Si's N-GaN layer 550nm；
1.6) in the growth temperature 750 DEG C of trap, the growth temperature at base is 830 DEG C, pressure is first to grow 15 under 200torr Periodic thickness is the InGaN/GaN superlattices of the Al that undopes of 100nm, including: first grow the GaN-cap layer of 35nm, regrowth The barrierGaN layer of 10nm, finally grows the InGaN well layer of 3.5nm；
8 periodic thicknesses of regrowth are the InGaN/AlGaN of the Al doping of 130nm, including: first grow 10nm's BarrierInGaN layer, the AlGaN well layer of regrowth 3.5nm, finally grow the GaN-cap layer of 35nm.
1.7) being warming up to 970 DEG C, pressure is that 150torr grows PAlGaN layer, and thickness is 100nm；It is cooled to 930 DEG C, pressure Power is the P+GaN layer that 150torr grows light Mg doping, and thickness is 0.15 μm；The P++GaN layer of growth weight Mg doping, thickness is 10nm；
1.8) growth CTL layer, thickness is 20nm, after growth, is cooled to 720 DEG C and carries out the 90min that anneals, afterwards with stove Cooling.
Prepare vertical stratification purple LED chip again, concretely comprise the following steps:
2.1), after to the P-GaN surface clean of purple LED epitaxial wafer, substrate is ground polishing, enters on P-GaN surface Row gluing and laser scribing, then remove the oxide layer on P-GaN surface, cleaning up with deionized water PM, nitrogen dries up；
2.2) carry out PM on P-GaN surface and be deposited with mirror electrodes, make P electrode mask the most with photoresist, carry out PM rotten Losing and remove photoresist, then the glue hydatogenesis of deposited by electron beam evaporation platform band forms the metal level doubling as ohmic contact layer and reflecting mirror, then With glue-dispenser stripping photoresist to form p-type metal electrode figure, then carrying out short annealing, annealing temperature is 400 DEG C；
2.3) high-temperature metal bonding technology is utilized, at N2Pressurize under environment and P-GaN face is bonded in silicon or copper or tungsten copper conjunction On gold base, P-GaN surface, silicon or copper or tungsten-copper alloy substrate surface at purple LED epitaxial wafer are deposited with one layer of 1.5um respectively Bond wire, then the sample being bonded in advance is put in wafer bonding machine, bonding temperature is 500 DEG C, and bonding pressure is 300N, Time is 1h, at N2It is bonded according to the temperature set and pressure parameter under protection；
2.4) utilizing at the bottom of laser lift-off technique peeling liner, be carried out after stripping, employing wavelength 248nm, spot size are The square hot spot of 2mm × 2mm, energy density are that the laser of the KrF excimer laser of 500mJ/cm2 makees radiation source, from Whole sample is scanned in sapphire side, and translational speed is 1.55mm/s, and after the complete sample of laser scanning, Sapphire Substrate comes off, and uses The HCI of 1:1 soaks sample, removes the metal Ga on GaN；
2.5) first u-GaN is performed etching process, use soda acid to carry out roughening treatment, then to u-GaN table in u-GaN face Face processes, and first uses photoresist deposition earth silicon mask to make N electrode, then carries out scribe line photoetching, to drawing after overexposure Sheet trench etch, carries out silica deposit again after the silicon dioxide that removes photoresist, then carry out electrode photoetching, exposes after etching titanium dioxide Silicon；
Described etching processing specifically uses inductively coupled plasma to etch u-GaN epitaxial wafer surface, the power of ICP 550W, reaction pressure is 650Pa, and reacting gas is the Cl of 50sccm2With the oxygen of 50sccm, etch period is 3200s, etching After the roughness RMS on u-GaN surface be 0.17nm, then carry out roughening treatment, particularly as follows:
3.1) u-GaN epitaxial wafer is cleaned: be sequentially placed into acetone ultrasonic cleaning 3.5 minutes, ethanol ultrasonic cleaning 2.5 points Clock, carries out ultrasonic cleaning 2.5 minutes in deionized water；
3.2) u-GaN epitaxial wafer is heated to 230 DEG C, after would be heated to the KOH uniform application of molten condition in GaN epitaxy Sheet surface, makes microwave heating temperature stabilization at 250 DEG C, persistently corrodes 9 minutes；
3.3) close heating, after naturally cooling to room temperature, clean the KOH on GaN epitaxy sheet surface again with deionized water.
2.6) the glue hydatogenesis of deposited by electron beam evaporation platform band forms N-type electrode metal again, then uses glue-dispenser stripping photoresist To form N-type metal electrode figure, finally give the purple LED of vertical stratification.
Embodiment 3
First prepare purple LED epitaxial wafer, comprise the following steps:
1.1) at a temperature of 1090 DEG C, pressure be logical N under 150torr2Baking 30min, nitridation sapphire, SiC or Si lining The end, substrate thickness is 450 μm；
1.2) sapphire after step 1 being nitrogenized, SiC or Si substrate be cooled to 535 DEG C, pressure be 800torr, then exist Grown thickness is the substrate of 35nm, then raise temperature to 1050 DEG C, pressure be that 400torr makes substrate recrystallize, regeneration The u-GaN repair layer of long 2.5 μm；
1.3) be warming up to 1090 DEG C, pressure be 200torr first grow light Si doping n-GaN layer, thickness is 600nm, then The n-GaN layer of growth weight Si doping, thickness is 400nm；
1.4) growing n-AlGaN current extending on the basis of described heavy Si doped n-gan layer, thickness is 240nm；
1.5) growing the n+GaN layer of Si doping on the basis of n-AlGaN layer, thickness is 4 μm, grows subsequently and does not mix Si's N-GaN layer 600nm；
1.6) in the growth temperature 760 DEG C of trap, the growth temperature at base is 840 DEG C, pressure is first to grow 20 under 200torr Periodic thickness is the InGaN/GaN superlattices of the Al that undopes of 120nm, including: first grow the GaN-cap layer of 40nm, regrowth The barrierGaN layer of 15nm, finally grows the InGaN well layer of 5nm；
8 periodic thicknesses of regrowth are the InGaN/AlGaN of the Al doping of 150nm, including: first grow 15nm's BarrierInGaN layer, the AlGaN well layer of regrowth 5nm, finally grow the GaN-cap layer of 40nm.
1.7) being warming up to 980 DEG C, pressure is that 150torr grows PAlGaN layer, and thickness is 200nm；It is cooled to 940 DEG C, pressure Power is the P+GaN layer that 150torr grows light Mg doping, and thickness is 0.2 μm；The P++G aN layer of growth weight Mg doping, thickness is 20nm；
1.8) growth CTL layer, thickness is 30nm, after growth, be cooled to 730 DEG C carry out anneal 120min, afterwards with Stove cools down.
Prepare vertical stratification purple LED chip again, concretely comprise the following steps:
2.1), after to the P-GaN surface clean of purple LED epitaxial wafer, substrate is ground polishing, enters on P-GaN surface Row gluing and laser scribing, then remove the oxide layer on P-GaN surface, cleaning up with deionized water PM, nitrogen dries up；
2.2) carry out PM on P-GaN surface and be deposited with mirror electrodes, make P electrode mask the most with photoresist, carry out PM rotten Losing and remove photoresist, then the glue hydatogenesis of deposited by electron beam evaporation platform band forms the metal level doubling as ohmic contact layer and reflecting mirror, then With glue-dispenser stripping photoresist to form p-type metal electrode figure, then carrying out short annealing, annealing temperature is 450 DEG C；
2.3) high-temperature metal bonding technology is utilized, at N2Pressurize under environment and P-GaN face is bonded in silicon or copper or tungsten copper conjunction On gold base, P-GaN surface, silicon or copper or tungsten-copper alloy substrate surface at purple LED epitaxial wafer are deposited with one layer of 2um's respectively Bond wire, then puts in wafer bonding machine by the sample being bonded in advance, and bonding temperature is 800 DEG C, and bonding pressure is 300N, time Between be 1h, at N2It is bonded according to the temperature set and pressure parameter under protection；
2.4) utilizing at the bottom of laser lift-off technique peeling liner, be carried out after stripping, employing wavelength 248nm, spot size are The square hot spot of 2mm × 2mm, energy density are that the laser of the KrF excimer laser of 500mJ/cm2 makees radiation source, from Whole sample is scanned in sapphire side, and translational speed is 1.55mm/s, and after the complete sample of laser scanning, Sapphire Substrate comes off, and uses The HCI of 1:1 soaks sample, removes the metal Ga on GaN；
2.5) first u-GaN is performed etching process, use soda acid to carry out roughening treatment, then to u-GaN table in u-GaN face Face processes, and first uses photoresist deposition earth silicon mask to make N electrode, then carries out scribe line photoetching, to drawing after overexposure Sheet trench etch, carries out silica deposit again after the silicon dioxide that removes photoresist, then carry out electrode photoetching, exposes after etching titanium dioxide Silicon；
Described etching processing specifically uses inductively coupled plasma to etch u-GaN epitaxial wafer surface, the power of ICP 700W, reaction pressure is 800Pa, and reacting gas is the Cl of 50sccm2With the oxygen of 50sccm, etch period is 3200s, etching After the roughness RMS on u-GaN surface be 0.18nm, then carry out roughening treatment, particularly as follows:
3.1) u-GaN epitaxial wafer is cleaned: be sequentially placed into acetone ultrasonic cleaning 5 minutes, ethanol ultrasonic cleaning 3 minutes, go Ionized water carries out ultrasonic cleaning 3 minutes；
3.2) u-GaN epitaxial wafer is heated to 260 DEG C, after would be heated to the KOH uniform application of molten condition in GaN epitaxy Sheet surface, makes microwave heating temperature stabilization at 250 DEG C, persistently corrodes 10 minutes；
3.3) close heating, after naturally cooling to room temperature, clean the KOH on GaN epitaxy sheet surface again with deionized water.
2.6) the glue hydatogenesis of deposited by electron beam evaporation platform band forms N-type electrode metal again, then uses glue-dispenser stripping photoresist To form N-type metal electrode figure, finally give the purple LED of vertical stratification.
Refer to shown in Fig. 6, utilize impressed pressure and temperature to make transfer substrate (such as Si, CuW, CuMo etc.) and epitaxial wafer At contact interface, there is physical chemistry bonding reaction, produce covalent bond and form integrative-structure, and possess the conduction of excellence, heat conduction And mechanical performance, realize the thermal coefficient of expansion matched between epitaxial material and transfer substrate, shear stress and direct stress simultaneously Less.This bonded layer is closely uniform, without hole and slight crack.Critical technical parameter includes bonding temperature, pressure, annealing conditions, crystalline substance Circle flatness and scaling powder, alloy ratio etc..For vertical gallium nitride LED chip technique and the feature of material self, at 200- In 500 DEG C, it is achieved the purpose that gallium nitride based LED epitaxial layer is shifted from Sapphire Substrate.
3D wafer surface flatness picture after above bonding, and at bonded interface in SEM picture it can be seen that bonding Rear wafer surface flatness is good, and bonded layer is completely embedded, it is ensured that light emitting diode (LED) chip with vertical structure possesses high heat conductance and good machine Tool strength characteristics.
Use 1.0mm prepared by the inventive method2Light emitting diode (LED) chip with vertical structure performance indications are as shown in the table
With thicker N-GaN layer as exiting surface, it is easy to process rough surface or utilize micro-nano technology technology to obtain light Sub-crystal structure, can bring up to more than 90% by light extraction efficiency from existing 60%.
Have employed the preferable substrate of conductive capability, operating current meets and exceeds 1A/mm2, under pulse mode even up to 2.5-3A/mm2, like products dimension orthogonal fabric chip significantly promotes than the operating current of horizontal chip.
Use wafer bonding technique, replace sapphire as substrate with the good silica-based or metal material of heat conductivility, can Effectively to solve heat dissipation problem, make the heat dispersion of product obtain and significantly improve, thus thoroughly solve asking of heat radiation difficulty Topic.
Vertical stratification purple LED list chips power prepared by the present invention is relatively big, decreases connection in series-parallel LED quantity, permissible Realize meeting user's request with single-chip, simplify design of drive circuit simultaneously, be greatly improved the reliability of LED product and use the longevity Life.
Above content is only the technological thought that the present invention is described, it is impossible to limit protection scope of the present invention with this, every presses The technological thought proposed according to the present invention, any change done on the basis of technical scheme, each fall within claims of the present invention Protection domain within.

Claims (9)

1. the preparation method of a vertical stratification purple LED chip, it is characterised in that with low temperature u-GaN repair layer and base The substrate at the end, as growth basis, then, grows other each layer extensions successively on smooth u-GaN repair layer surface, is prepared into To purple LED epitaxial wafer；Finally purple LED epitaxial wafer is made light emitting diode (LED) chip with vertical structure, comprises the following steps:
2.1), after the P-GaN surface clean of purple LED epitaxial wafer, substrate is ground polishing, carries out gluing on P-GaN surface And laser scribing, then remove the oxide layer on P-GaN surface, and cleaning up with deionized water PM, nitrogen dries up；
2.2) carry out on P-GaN surface PM be deposited with mirror electrodes, make P electrode mask the most with photoresist, carry out PM corrosion and Removing photoresist, then the glue hydatogenesis of deposited by electron beam evaporation platform band forms the metal level doubling as ohmic contact layer and reflecting mirror, then spends Colloid stripping photoresist, to form p-type metal electrode figure, then carries out short annealing, and annealing temperature is 350～450 DEG C；
2.3) high-temperature metal bonding technology is utilized, at N2Pressurize under environment and P-GaN face is bonded in silicon or copper or tungsten-copper alloy substrate On；
2.4) utilize at the bottom of laser lift-off technique peeling liner, be carried out after stripping；
2.5) first u-GaN is performed etching process, use soda acid to carry out roughening treatment, the most again to u-GaN surface in u-GaN face Process, first use photoresist deposition earth silicon mask to make N electrode, then carry out scribe line photoetching, to scribing after overexposure Trench etch, carries out silica deposit again after the silicon dioxide that removes photoresist, then carry out electrode photoetching, exposes after etching titanium dioxide Silicon；
2.6) the glue hydatogenesis of deposited by electron beam evaporation platform band forms N-type electrode metal again, then with glue-dispenser stripping photoresist with shape Become N-type metal electrode figure, finally give the LED of vertical stratification.
The preparation method of a kind of vertical stratification purple LED chip the most according to claim 1, it is characterised in that 2.3) in, The bonding gold of one layer 1～2um it is deposited with respectively at P-GaN surface, silicon or the copper of purple LED epitaxial wafer or tungsten-copper alloy substrate surface Belong to, then the sample being bonded in advance is put in wafer bonding machine, at N2Carry out according to the temperature set and pressure parameter under protection Bonding.
The preparation method of a kind of vertical stratification purple LED chip the most according to claim 2, it is characterised in that described crystalline substance In circle bonder, bonding temperature is 200～800 DEG C, and bonding pressure is 300N, and the time is 1h.
The preparation method of a kind of vertical stratification purple LED chip the most according to claim 3, it is characterised in that described key While cleaning substrate during conjunction, described purple LED chip is carried out POD steaming degree, then by substrate and chip epitaxial layer Bonding.
The preparation method of a kind of vertical stratification purple LED chip the most according to claim 1, it is characterised in that 2.5) in, Described etching is specially and uses inductively coupled plasma etching u-GaN epitaxial wafer surface, and the power of ICP is 400～700W, instead Answering pressure is 500～800Pa, and reacting gas is the Cl of 50sccm2With the oxygen of 50sccm, etch period is 3200s, after etching U-GaN surface roughness RMS be 0.15～0.18nm, then carry out roughening treatment.
The preparation method of a kind of vertical stratification purple LED chip the most according to claim 5, it is characterised in that described slightly Change process particularly as follows:
3.1) u-GaN epitaxial wafer is cleaned: be sequentially placed into acetone ultrasonic cleaning 2～5 minutes, ethanol ultrasonic cleaning 2～3 minutes, Deionized water carries out ultrasonic cleaning 2～3 minutes；
3.2) u-GaN epitaxial wafer used be heated to 200～260 DEG C, after would be heated to the KOH uniform application of molten condition and exist GaN epitaxy sheet surface, makes microwave heating temperature stabilization at 250 DEG C, persistently corrodes 8～10 minutes；
3.3) close heating, after naturally cooling to room temperature, clean the KOH on GaN epitaxy sheet surface again with deionized water.
The preparation method of a kind of vertical stratification purple LED chip the most according to claim 1, it is characterised in that described sharp Photospallation technology is particularly as follows: use pointwise stripping technology, and wavelength 248nm, spot size are the square hot spot of 2mm × 2mm, energy Metric density is that the laser of the KrF excimer laser of 500mJ/cm2 makees radiation source, scans whole sample from sapphire side, Translational speed is 1.55mm/s, and after the complete sample of laser scanning, Sapphire Substrate comes off, and soaks sample with the HCI of 1:1, removes GaN On metal Ga.
The preparation method of a kind of vertical stratification purple LED chip the most according to claim 1, it is characterised in that described purple The preparation of light LED comprises the following steps:
1.1) at a temperature of 1070～1090 DEG C, pressure be logical N under 150torr2Baking 10～30min, nitridation sapphire, SiC or Si substrate, substrate thickness is 430～450 μm；
1.2) sapphire after step 1 being nitrogenized, SiC or Si substrate be cooled to 515～535 DEG C, pressure be 800torr, then In the substrate that Grown thickness is 15～35nm, then raise temperature to 1030～1050 DEG C, pressure be that 400torr makes substrate weight New crystallization, the u-GaN repair layer of regrowth 1.8～2.5 μm；
1.3) be warming up to 1070～1090 DEG C, pressure be 200torr first grow light Si doping n-GaN layer, thickness be 500～ 600nm, the n-GaN layer of regrowth weight Si doping, thickness is 300～400nm；
1.4) growing n-AlGaN current extending on the basis of described heavy Si doped n-gan layer, thickness is 80～240nm；
1.5) growing the n+GaN layer of Si doping on the basis of n-AlGaN layer, thickness is 2～4 μm, grows subsequently and does not mix Si's N-GaN layer 500～600nm；
1.6) the growth temperature 740 of trap～760 DEG C, the growth temperature at base is 820-840 DEG C, pressure is to grow under 200torr The InGaN/GaN superlattices of the Al that undopes in 10～20 cycles, the InGaN/AlGaN of 8 cycle Al doping of regrowth；Described MQW layer thickness is 250～350nm；
1.7) being warming up to 960～980 DEG C, pressure is that 150torr grows PAlGaN layer, and thickness is 1～200nm；Be cooled to 920～ 940 DEG C, pressure is the P+GaN layer that 150torr grows light Mg doping, and thickness is 0.1～0.2 μm；The P++ of growth weight Mg doping GaN layer, thickness is 5～20nm；
1.8) growth CTL layer, thickness is 10～30nm, after growth, is cooled to 700～730 DEG C and carries out the 60-that anneals 120min, afterwards furnace cooling.
The preparation method of a kind of vertical stratification purple LED chip the most according to claim 8, it is characterised in that 1.6) in, 10～20 periodic thicknesses of described first growth are the InGaN/GaN superlattices of the Al that undopes of 80～120nm, particularly as follows: Mr. The GaN-cap layer of long 30～40nm, the barrierGaN layer of regrowth 5～15nm, finally the InGaN trap of growth 1.5～5nm Layer；
8 periodic thicknesses of described regrowth be 100～150nm Al doping InGaN/AlGaN, particularly as follows: first growth 5～ The barrierInGaN layer of 15nm, the AlGaN well layer of regrowth 1.5～5nm, finally the GaN-cap layer of growth 30～40nm.
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CN114122227A (en) * 2022-01-26 2022-03-01 山东省科学院激光研究所 Inverted flexible GaN-based LED and preparation method thereof

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CN104701427A (en) * 2015-02-13 2015-06-10 西安神光皓瑞光电科技有限公司 Vertical LED chip preparation method
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