CN106325893A - Logic device configuration method and device - Google Patents
Logic device configuration method and device Download PDFInfo
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- CN106325893A CN106325893A CN201510331399.6A CN201510331399A CN106325893A CN 106325893 A CN106325893 A CN 106325893A CN 201510331399 A CN201510331399 A CN 201510331399A CN 106325893 A CN106325893 A CN 106325893A
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Abstract
The invention provides a logic device configuration method and device, wherein the method comprises the following steps: an appointed universal input/output GPIO sends an address signal to a logic device, wherein the address signal is used for indicating the address of the logic device; and, after the GPIO sends the address signal to the logic device, the same appointed GPIO sends a data signal used for being written in the logic device to the logic device. By means of the logic device configuration method and device disclosed by the invention, the problems that a specific access interface needs to be used in a logic device configuration process and a design circuit is complex in the related technology can be solved; therefore, requirements of an interface provided by a CPU are low; and thus, interface resources are saved.
Description
Technical field
The present invention relates to the communications field, in particular to a kind of logical device collocation method and device.
Background technology
Universal input/output (General Purpose Input Output, referred to as GPIO) mouth is applied in embedded systems
The most, user can transmit some signals by programming Control GPIO mouth output low and high level, can be used as same
Step signal or control signal.
PLD is widely used in a communications system, can carry out burning program by following several ways:
JTAG instrument/debugger is used to carry out online burning；
Use special chip cd-rom recorder that nude film is carried out off-line burning；
The data transmission interface using device to provide carries out programming to device.Conventional such as Local Bus EBI, SPI
EBI；
But above several access interfaces the most all of process chip is all supported, and it is complex to design circuit, right
CPU exports the stability of clock, and the frequency range of clock has stronger dependency.
Summary of the invention
The invention provides a kind of logical device collocation method and device, with at least solve the problems referred to above in correlation technique it
One.
According to an aspect of the invention, it is provided a kind of logical device collocation method, including: appointment universal input/defeated
Address signal is sent to logical device by outlet GPIO；Wherein, described address signal is for indicating described logical device
Address；Being sent after described logical device by described address signal at described GPIO, same described appointment GPIO will
Send to described logical device for writing the data signal of described logical device.
Alternatively, it is intended that address signal transmission is included by general I/O port GPIO to logical device: described address is believed
Number by exporting appointment wave form transmission that high and low level generates to described logical device, the quantity of described appointment waveform
Address for described logical device.
Alternatively, described appointment GPIO is described by comprising determining that before described address signal transmission to described logical device
The direction depositor specifying GPIO is set as output pin by central processor CPU.
Alternatively, the frequency of described appointment waveform is set by CPU.
Alternatively, described appointment waveform is square wave.
According to another aspect of the present invention, additionally provide a kind of logical device collocation method, including: logical device is from finger
Determine general I/O port GPIO and receive address signal；Wherein, described address signal is for indicating described logical device
Address；At described logical device after described GPIO receives described address signal, connect from same described appointment GPIO
Receive the data signal for writing described logical device.
According to an aspect of the invention, it is provided a kind of logical device configuration device, it is applied to specify universal input/defeated
Outlet GPIO, described device includes: the first sending module, for sending address signal to logical device；Wherein,
Described address signal is for indicating the address of described logical device；Second sending module, is used for described at described GPIO
Address signal sends to after described logical device, the data signal being used for writing described logical device is sent to described in patrol
Collect device.
Alternatively, the appointment wave form transmission that described address signal generates by exporting high and low level is to described logic device
Part, the address that quantity is described logical device of described appointment waveform.
Alternatively, described device also comprises determining that module, for determine the direction depositor of described appointment GPIO by
Central processor CPU is set as output pin.
Alternatively, the frequency of described appointment waveform is set by CPU.
Alternatively, described appointment waveform is square wave.
According to another aspect of the present invention, additionally provide another kind of logical device configuration device, be applied to logical device,
Described device includes: the first receiver module, for from specifying general I/O port GPIO to receive address signal；Wherein,
Described address signal is for indicating the address of described logical device；Second receiver module, is used at described logical device from institute
After stating the GPIO described address signal of reception, receive for writing described logical device from same described appointment GPIO
Data signal.
By the present invention, use and specify general I/O port GPIO to send address signal to logical device；Wherein,
This address signal is for indicating the address of logical device；At GPIO, address signal is sent after logical device, same
GPIO is specified to send the data signal being used for writing this logical device to this logical device.Solve in correlation technique
Require to use specific access interface during configuration logical device, and design the problem that circuit is complicated, and then realize
Low to the interface requirement provided needed for CPU, save the effect of interface resource.
Accompanying drawing explanation
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, the present invention
Schematic description and description be used for explaining the present invention, be not intended that inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the flow chart of logical device collocation method according to embodiments of the present invention；
Fig. 2 is the structured flowchart of logical device configuration device according to embodiments of the present invention；
Fig. 3 is the structured flowchart () of logical device configuration device according to embodiments of the present invention；
Fig. 4 is the flow chart () of logical device collocation method according to embodiments of the present invention；
Fig. 5 is the structured flowchart (two) of logical device configuration device according to embodiments of the present invention；
Fig. 6 is the schematic flow sheet of single line GPIO configuration logical device according to embodiments of the present invention.
Detailed description of the invention
Below with reference to accompanying drawing and describe the present invention in detail in conjunction with the embodiments.It should be noted that in the feelings do not conflicted
Under condition, the embodiment in the application and the feature in embodiment can be mutually combined.
It should be noted that term " first " in description and claims of this specification and above-mentioned accompanying drawing, " second "
Etc. being for distinguishing similar object, without being used for describing specific order or precedence.
Providing a kind of logical device collocation method in the present embodiment, Fig. 1 is logical device according to embodiments of the present invention
The flow chart of collocation method, as it is shown in figure 1, this flow process comprises the steps:
Step S102, it is intended that address signal is sent to logical device by general I/O port GPIO；Wherein, this ground
Location signal is for indicating the address of this logical device；
Step S104, sends address signal after logical device at GPIO, and same appointment GPIO will be used for writing
The data signal of logical device sends to this logical device.
By above-mentioned steps, by the address signal of logical device and need to write the data of logical device by single line GPIO
Signal sends to logical device, compared in correlation technique, uses JTAG instrument/debugger to carry out online burning；Or,
Use special chip cd-rom recorder that nude film is carried out off-line burning；Or, use the data transmission interface that device provides to device
Carry out programming, above-mentioned steps, solve above several access interface the most all of process chip and all support, and design
Circuit is complex, the stability to CPU output clock, and the frequency range of clock has stronger dependent ask
Topic, and then it is low to achieve the interface requirement to providing needed for CPU, saves the effect of interface resource.
In one alternate embodiment, the appointment wave form that address above mentioned signal generates by exporting high and low level is transmitted
To this logical device, the quantity of this appointment waveform is the address of above-mentioned logical device.In another alternative embodiment, above-mentioned
Address signal is CPLD register address * 8+CPLD register bit position+1.
Above-mentioned GPIO, for sending address signal and data signal to logical device, in one alternate embodiment, refers to
Determine GPIO to be sent before logical device by address signal, determine that the direction depositor of this appointment GPIO is by centre
Reason device CPU is set as output pin.
The frequency of above-mentioned appointment waveform can be adjusted, and in one alternate embodiment, arranges this appointment by CPU
The frequency of waveform.
The form of address above mentioned signal can be various ways, and in one alternate embodiment, this appointment waveform is square wave.
Receive address mode and use the mode calculating square wave, enable the system to normally work in the range of bigger baud rate, reduce
System stability is for the dependence of clock performance, the lowest to timing requirements, is suitable for using in embedded systems.
Through the above description of the embodiments, those skilled in the art is it can be understood that arrive according to above-described embodiment
Method can add the mode of required general hardware platform by software and realize, naturally it is also possible to by hardware, but a lot
In the case of the former is more preferably embodiment.Based on such understanding, technical scheme is the most in other words to existing
The part having technology to contribute can embody with the form of software product, and this computer software product is stored in one
In storage medium (such as ROM/RAM, magnetic disc, CD), including some instructions with so that a station terminal equipment (can
To be mobile phone, computer, server, or the network equipment etc.) perform the method that each embodiment of the present invention is somebody's turn to do.
Additionally providing a kind of logical device configuration device in the present embodiment, this device is used for realizing above-described embodiment and preferably
Embodiment, had carried out repeating no more of explanation.As used below, term " module " can realize making a reservation for
The software of function and/or the combination of hardware.Although the device described by following example preferably realizes with software, but
It is hardware, or the realization of the combination of software and hardware also may and be contemplated.
Fig. 2 be according to embodiments of the present invention logical device configuration device structured flowchart, be applied to specify universal input/
Delivery outlet GPIO, as in figure 2 it is shown, this device includes: the first sending module 22, for sending address signal to patrolling
Collect device；Wherein, this address signal is for indicating the address of this logical device；Second sending module 24, at this
Address signal is sent after this logical device by GPIO, sends the data signal being used for writing logical device to logic
Device.
Alternatively, the appointment wave form that address signal generates by exporting high and low level is transmitted to logical device, and this refers to
The quantity of standing wave shape is the address of logical device.
Fig. 3 is the structured flowchart () of logical device configuration device according to embodiments of the present invention, as it is shown on figure 3, should
Device also comprises determining that module 32, for determining that the direction depositor specifying GPIO is set by central processor CPU
It is set to output pin.
Alternatively, the frequency of this appointment waveform is set by CPU.
Alternatively, this appointment waveform is square wave.
Additionally providing another kind of logical device collocation method in another embodiment, Fig. 4 is according to embodiments of the present invention
The flow chart (one) of logical device collocation method, as shown in Figure 4, this flow process comprises the steps:
Step S402, logical device is from specifying general I/O port GPIO reception address signal；Wherein, this address
Signal is for indicating the address of this logical device；
Step S404, at this logical device after GPIO receives this address signal, receives from same appointment GPIO and uses
In the data signal writing this logical device.
By above-mentioned steps, logical device receives the address signal of logical device by single line GPIO and needs to write logic
The data signal of device, compared in correlation technique, uses JTAG instrument/debugger to carry out online burning；Or, make
With special chip cd-rom recorder, nude film is carried out off-line burning；Or, device is entered by the data transmission interface using device to provide
Row programming, above-mentioned steps, solve above several access interface the most all of process chip and all support, and design electricity
Road is complex, the stability to CPU output clock, and the frequency range of clock has stronger dependent problem,
And then it is low to achieve the interface requirement to providing needed for CPU, saves the effect of interface resource.
Additionally providing another kind of logical device configuration device in another embodiment, this device is used for realizing above-described embodiment
And preferred implementation, carried out repeating no more of explanation.As used below, term " module " can be real
The software of existing predetermined function and/or the combination of hardware.Although the device described by following example preferably comes real with software
Existing, but hardware, or the realization of the combination of software and hardware also may and be contemplated.
Fig. 5 is the structured flowchart (two) of logical device configuration device according to embodiments of the present invention, is applied to logical device,
As it is shown in figure 5, this device includes: the first receiver module 52, for from specifying general I/O port GPIO to receive
Address signal；Wherein, this address signal is for indicating the address of this logical device；Second receiver module 54, at this
Logical device, after this GPIO receives this address signal, receives from same this appointment GPIO and is used for writing this logic device
The data signal of part.
It should be noted that above-mentioned modules can be by software or hardware realizes, for the latter, Ke Yitong
Cross in the following manner to realize, but be not limited to this: above-mentioned module is respectively positioned in same processor；Or, above-mentioned module position respectively
In multiple processors.
Embodiments of the invention additionally provide a kind of storage medium.Alternatively, in the present embodiment, above-mentioned storage medium can
To be arranged to storage for the program code performing following steps:
S1, step S102, it is intended that address signal is sent to logical device by general I/O port GPIO；Wherein,
This address signal is for indicating the address of this logical device；
S2, sends address signal after logical device at GPIO, and same appointment GPIO will be used for writing logic device
The data signal of part sends to this logical device.
Alternatively, storage medium is also configured to storage for the program code performing following steps:
S1, logical device is from specifying general I/O port GPIO reception address signal；Wherein, this address signal is used for
Indicate the address of this logical device；
S2, at this logical device after GPIO receives this address signal, receives from same appointment GPIO and is used for writing
The data signal of this logical device.
Alternatively, in the present embodiment, above-mentioned storage medium can include but not limited to: USB flash disk, read only memory (ROM,
Read-Only Memory), random access memory (RAM, Random Access Memory), portable hard drive,
The various medium that can store program code such as magnetic disc or CD.
Alternatively, the concrete example in the present embodiment is referred to showing described in above-described embodiment and optional embodiment
Example, the present embodiment does not repeats them here.
This alternative embodiment is applicable to field of data transmission, it is provided that a kind of by single line GPIO mouth configuration FPGA
The method of device depositor.The access mode of described method design PLD is linear access mode, and utilizes
CPU single line GPIO mouth, it is achieved configuration of programmable logic devices.Single line GPIO transmits data, the first rank in two stages
Section transmission address signal, second stage transmission data signal.Address signal is sequentially output high and low electricity with prefixed time interval
The square become all one's life is transmitted, and data signal is transmitted after the address signal end of transmission, and when keeping one section
Between to judge from device.PLD receives the square-wave signal that sends of GPIO mouth and counts, and preserves and makees
For reference address, and the data that the output of GPIO second stage keeps are updated in corresponding address.The present invention passes through single line
GPIO mouth achieves the linear configurations method of PLD.
Specifically comprising the following steps that of this alternative embodiment
A, a certain road universal input/output interface GPIO of selection processor, receive programmable logic device by this road GPIO
Part input；
During B, CPU configuration of programmable logic devices, data are transmitted in each configuration in two stages, and the first stage is at this GPIO
Mouth output square wave, square wave number is the address of PLD, after square wave output, carries out second stage transmission,
GPIO output will write the data of PLD, and keeps certain time.
C, PLD end, receiving first square wave rising edge, opens timer, each rising edge
Timer will be emptied, calculate square wave number by record rising edge.Timer waits one after receiving last square wave
Close after fixing time, and by current GPIO output valve write PLD.
It is preferred that step B includes:
B1, GPIO direction depositor is set, is set as output pin；
B2, by signal sequence requirement, GPIO data register, square wave frequency scope are set；
After B3, output square wave, data hold time need to keep more than 1ms, accordingly, the time that timer expired is closed
It is also configured as 1ms.
The method of the single line GPIO configuration of programmable logic devices that alternative embodiment of the present invention proposes, does not use CPU special
With interface and the lowest to timing requirements, there is extraordinary practical value.
In an optional example of the present invention, system is mainly made up of data transmission blocks and data reception module.This number
Using MIPS framework CPU according to sending module, be responsible for the output of data, output interface is single channel GPIO.Data receiver
Module uses CPLD device, is responsible for the reception of data.In systems, this single channel GPIO is connected to data receipt unit
Input.
Input block configuration single channel GPIO is general GPIO delivery outlet, and is divided into two stage output data, the first rank
Section output access address signal, second stage output write data.Data receipt unit is according to sequential processing.
The data of concrete transmission are as follows:
Read-write operation data:
Note 1:
GPIO exports first stage data=CPLD register address * 8+CPLD register bit position+1
Fig. 6 is the schematic flow sheet of single line GPIO configuration logical device according to embodiments of the present invention, shown in Fig. 6,
Following steps are specifically included by the method for single line GPIO configuration of programmable logic devices:
Step S602: data transmission blocks configuration single channel GPIO is general GPIO delivery outlet, and calculates GPIO first
Stage output address data.
Step S604: data module send first stage data, single channel GPIO with prefixed time interval be sequentially output height,
Low level generates square wave, and the square wave number of generation is the first stage output address data calculated in step S602.
Step S606: data reception module waits square wave, after receiving first square wave rising edge, starts meter record square wave
Number, and open timer.Now starting, often capture a square wave rising edge, square wave enumerator adds one, and by timing
Device resets；Otherwise, not capturing next square wave rising edge, square wave number keeps constant, and timer continues timing.
Step S608: data transmission blocks sends second stage data, the output of single channel GPIO will write receiver module
Data, and keep the time of more than 1.5ms.
Step S610: data reception module is not after receiving square wave, and timer is closed after being 1ms, and by GPIO
The depositor correspondence bit of the data write CPLD of current output.Now complete second stage transmission.
Step S612: after data transmission blocks completes the transmission of second stage data, drags down the output of single channel GPIO.Data
Receiver module, after the operation completing to write CPLD depositor, waits 0.5ms, can start the data transmission of a new round.
In sum, realize configuration of programmable logic devices by the present invention merely with single channel GPIO, needed for CPU
The interface requirement provided is low, and saves interface resource, the lowest to timing requirements, is suitable for using in embedded systems.
Address access patterns uses the mode calculating square wave, enables the system to normally work in the range of bigger baud rate, reduces
System stability is for the dependence of clock performance.
Obviously, those skilled in the art should be understood that each module of the above-mentioned present invention or each step can be with general
Calculating device to realize, they can concentrate on single calculating device, or be distributed in multiple calculating device and formed
Network on, alternatively, they can realize, it is thus possible to by them with calculating the executable program code of device
Storage is performed by calculating device in the storage device, and in some cases, can hold with the order being different from herein
Step shown or described by row, or they are fabricated to respectively each integrated circuit modules, or by many in them
Individual module or step are fabricated to single integrated circuit module and realize.So, the present invention is not restricted to any specific hardware
Combine with software.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for the technology of this area
For personnel, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, that is made is any
Amendment, equivalent, improvement etc., should be included within the scope of the present invention.
Claims (12)
1. a logical device collocation method, it is characterised in that including:
General I/O port GPIO is specified to send address signal to logical device；Wherein, described address signal
For indicating the address of described logical device；
Being sent after described logical device by described address signal at described GPIO, same described appointment GPIO will
Send to described logical device for writing the data signal of described logical device.
Method the most according to claim 1, it is characterised in that specify general I/O port GPIO by address signal
Transmission to logical device includes:
The appointment wave form transmission extremely described logical device that described address signal generates by exporting high and low level,
The address that quantity is described logical device of described appointment waveform.
Method the most according to claim 1, it is characterised in that described address signal is sent extremely by described appointment GPIO
Include before described logical device:
Determine that the direction depositor of described appointment GPIO is set as output pin by central processor CPU.
Method the most according to claim 2, it is characterised in that the frequency of described appointment waveform is set by CPU.
Method the most according to claim 2, it is characterised in that described appointment waveform is square wave.
6. a logical device collocation method, it is characterised in that including:
Logical device is from specifying general I/O port GPIO reception address signal；Wherein, described address signal is used
In the address indicating described logical device；
At described logical device after described GPIO receives described address signal, connect from same described appointment GPIO
Receive the data signal for writing described logical device.
7. a logical device configuration device, is applied to specify general I/O port GPIO, it is characterised in that described dress
Put and include:
First sending module, for sending address signal to logical device；Wherein, described address signal is used for referring to
Show the address of described logical device；
Second sending module, for described address signal being sent after described logical device at described GPIO,
The data signal being used for writing described logical device is sent to described logical device.
Device the most according to claim 7, it is characterised in that described address signal generates by exporting high and low level
The transmission of appointment wave form to described logical device, the address that quantity is described logical device of described appointment waveform.
Device the most according to claim 7, it is characterised in that described device also includes:
Determine module, for determining that the direction depositor of described appointment GPIO is set as by central processor CPU
Output pin.
Device the most according to claim 8, it is characterised in that the frequency of described appointment waveform is set by CPU.
11. devices according to claim 8, it is characterised in that described appointment waveform is square wave.
12. 1 kinds of logical device configuration devices, are applied to logical device, it is characterised in that described device includes:
First receiver module, for from specifying general I/O port GPIO to receive address signal；Wherein, described
Address signal is for indicating the address of described logical device；
Second receiver module, is used at described logical device after described GPIO receives described address signal, from
Same described appointment GPIO receives the data signal for writing described logical device.
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| CN201510331399.6A CN106325893A (en) | 2015-06-15 | 2015-06-15 | Logic device configuration method and device |
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| CN113704147A (en) * | 2021-10-28 | 2021-11-26 | 苏州浪潮智能科技有限公司 | Multi-controller communication method, multi-controller communication device, computer equipment and storage medium |
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