CN102411535B - Navigating-SoC (System On Chip) simulating, verifying and debugging platform - Google Patents
Navigating-SoC (System On Chip) simulating, verifying and debugging platform Download PDFInfo
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Abstract
The invention discloses a navigating-SoC (System On Chip) simulating, verifying and debugging platform, which comprises a navigating-SoC verifying plate and a PC (Personal Computer) host-computer environment, wherein an RISC (Reduced Instruction Set Computer) processor and an FPGA (Field-Programmable Gate Array) are integrated onto the navigating-SoC verifying plate, and the PC host-computer environment is used for assisting the debugging and the analysis of a designer. A navigating IP (Internet Protocol) is realized on the FPGA, and the support for a hanging/operating mode is added. According to a hardware-hanging/operating state, a navigation-interrupting program is divided into a hardware-hanging period and a hardware-operating period, the introduction of intermediate-frequency data into the SoC verifying plate is finished through a UDP (User Datagram Protocol)/USB (Universal Serial Bus) protocol by a PC host computer at the hanging period, and debugging information is sequentially transmitted to the PC host computer by the SoC verifying plate. In the invention, the operating time of a code on the RISC processor is also accurately analyzed by utilizing a timer resource on the SoC verifying plate, and the real-time property of software and hardware can be analyzed. A PC host-computer end comprises a GUI (Graphical User Interface), a UDP/USB communication thread and a background database, so that a perfect verifying environment is provided for the designer.
Description
Technical field
The present invention relates to SoC(System On Chi, SOC (system on a chip)) verifying and debugging field, particularly a kind of apparatus platform of can be used for navigating SoC chip emulation, checking and debugging.
Background technology
Global navigational satellite positioning system (GNSS) is widely used in every field between decades in the past.At present GNSS has comprised the Compass(Big Dipper of the GPS of the U.S., Muscovite GLONASS, China) and the Galileo system of European Union.At civil area, most mobile device all possesses navigation feature, for people's trip provides great convenience.Many vehicles have been equipped with GPS navigation equipment, have greatly simplified the management of communications.In military field, navigational system is the most important thing of modernized war especially, the chip and the core of these equipment is navigated exactly.In navigation chip design field, the advanced level of home and overseas has a certain distance, and the chips such as Sirf, u-blox and corresponding solution have all reached high level at power consumption, degree of ripeness, reliability and cost.
Gradual perfection along with the Big Dipper two generations satellite navigation system, the design of navigation chip and research and development become again the focus of academia and industry, in order not to be limited by external chip supplier, the IP(Intellectual Property that navigates that contains of independent intellectual property right is badly in need of developing in China, ip module) and the SoC solution of RSIC processor (Reduced Instruction Set Computer, Reduced Instruction Set Computer).
The hardware-accelerated unit of so-called navigation, is called for short navigation IP, refer to net solid core that table provides or with HDL(Hardware Description Language, hardware description language) the soft core that provides of code.Navigation algorithm relates to a large amount of mathematical operations and matrix operation, adopts hardware to realize difficulty completely excessive, is difficult to modify, and extendability can be restricted, and meanwhile, navigation algorithm is also in the process of continuous evolution, and the dirigibility of hardware cannot meet the demands.On the other hand, although pure software is realized, be the focus that academia pays close attention to always, processing power, power consumption requirement balance with current RISC, cannot meet the demands.Therefore, the scheme that hardware accelerator (IP navigates) becomes main flow is closed in risc processor caryogamy, and such navigation chip solution is called for short navigation SoC(System-on-a-Chip, i.e. SOC (system on a chip)).What build such SoC system is checking and debugging part a large difficult point, and this is also a longest part consuming time, directly has influence on Time To Market.
Operation and the checking of navigation SoC chip have following features:
1. navigation IP needs the cooperation of processor, and on processor, operating software can improve the dirigibility of design.Therefore, we want simulating, verifying to as if the system of a software-hardware synergism.In different debugging schemes, algorithm software both may operate on PC main frame, also may operate on the risc processor of Target Board, and the behavior of the latter and actual chips more conforms to.
2. navigation SoC chip must be paid close attention to real-time, and navigation algorithm is processed navigation intermediate frequency data stream, and these algorithms are all to have requirement of real-time.How to designer, provide real-time information accurately and complete Debugging message to become the basic problem of navigation SoC checking.
3. the checking of navigation IP and SoC system has very high requirement to simulation velocity.The sampling rate scope 4MHz ~ 17MHz of navigation intermediate frequency data, navigation IP operates in 30MHz ~ 100MHz, the data that processor is processed 1s need up to ten million clock period, and the data that navigation algorithm is often wanted a minute just can calculate result, if simulate some special scenes, the data that need dozens of minutes, adopt HDL emulator to go emulation length that will be very consuming time completely.
4. the memory space of navigation intermediate frequency data is very large, and the sampling rate 2bit precision of 5.714MHz of take is example, and the data of 1 minute just need the data of 85.71MB; If need to carry out emulation to the flow processs such as catching, follow the tracks of and resolve under different scenes, often need 5 minutes even for more time, data volume will reach MB more than 400, and therefore data storage efficiently, importing and playback mechanism are also the problems that debug platform must solve.The importing of data also will guarantee temporal accuracy, and the sampled point that staggers all can affect the accuracy of whole system operation.
5. Fig. 1 is the SoC program operational scheme of typically navigating, and timer triggers at set intervals processor and once interrupts, and typical case is spaced apart 520us.And navigation IP with sampling interval time input intermediate frequency data, typical sampling rate is 40/7MHz or 16.368MHz.After interrupt function returns, according to the result of zone bit, can call termly principal function.(navigation IP) carries out mutual main the and hardware-accelerated unit of interrupt service routine.Program execution flow is as shown in the figure the main flow mode of operation of navigation chip.
Fig. 1 is the typical flowchart of navigation SoC running software, in the emulation field of navigation algorithm and hardware accelerator system, mainly contains at present three kinds of schemes:
Scheme one, uses hardware description language (HDL) to describe whole system, comprises that processor core and navigation IP all adopt HDL to describe, and what processor core moved is the binary executable code having compiled;
Scheme two, adopt isa simulator to carry out the emulation of navigation algorithm software, and the hardware-accelerated unit that navigates is by the emulation of HDL emulator, the two is undertaken alternately by DPI mechanism (Direct Programming Interface, the mechanism that SystemVerilog and C/C++ language are mutual) or operating system inter-process communication mechanisms;
Scheme three, the scheme of employing software-hardware synergism, the FPGA(field programmable gate array on Target Board) realize navigation IP, on X86 main frame, move navigation operations program, PC main frame and FPGA communicate by pci interface;
Scheme one can obtain the most accurate simulation result, and debugs by HDL emulator, and shortcoming is very slow, and the result that HDL emulator obtains is not directly perceived yet, only can debug in the pin signal rank of low level very.The logic of processor core (can be comprehensive) is very complicated, and the complicacy of navigation IP itself, often need several days time could emulation the data in several seconds.Meanwhile, the expense of processor core mandate is very high, high cost, and general company and Scientific Research Activities unit can't afford.
Scheme two has been accelerated the simulation velocity of processor part, but bulk velocity is still limited to the simulation performance of the hardware-accelerated unit R TL of navigation.Because software module is moved by isa simulator, Cache(buffer memory) the accurately simulation of having no idea of behavior and the sequential of bus, cannot truly reflect the behavior of SoC chip, the assessment of severe jamming designer to real-time.
Scheme three does not need to move HDL emulator, and bottleneck is transferred on the communication efficiency of PC main frame and FPGA.But will be appreciated that, it is different that software code operates in the operation result that on X86 main frame, resulting result often obtains with risc processor, X 86 processor and risc processor on framework (such as instruction set, Cache, memory management unit MMU and floating-point coprocessor) are widely different, cause in operational efficiency and the difference of operation result precision, also cannot assess software real-time.Pci interface agreement is very complicated, often needs a special main frame to move whole system.
In the playback scheme of intermediate frequency data, traditional method has two kinds:
Method one: carry out real-time simulation truly, the navigation IP realizing on FPGA is directly connected with the intermediate frequency data output port of sampling A/D chip;
Method two: carry out the playback of supported data by PCI-E interface or USB interface, according to certain sequential, intermediate frequency data is imported in FPGA;
Method one is the playback of supported data not.Can reproducing characteristic be the basic demand in SoC checking field always.In the middle of extraneous scene is often in and constantly changes, the time of occurrence of problem is random often, and this just brings very large difficulty to debugging.Therefore the playback of supported data is the prerequisite of navigation debug function, and it makes designer repeatedly to same batch data and same problem, to carry out omnibearing anatomy, thereby finds the defect in system.Get rid of the interference that the extraneous factors such as weather, place are brought, the debugging of the collection of data and SoC system is verified to these two steps separately.
Although the protocol comparison complexity that method two is used, and be all with the x86 processor on PC main frame, to move the software section of navigation algorithm, although can analyze the real-time of hardware, but cannot carry out to the real-time of software the analysis of accurate quantification, and the real-time of software is only the difficult point in navigation algorithm design.
Through the retrieval of prior art document is found, application number is " 200610012061.5 ", name is called " system for processing navigational satellite signal ", this patent provides a kind of Navsat disposal system, can gather in real time, continuously, for a long time navigation satellite signal, be sent to computing machine, and by high-speed interfaces such as USB by sampling data playback.This platform is only paid close attention to playback function, and unpromising debugging provides solution.
In retrieval, also find, Granted publication number is CN 100526910C, name is called " for the plateform system of researching and developing satellite navigation receiver ", plateform system in this patent is divided into hardware components and software section by navigation neceiver, software section runs on computing machine, and hardware components is connected in described computing machine by computer interface by computer interface.Because running software is on x86 computing machine, the analysis of software real-time just cannot be carried out, because x86 processor core flush bonding processor exists very large difference.Therefore, there is big-difference very in the ruuning situation of the operation of this platform and navigation SoC real chip, and a lot of exclusive problems of embedded system all cannot come out.
Current existing scheme is all just paid close attention to the hardware-software partition of navigation algorithm itself, only with FPGA, hardware accelerator is verified, do not pay close attention to and risc processor and navigation mutual sequential between hardware cell, not for SoC and chip design provide debugging and verification mechanism.These existing schemes cannot be assessed navigation algorithm in the real-time of true risc processor, the real-time of especially interrupting.As everyone knows, interrupting processing is to affect system stability and the very crucial factor of operational efficiency.The given software code of these existing schemes, when the later stage downloads to risc processor, there will be the leak that is difficult to debugging, has a strong impact on design schedule.
Summary of the invention
For the technical matters existing in prior art, the invention provides a kind of high efficiency, can be to navigation SoC chip emulation, checking and debug platform based on UDP/USB the agreement quantitative test of software and hardware real-time, that signal system is irrelevant.
for realizing above-mentioned object, the technical solution used in the present invention is as follows:the present invention is navigation chip design exploitation service, concern be checking and the debugging of SOC (system on a chip).First customize a SoC system verification plate, on plate, with risc processor and FPGA, be equipped with Ethernet interface or USB interface.Different from existing most of PC/FPGA collaborative simulation mechanism, in this platform, Navigator operates on risc processor.For hardware adds Suspend Mode, will navigate accelerator hardware and Abort Timer of certain stage in interrupt routine hung up.At hardware, hang up stage PC main frame intermediate frequency data imported to the FIFO(First Input First Output in FPGA by udp protocol or usb protocol), and complete the collection of Debugging message, the IP that navigates afterwards resumes operation.In order to support the precise evaluation of real-time, all these network service codes, Debugging message collect code be all placed on Non-Cacheable(can not buffer memory) region, reduce the interference to original system.Debugging gui program and the background data base of main frame Erecting and improving, allow designer can utilize these Debugging message to analyze navigation SoC chip, further improves existing algorithm framework and hardware design.
The invention provides a kind of navigation SoC chip emulation, checking and debug platform, this platform specifically comprises PC main frame and SoC system verification plate, communication between them is by UDP(User Datagram Protocol) or USB(USB (universal serial bus)) agreement carries out, described PC main frame completes intermediate frequency data to the importing of SoC system verification plate by UDP or usb protocol and handshake mechanism, and SoC system verification plate gathers Debugging message and also returns to PC main frame.
On described SoC system verification plate, comprise risc processor and fpga chip, wherein FPGA and risc processor communicate with the interface of bus mode or short time delay.Navigation IP provides with RTL form, comprehensively realizes on FPGA.On FPGA hardware, realize the navigation IP with Suspend Mode, on risc processor, move navigation algorithm, under navigation IP auxiliary, complete positioning calculation function.
Described risc processor realizes memory-mapped by memory management unit MMU and Cache manages; The peripheral hardware resource that risc processor can be controlled at least will have ethernet controller or USB controller, and is connected with PC main frame; All C/C++ programs of navigating all operate on risc processor, are divided into master routine and interrupt service routine in main body; Interrupt service routine is responsible for carrying out alternately with navigation IP, and typical interrupt is spaced apart 520 ~ 800us; Master routine utilizes the information that interrupt service routine returns to calculate coordinate, these two program flows satnav of having worked in coordination.
For real-time is assessed, risc processor should have access to three timer resources, one of them timer completes the time delay of set time, and another timer completes down trigger, and the 3rd timer completes the measurement of working time of a plurality of program segment.It is upper that these timer resources both can be distributed in FPGA, also can be inner in risc chip.
Described risc processor can conduct interviews and read and write the hardware-accelerated unit that navigates, and must configure pin according to the situation of development board and connect in FPGA.The most natural form is that FPGA and risc processor connect by on-chip bus (take ARM as example, is exactly AMBA bus) or PCI-E bus.
In the RTL code of the hardware-accelerated unit of described navigation (being called for short navigation IP), must add the support (mode enabling with clk_enable clock realizes) to Suspend Mode, the mode that ppu can be read and write by register changes operation/suspended state of navigation IP, it is suspended, then continue to carry out.
The interrupt function moving on described risc processor is divided into the hardware operation phase and hardware is hung up the stage.Hardware is hung up stage PC main frame and to FPGA, is imported in batches navigation data by Ethernet/USB interface into; On FPGA, there is corresponding FIFO to store these data; The collection of Debugging message and to return be also to complete in this stage.
Described PC end storage navigation intermediate frequency data, PC main frame is shaken hands and is communicated by letter by UDP or usb protocol with SoC witness plate.PC main frame should be with network interface or USB interface.
Described PC main frame is divided into four threads, is respectively GUI graphical interfaces thread, debug system master control thread, database thread and UDP/USB communication thread.Master control thread is responsible between other three threads the distribution of resource, the stamping-out of communication.UDP/USB communication thread is responsible for and SoC witness plate communicates.The Debugging message that database thread is come to the communications storage of classifying, and support user to retrieve these information, database thread is also responsible for calling in of intermediate frequency data data source.Graphical interfaces allows designer check Debugging message and real-time information, drawing waveforms and the operation of controlling receiver in mode intuitively.
In the present invention, at the hardware of interrupt service routine, hang up the stage, with controlled pattern, navigation intermediate frequency data is sent to the FIFO(First Input First Output in FPGA).FIFO is encapsulated as the peripheral hardware of processor place bus, is mapped to one section of region in internal memory, and processor to FIFO data writing in batches, provides data in one period in the future for Hardware I P module in the mode of memory read-write.
RISC/FPGA witness plate checks the residue of intermediate frequency data FIFO, in each interrupt function, to PC end, initiates request of data, and PC end is followed handshake mechanism navigation intermediate frequency data is returned to SoC system verification plate.The Debugging message collection procedure of risc processor end is further analyzed the logical PC end that is sent to of the relevant informations such as receiver state, Debugging message, calculation result and real time analysis.These Debugging message will be filled whole Ethernet data bag with the form of parcel, and then PC host side completes fractionation and the parsing of these packets, insert subsequently the database on backstage, gui interface is by according to designer's operation, the retrieval of database, take out these information and represent these information with the form of waveform or form, carry out the debugging that time precision is interrupt levels.
The extracode of these UDP/USB communication is by link script and MMU(memory management unit) setting, be positioned over the region of Non-Cacheable, the Cache(cache memory of risc processor) will be subject to minimum interference, so just can estimate accurately the real-time of original navigation algorithm software.And, the mode enabling by sequential logic, make the navigation IP of the upper operation of FPGA support Suspend Mode, under the control of risc processor, will be in Suspend Mode at network service stage (moving the stage of extracode) navigation IP and timer, now the software and hardware logic of navigation algorithm itself does not all have operation, designer can fully add Debugging message code, Debugging message can be collected fully, and can not be limited to the performance of risc processor, also can not have influence on the measurement of real-time.
These extracodes are that the form at Non-Cacheable allows risc processor operation, so the performance of processor is higher, bus communication bandwidth is higher, the simulation performance of whole platform is just higher.This scheme is protocol-independent, the USB2.0 of compatible main flow and UDP communication protocol.
technique effect of the present invention is as follows:
Navigation SoC chip emulation of the present invention, checking and debug platform, at X86 main frame and ARM RealView Emulation Board platform (risc processor has been selected the most general arm processor of industry), cooperatively interact to descend can than to navigation neceiver, carry out emulation with the speed of 1:7, and completing the collection of Debugging message, designer can be take and interrupted controlling as base unit the operation of whole receiver.Whole platform can be worked on high efficient and reliable ground, considerably beyond the speed of HDL emulator RTL emulation, and supports embedded system real-time to analyze.Designer can control by gui interface the operation of navigation SoC witness plate software and hardware part, from database, retrieve Debugging message and real-time information, Debugging message and real-time data are analyzed the bottleneck of total system better, improve navigation SoC chip architecture, adjustment algorithm and Optimized code, realize and carry out sufficient preparation for later stage chip.
Accompanying drawing explanation
Fig. 1 is the typical flowchart of navigation SoC running software;
Fig. 2 is the system construction drawing of navigation SoC chip;
Fig. 3 is the Typical Disposition figure that adds the navigation SoC witness plate of intermediate frequency data playback mechanism in the embodiment of the present invention;
Fig. 4 is the structured flowchart that the present invention adds the SoC system verification plate of hardware Suspend Mode on the basis of Fig. 3;
Fig. 5 is the interrupt function processing flow chart that adds intermediate frequency data playback and Debugging message transmission in the embodiment of the present invention;
Fig. 6 is this corresponding MMU configuration and memory-mapped block diagram of embodiment of the present invention medium chain pin;
Fig. 7 is the truck schematic diagram of PC mainframe program overall framework and navigation SoC system verification plate in the embodiment of the present invention.
Embodiment
Below technical scheme of the present invention is further described, the following description, only for understanding the use of technical solution of the present invention, is not used in and limits scope of the present invention, and protection scope of the present invention is as the criterion with claims.
Below in conjunction with accompanying drawing, navigation SoC chip emulation of the present invention, checking and debug platform are described in further detail, below describe that all to take arm processor and ahb bus be example, if other risc processor or other bus form are please suitably revised.
Step 1, customizing navigation SoC chip checking plate.If Fig. 2 is the system construction drawing of navigation SoC chip, it directly obtains intermediate frequency data from radio-frequency front-end, these data enter hardware-accelerated IP and process, and risc processor or DSP complete the location of coordinate under the assistance of hardware accelerator, do not need the support of radio-frequency front-end in the present embodiment.On the SoC witness plate customizing, with arm processor and FPGA, with main frame, by UDP or usb protocol, communicate.
Step 2, adds the support of data readback.As shown in way 3, be the Typical Disposition figure that adds the navigation SoC witness plate of intermediate frequency data playback mechanism in the embodiment of the present invention.Exampleization fifo module in FPGA, because we can not carry out read-write operation to FIFO simultaneously, so the FIFO of synchronized model or asynchronous type all meets the demands.FIFO is corresponding to two addresses of bus, respectively:
L address 0 data write register, with the 32bit data width of current main flow, write;
The effective location register of l address 1 FIFO, returns to the quantity of spare word in current FIFO, and navigation interrupt routine need to this register obtains the information of FIFO, to determine next time should ask how many data to PC end;
Fifo module and navigation IP kernel are all realized in FPGA, and ARM can control it by bus.
Step 3, for navigation, IP adds the support of hardware Suspend Mode.Navigation IP provides with the form of RTL, different according to processor and FPGA type of attachment, and this navigation IP skin will possess different bus interface.The ARM RealView Emulation Board of take is example, and arm processor is externally AHB interface, so this navigation correlator IP must carry AHB interface.If otherwise connect, navigation IP must carry different interface logics.For example, if or1200 microprocessor, the wishbone interface of can arranging in pairs or groups.
Fig. 4 is the structured flowchart that the present invention adds the SoC system verification plate of hardware Suspend Mode on the basis of Fig. 3.Give RTL(Method at Register Transfer Level) code adds the support method of Suspend Mode is described as follows, in general the code of Hardware I P core is all to describe based on all synchro style, take Verilog as example, and each module generally comprises the synchronous sequential logic statement (seeing left hurdle) of the description of following style:
Amended code, as shown in right hurdle, adds `define SUSPEND_SUPPORT at top layer precompile file, and adds pd_n port (see figure 3) in all module ports that comprise synchronous sequential logic.So long as full synchronization can be comprehensive hardware module can be transformed in such a manner the module of supporting Suspend Mode.
Corresponding to Suspend Mode and operational mode, need to add two registers, the write mode of operation that just can switch Hardware I P of processor to these two registers.These two registers are controlled the pd_n port of IP kernel, and to register, suspend_reg writes, and pd_n is set to low level, and the IP that makes to navigate enters Suspend Mode; To register, wakeup_reg writes, and pd_n is set to high level, and navigation IP continues operation.
Step 4, for verifying this configuration timer resource.On plate, need to have three timer resource A, B, C, these three resources are all wanted to be utilized by arm processor, are described below:
L timer A: support the time delay of set time, such as the distributed time delay of delicate grade and Millisecond of the function of delayus () and delayms ();
L timer B: supporting the measurement of real-time, is below program runtime interval measurement code example, in order to measuring (timer is counted) working time of one section of code downwards:
T_start=timerB_cnt (); // initial
codeA?to_measure…
CodeA_duration=timerB_cnt () – t_start; // finish
CodeA_duration is exactly the time that codeA code moves, and its precision is relevant with the minimum resolution of timer B, and representative value is 1us.
L timer C: look-at-me timer, in the running software flow process of Fig. 1, needs look-at-me to trigger processor and enter Interrupt Service Routine;
Step 5, the planning of software flow on risc processor, focuses on the support of real-time performance evaluation especially.Program on arm processor is divided into navigation algorithm software and two parts of network communication software.Wherein in navigation algorithm software, comprise and interrupt processing function, our network communication software just operates in the hardware hang-up stage of interrupting processing function.If Fig. 5 is the interrupt function processing flow chart that adds intermediate frequency data playback and Debugging message transmission in the embodiment of the present invention.Network communication software completes the playback of intermediate frequency data and the statistics of Debugging message, and these codes belong to extracode for navigation algorithm software.If not special processing, these codes can disturb the content of Cache, and under worst condition, processor Cache can replace to completely along with the operation of extracode the content of extracode.When re-executing navigation algorithm software next time, processor have to again from external RAM, read in code and data, the situation of this and chip actual motion does not meet, and can disturb the assessment of real-time.
For real-time is correctly assessed, get rid of the uncertainty of Cache that extracode is introduced.In this sets of plan, need to configure by means of MMU page management mechanism the Cache support of different region of memorys.According to the difference of system board interconnection mode, MMU also has various configurations pattern.But basic ideas following (embodying at chained file):
L memory headroom is divided in MMU can Cache and can not two regions of Cache;
The stack space of l extracode is used more few better, or storehouse also point to can not Cache region;
L extracode is mapped to Non-Cacheable region, and corresponding to Fig. 5, networkProcess.cpp and dataCollect.cpp compilation unit are placed into the region of Non-Cacheable.
Its workflow, as Fig. 5, is described below:
Timer triggers the interrupt service routine that once navigates at set intervals, and the interrupt service routine first step is suspended correlator and Abort Timer exactly.It should be noted that now delay timer and real-time measurement timer are still in operation, the mechanism of delay function Delayus () and code measurement working time is still supported.In the present embodiment, can insert time interval measurement code in the various piece of interrupt function and master routine.
Step 6, the support that Debugging message is collected, does not disturb the assessment to former navigation SoC chip system real-time.Increase unified Debugging message data pool, concentrate on same compilation unit dataCollect.It quotes the data of other unit by the mode of extern, do not need to revise the code of other compilation unit, and the data of collecting will pass to main frame.
In order better in link script, memory headroom to be divided, make whole platform scheme there is versatility.The programming of this one end of RISC should be done following agreement.The content of processing network service (only the break in service at SoC witness plate occurs) as Fig. 5: networdProcess includes:
L navigation SoC witness plate is to PC request msg;
L PC navigation SoC chip board transmits navigation intermediate frequency data, with supported data playback;
L navigation SoC witness plate sends Debugging message to PC;
Being collected in dataCollect.cpp module of Debugging message content carried out, and in data pool, after populated content, networkProcess.cpp module can further be processed the content in data pool to send to main frame.Fig. 6 is this corresponding MMU configuration and memory-mapped block diagram of embodiment of the present invention medium chain pin, wherein the content of networkProcess.cpp module and dataCollect.cpp module is all the region of memory that is placed on Non-Cahceable, and navigation algorithm interrupt function (except network service part) and algorithm master routine are all Cacheable.
By the Cache switch of MMU Single Component Management memory pages.UDP/USB communication extracode drops to minimum to the interference of primal system, can not go to take Cache space, and the operation of whole system will be in close proximity to the ruuning situation of the inner SoC system of actual chips.
Step 6, the debugging enironment of PC main frame Erecting and improving, coordinates with navigation SoC chip checking plate.Fig. 7 is the truck schematic diagram of PC mainframe program overall framework and navigation SoC system verification plate in the embodiment of the present invention., simulating, verifying debug platform must provide abundant information to check for designer, so gui interface is essential.PC end debug platform is divided into four threads:
Thread one: UDP/USB thread, be responsible for transmitting navigation intermediate frequency data and receiving Debugging message to SoC system board;
Thread two: database thread, the Debugging message that navigation SoC chip checking plate is sent is stored in database, to facilitate commissioning staff to carry out search operaqtion and accessing operation to data;
Thread three: graphical interfaces thread, designer can watch the distribution of satellite, the state of receiver and real-time information, and commissioning staff can selectively check, filter information draw out waveform;
Thread four: debug system master control thread, be used for distributing the distribution of other three thread resources, and the arbitration of communicating by letter between them;
So far, navigation SoC chip emulation, checking and debug platform have been built.
Whole platform is to serve for the design of navigation neceiver chip, no matter is the checking of algorithm or the debugging of hardware, and designer can therefrom obtain abundant information and improve original design to revise.One spotlight of this platform is to have added the debugging to real-time, the setting that is configured to MMU from timer, and link the writing of script, all for accurately obtaining real-time, make great efforts, make every effort to reduce the interference of debug system to original system (SoC itself navigates) itself, can truly reflect operation result and the real-time information of SoC system in navigation chip, for next step post-simulation so that flow checking ready.
Utilize platform of the present invention the navigation intermediate frequency data being stored on PC main frame can be input in navigation IP in an orderly manner by Ethernet or USB interface, and commissioning staff can take interrupt carrying out with single-step(single step as least unit) or free-running(free-running operation) mode control the operation of whole system, and can from the feedback result of this system, obtain about software and hardware real-time, the information of the state of each passage of navigation neceiver and navigation calculation various aspects, all these information exchanges cross UDP or usb protocol is sent to PC from SoC mini system witness plate, be stored in subsequently background data base, so that designer retrieves from database by gui interface (graphic user interface), read, show these information.Navigation algorithm running software is on risc processor, and navigation IP realizes on FPGA, and whole platform operation result is as far as possible close to the operation result of SoC system in reality navigation chip.Simultaneously, by a kind of mechanism, allow the hardware-accelerated IP of navigation support hang-up/execution mechanism, the extracode that this debug platform adds all without impact, under these measures, can be assessed the real-time of software and hardware to the Cache of original system, interruption real-time more exactly.
To sum up, the SoC system verification plate that the hardware model compatibility of platform of the present invention is built by FPGA such as the risc processor of the main flows such as ARM, MIPS and Xilinx, Altera, with communicating by letter based on udp protocol or usb protocol of PC, design and commissioning staff can carry out the control of interrupt levels and the collection of Debugging message to the operation of navigation SoC system by PC main frame, the real-time of precise evaluation software and hardware, compatible multiple navigational system, comprising GPS, Galileo, the Big Dipper and GLONASS system, is the strong instrument in navigation chip design checking field.
The foregoing is only preferred embodiment of the present invention, not technical scope of the present invention is done to any restriction, all any modifications of making within the spirit and principles in the present invention, are equal to replacement and improvement etc., within all should being included in protection scope of the present invention.
Claims (9)
1. navigation SoC chip emulation, checking and a debug platform, is characterized in that comprising: PC main frame and SoC system verification plate, and the communication between them is undertaken by UDP or usb protocol; Described PC main frame completes intermediate frequency data to the importing of SoC system verification plate by UDP or usb protocol and handshake mechanism, and SoC system verification plate gathers Debugging message and also returns to PC main frame; Wherein:
On described SoC system verification plate, comprise risc processor and fpga chip, described fpga chip and risc processor communicate with the interface of bus mode or short time delay, and navigation IP provides with RTL form, comprehensively realizes on FPGA; On FPGA hardware, realize the navigation IP with Suspend Mode, on risc processor, move navigation algorithm, under navigation IP auxiliary, complete positioning calculation function;
Described risc processor realizes memory-mapped by MMU memory management unit and Cache manages; The peripheral hardware resource that described risc processor can be controlled at least will have ethernet controller or USB controller, and is connected with PC main frame; All C/C++ programs of navigating all operate on risc processor, are divided into master routine and interrupt service routine in main body; Interrupt service routine is responsible for carrying out alternately with navigation IP, and master routine utilizes the information that interrupt service routine returns to calculate coordinate, these two program flows satnav of having worked in coordination.
2. navigation SoC chip emulation according to claim 1, checking and debug platform, it is characterized in that: described risc processor is supported interrupt mechanism, and there are three above timer resources, one of them timer completes the time delay of set time, another timer completes and interrupts setting out, the 3rd timer completes the measurement of working time of a plurality of program segment, and these timer resource distributions are on FPGA, or inner in risc chip.
3. navigation SoC chip emulation according to claim 1, checking and debug platform, it is characterized in that: described risc processor can conduct interviews and read and write the hardware-accelerated unit that navigates, FPGA is connected by sheet external bus or PCI-E bus with risc processor.
4. navigation SoC chip emulation according to claim 1, checking and debug platform, it is characterized in that: described PC main frame is deposited navigation intermediate frequency data, PC main frame is shaken hands and is communicated by letter by UDP or usb protocol with SoC verification system, and PC main frame is with network interface or USB interface.
5. navigation SoC chip emulation according to claim 1, checking and debug platform, it is characterized in that: in the RTL code of described navigation IP, add the support to Suspend Mode, the mode enabling with clk_enable clock realizes, the mode that ppu can be read and write by register changes operation/suspended state of navigation IP, it is suspended, then continue to carry out.
6. navigation SoC chip emulation according to claim 1, checking and debug platform, it is characterized in that: the interrupt service routine moving on described risc processor is divided into the hardware operation phase and hardware is hung up the stage, hardware is hung up stage PC main frame and to FPGA, is imported in batches navigation data by Ethernet/USB interface into; On FPGA, there is corresponding FIFO to store these data; The collection of Debugging message and to return be also to complete in this stage.
7. navigation SoC chip emulation according to claim 6, checking and debug platform, it is characterized in that: the hardware at interrupt service routine is hung up the stage, with controlled pattern, navigation intermediate frequency data is sent to the FIFO in FPGA, FIFO is encapsulated as the peripheral hardware of processor place bus, be mapped to one section of region in internal memory, processor in the mode of memory read-write to FIFO data writing in batches, for Hardware I P module provides data, the residue of systems inspection intermediate frequency data FIFO is initiated request of data to PC end in each interrupt function, and PC end is followed handshake mechanism navigation intermediate frequency data is returned to SoC system verification plate, the Debugging message collection procedure of risc processor end is by receiver state, Debugging message, calculation result and real time analysis information are sent to PC end and further analyze, these information will be filled whole Ethernet data bag with the form of parcel, then PC host side completes fractionation and the parsing of these packets again, insert subsequently the database on backstage, gui interface is according to the retrieval of designer's operation database, take out these information and represent these information with the form of waveform or form, carry out the debugging that time precision is interrupt levels, the extracode of these UDP/USB communications is by the setting of link script and memory management unit MMU, be positioned over the region of Non-Cacheable.
8. navigation SoC chip emulation according to claim 1, checking and debug platform, it is characterized in that: described risc processor is the operation real-time quantification to software and hardware by timer, the working time of accurate Survey Software code, the debug information collection that this platform is introduced and intermediate frequency data playback extracode, by memory-mapped and Cache administrative mechanism, substantially noiseless to navigation original program, real time analysis result is accurate.
9. navigation SoC chip emulation according to claim 1, checking and debug platform, it is characterized in that: described PC main frame is divided into four threads, respectively GUI graphical interfaces thread, debug system master control thread, database thread and UDP/USB communication thread, wherein: master control thread is responsible between other three threads the distribution of resource, the arbitration of communication; UDP/USB communication thread is responsible for and SoC witness plate communicates; The Debugging message that database thread is come to the communications storage of classifying, and support user to retrieve these information, database thread is also responsible for calling in of intermediate frequency data data source; Graphical interfaces allows designer check Debugging message and real-time information, drawing waveforms and the operation of controlling receiver in mode intuitively.
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