CN106299015B - 一种采用低维量子点倍增层的半导体雪崩光电探测器 - Google Patents
一种采用低维量子点倍增层的半导体雪崩光电探测器 Download PDFInfo
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Abstract
本发明涉及一种采用低维量子点倍增层的半导体雪崩光电探测器，在半导体雪崩光电探测器的倍增层中包含有若干层量子点层，所述量子点层具有比倍增层更窄的禁带宽度，且与倍增层材料形成I型能带结构。本发明增益系数显著提升、过剩噪声得到抑制，可广泛应用于增强Si‑Ge、GaAs‑InAs、InP‑InGaAs、InAlAs‑InGaAs、GaAs‑AlSb等不同波段的雪崩探测器性能，提升高速光通讯、单光子计数、激光雷达、量子信息等雪崩探测器系统的应用水平。
Description
技术领域
本发明属于半导体雪崩光电探测器领域，特别涉及一种采用低维量子点倍增层的半导体雪崩光电探测器。
背景技术
半导体雪崩光电探测器(Avalanche Photodiode，APD)是一种利用载流子碰撞离化倍增效应实现内部光电流放大的高灵敏型光探测器。其基本结构是一个工作于大反向偏压下的半导体光电二极管，通过利用耗尽区内光生载流子的碰撞离化倍增效应实现器件内光电流增益。可提供比PIN型探测器高5dB甚至以上的光电流增益。APD还具有更低的结电容，因此能同时满足高速响应和高探测灵敏度。根据所用半导体材料的不同，APD可以覆盖不同的光探测波段。如200-1000nm波段的Si APD，0.9-1.7μm波段的Ge/Si、InP/InGaAsP、InP/InGaAs及InAlAs/InGaAs APD，1.8-2.5μm波段的InP/InGaAs/GaAsSb二类超晶格APD、GaSb/InAs超晶格APD，2-3.3μm波段的InAs APD和4μm波段的HgCdTe APD等。根据工作电压的不同，可以将APD工作模式分为线性模式盖革模式。在线性模式下，工作电压小于击穿电压。通常可以实现1-100之间的增益系数。根据工作波长的不同，可以被应用于自由空间光通信、光纤通讯、激光测距、医疗检测、气体含量分析等等领域。而在盖革模式下，工作电压大于击穿电压，可实现>105的光电流增益，实现对单光子的灵敏探测。盖革模式APD器件具有结构简单可靠、可室温工作无需制冷、低成本和易于系统集成等突出优势。此外，APD器件具有比传统PIN更小的结电容和更高的增益带宽积，盖革APD在传统光纤通讯和航天三维激光雷达成像、单光子计数、量子密钥分发等前沿光子学领域均已经获得了重要应用。以InP基InGaAs、InGaAsP APD为例，其峰值探测波长分别位于1.55μm和1.06μm附近，分别被应用于光通信和激光雷达成像领域。尽管APD器件的研究和应用已经取得了较大发展，但是，目前其器件性能已经达到瓶颈。其线性模式下的增益带宽积、增益系数、过剩噪声，盖革模式下的光探测效率、暗计数等性能均难以再通过常规的材料和器件结构优化进一步提升，因此也对实际应用产生了较大限制。根本原因在于InP、InAlAs、InAs等倍增层材料的载流子碰撞离化几率难以进一步提升，且碰撞离化发生的位置不确定性高，进而限制了APD的增益系数和过剩噪声性能的提升。
为了突破APD器件的性能瓶颈，人们相继探索并提出了一系列方法，包括利用薄倍增层的“死空间”效应降低过剩噪声因子(Applied Physics Letters,82(13),2175-2177(2003))，利用渐变禁带宽度倍增层的低碰撞离化阈值能量增强增益(IEEE PhotonicsTechnology Letters14(12),1722-1724(2002))，利用晶片键合技术键合晶格失配的高效倍增材料提高雪崩特性(《光电器件》，31卷第5期，702-758(2010))，以及利用多级pin级联倍增增强碰撞离化系数(美国专利Voxtel,Inc.US 7432537B1)等。以上探索均对APD性能有一定提升，并分别显现出了它们的应用价值。然而也都分别存在一定的问题，如材料制备工艺复杂、暗电流大、器件可靠性低等。进一步寻求新的提升雪崩几率、降低过剩噪声的新型材料或器件结构仍然有重要意义。半导体量子点是一类载流子三维受限的量子结构，其具有许多优异的物理特性，如量子结构内的能级分立，存在声子瓶颈效应和增强的库仑相互作用，且其内部电声子散射能量弛豫较体材料大大降低。因此量子点在光电能量转换方面具有重要应用价值。有关量子点中雪崩效应的研究始于2004年(Physical Review Letters92(18)186601(2004))，但该类研究报道所述及的“雪崩”本质上是指高能光子辐射半导体材料所产生的“多激子激发”效应，研究其用于提升太阳能电池光电效率。并非是指电子或空穴在量子点中的碰撞离化效应。
发明内容
本发明所要解决的技术问题是提供一种采用低维量子点倍增层的半导体雪崩光电探测器，该半导体雪崩光电探测器增益系数显著提升、过剩噪声得到抑制，可广泛应用于增强Si-Ge、GaAs-InAs、InP-InGaAs、InAlAs-InGaAs、GaAs-AlSb等不同波段的雪崩探测器性能，提升高速光通讯、单光子计数、激光雷达、量子信息等雪崩探测器系统的应用水平。
本发明的一种采用低维量子点倍增层的半导体雪崩光电探测器，在半导体雪崩光电探测器的倍增层中包含有若干层量子点层，所述量子点层具有比倍增层更窄的禁带宽度，且与倍增层材料形成I型能带结构。
所述半导体雪崩光电探测器的结构如下：
倍增层材料碰撞离化系数比大于1(如Si、GaAs、InAlAs等)，采用电子倍增架构，P+-P--P+-P--N+的整体掺杂构型：由下至上器件依次包含衬底层、P+缓冲层、P+接触层、包含有量子点层的P-倍增层、P+电场控制层、P-能带过渡层、P-光吸收层、P+包覆层和P+接触层；
或者倍增层材料碰撞离化系数比小于1(如InP等)，采用空穴倍增架构，P+-N--N+-N--N+的整体掺杂构型：由下至上器件依次包含衬底层、N+缓冲层、N+接触层、N+包覆层、N-光吸收层、N-能带过渡层、N+电场控制层、包含有量子点层的N-倍增层和N+接触层。
采用电子倍增架构时，量子点与倍增层材料的导带带阶大于价带带阶；且导带带阶与价带带阶之差越大器件性能增强效果越好；
采用空穴倍增架构时，量子点与倍增层材料的价带带阶大于导带带阶；且导带带阶与价带带阶之差越大器件性能增强效果越好。
所述量子点层采用比倍增层材料晶格常数更大的材料制备。
所述量子点层为多层时，相邻量子点层之间的间隔层厚度大于量子点之间的受限激子波函数相互作用距离(一般应大于20nm)，形成足够高的势垒，相邻量子点层之间不耦合。
所述半导体雪崩光电探测器通过台面结结构制备或者通过平面结结构制备。
所述半导体雪崩光电探测器为Si-Ge、GaAs-InAs、InP-InGaAs、InAlAs-InGaAs、GaAs-GaSb或GaAs-AlSb雪崩光电探测器。
本发明是利用量子点的低碰撞离化阈值特性，同时利用量子点内的声子瓶颈效应和量子点与势垒层之间的带阶，在量子点层内实现高效的载流子定域碰撞离化雪崩倍增，实现提升APD的增益，同时降低过剩噪声。具体包括：
(1)材料的设计思路：
半导体量子点内由于载流子波函数在三维空间上受限，因此内部呈现量子化的分立能级。而由于载流子的能级分立，因此由跃迁定则可知，量子点内的跃迁能量也呈现量子化。由于声子能量通常很小，因而声子与晶格原子散射发射或者吸收一个声子的动量能量守恒容易通过材料内连续能级的跃迁实现匹配。而在量子点内，由于量子化的跃迁能量通常大于一个声子的能量，因此无法实现匹配，进而导致声子散射被显著抑制。这意味着在量子点内输运的载流子的动能不再容易通过声子散射而损失，因此更容易达到碰撞离化阈值能量，进而发生碰撞离化，产生雪崩倍增。
另一方面，半导体量子点的生长通常是通过在晶格更小的异质材料表面通过先层状-后岛状(S-K)的生长模式实现。由于量子点材料的晶格通常大于基质材料，因此其禁带宽度也小于基质材料。故量子点与基质材料之间通常存在大的带阶，且导带和价带的带阶通常不同。而从APD器件的角度出发，由于倍增层内存在高电场，因此通常要求倍增层材料具有较大的禁带宽度(较小的晶格常数)，以降低由于隧穿导致的暗电流。而由于碰撞离化阈值能量与禁带宽度成正比，因此同时又要求倍增层材料具有较小的禁带宽度(较大的晶格常数)，以降低碰撞离化阈值能量，提高雪崩增益。在相互矛盾的要求下，作为平衡考虑，通常是选取一个具有中等禁带宽度的材料作为倍增层。考虑到上述情况，将窄禁带的量子点生长在宽禁带的倍增层材料内，则一方面可以继续保持低的倍增层隧穿暗电流，另一方面又可以同时利用量子点的窄带隙和低碰撞离化阈值特性大大提升雪崩增益。此外，插入量子点的另一大利处在于，量子点和倍增层基质间存在大的带阶，因此载流子将在从倍增区基质进入量子点的界面处获得能量等于带阶差的额外动能，进而进一步提升雪崩增益。
由于量子点倍增结构中，主要的载流子碰撞离化过程发生在极薄的量子点层，因此雪崩倍增在空间上的确定性大大提升，进而显著降低了由于碰撞离化在雪崩层中位置不确定所产生的过剩噪声。进一步提升APD性能。
量子点APD的基本结构仍然基于传统的高性能吸收层倍增层分离架构。在宽禁带的倍增区材料中，根据材料的具体晶格结构和厚度，插入相匹配的若干层窄禁带量子点。间隔层厚度需要大于相邻量子点层的激子波函数的耦合临界厚度。一般应大于20nm。这是由于若间隔层厚度太薄，倍增层内的电压会更多的降低到量子点层，进而导致器件暗电流明显增加。
本发明的量子点倍增结构，广泛适用于增强不同材料体系的雪崩探测器性能，进而可以被用于不同探测波段。如Si或者SiGe的APD器件可以在Si倍增层中插入Ge量子点层；GaAs的同质结APD器件则可以在GaAs倍增层中插入InAs或GaSb量子点层；InP/InGaAs或InAlAs/InGaAs的APD器件可以在InP倍增层中插入InAs量子点层；GaSb/AlSb的APD器件可以在AlSb倍增层中插入InSb量子点层，等等。根据倍增区基质材料的电子空穴碰撞离化系数，对于电子碰撞离化系数大于空穴的，选择与倍增层基质具有更大导带带阶的量子点材料；而对于空穴碰撞离化系数大于电子的，则选择与倍增层基质具有更大价带带阶的量子点材料；通过选择合适的量子点材料，可以最大化的发挥量子点带来的雪崩增益增加和过剩噪声系数降低的优势。
(2)材料的生长结构：
基于以上设计思路，以InGaAs/InAlAs吸收倍增分离型APD为例，具体给出一种采用量子点倍增区的APD器件结构。器件基本结构如图1所示。由于InAlAs材料的电子比空穴具有更高的碰撞离化系数，因此采用电子作为倍增载流子，器件使用P+-P--P+-P--N+的整体掺杂构型。在半绝缘或者N型导电InP衬底上，首先外延N型重掺杂(N+)的InAlAs缓冲层，同时该缓冲层作为N型金属接触层。然后外延P型低掺杂浓度(P-)或者不掺杂的量子点倍增区，包含一定厚度的InAlAs基质和间隔厚度大于20nm的若干层InAs量子点。InAs量子点生长过程中不掺杂。接着生长一定厚度的中高掺杂(P)型InAlAs电荷层，以控制电场的分布，使得强电场分布在倍增区，而吸收层仅存在低电场。最后生长P型低掺杂浓度(P-)或者不掺杂的InGaAs光吸收层区和P型重掺杂(P+)的InAlAs P区电极接触层。
本发明所提出的量子点倍增APD结构，是一种基于传统意义上强电场下载流子雪崩碰撞离化倍增概念的探测器器件结构，可以充分利用半导体量子点的量子效应优势，同时提升雪崩增益系数和降低过剩噪声因子。这种量子点倍增结构适用于多种APD材料体系，对于提升APD的器件性能将十分有利。
有益效果
(1)本发明雪崩区内声子散射被显著抑制，载流子的动能损失更少，因此更容易达到碰撞离化阈值能量，产生雪崩倍增。
(2)本发明在保持低倍增层隧穿暗电流的前提下，利用量子点的窄带隙和低碰撞离化阈值特性大大提升雪崩增益。
(3)本发明利用倍增层基质和量子点的导带或者价带带阶差，为电子或空穴提供额外的动能，提高雪崩增益。
(4)本发明碰撞离化在空间上发生的确定性大大提升，显著降低雪崩过剩噪声系数。
(5)本发明量子点和倍增区基质的带阶可以由量子点的种类控制，且可以增加插入层数产生级联倍增，便于实现最优化的雪崩性能增强。
(6)本发明的APD结构可广泛应用于增强Si-Ge、GaAs-InAs、InP-InGaAs、InAlAs-InGaAs、GaAs-AlSb等不同波段的雪崩探测器性能，提升高速光通讯、单光子计数、激光雷达、量子信息等雪崩探测器系统的应用水平。
附图说明
图1为本发明以电子倍增APD器件为例时，P+-P--P+-P--N+型量子点倍增APD器件结构示意图；
图2为以GaAs/InAs为例的量子点APD结构(左)及无量子点的对照APD器件结构(右)示意图；
图3为量子点APD与对照APD的雪崩增益的实际测量结果；其中黑色实线为量子点APD的光电流和暗电流曲线，灰色虚线为对照APD的光电流和暗电流曲线，黑色圆点为量子点APD的增益曲线，灰色菱形框为对照APD的增益曲线；
图4为量子点APD与对照APD的过剩噪声系数的实际测量结果；其中方形实心点为量子点APD的过剩噪声数据，圆形实心点为对照APD的过剩噪声数据；虚线为理论计算的不同碰撞离化系数比(k)下的过剩噪声曲线。
具体实施方式
下面结合具体实施例，进一步阐述本发明。应理解，这些实施例仅用于说明本发明而不用于限制本发明的范围。此外应理解，在阅读了本发明讲授的内容之后，本领域技术人员可以对本发明作各种改动或修改，这些等价形式同样落于本申请所附权利要求书所限定的范围。
实施例1
本实施例目的是用InAs量子点作为倍增材料提升GaAs APD的增益系数降低其过剩噪声。器件为台面结结构，采用吸收倍增分离型基本架构，采用电子作为倍增载流子，采用P+-P--P+-P--N+的掺杂结构，器件材料使用分子束外延系统生长获得。通过与无量子点倍增的对照器件对比，验证本发明的可行性。量子点倍增与无量子点倍增APD的具体器件结构分别如图2左右所示。两者除倍增区外其余器件结构参数完全相同。其结构由下至上依次包含以下材料：
①半绝缘(S.I.)GaAs(001)衬底。厚度350微米，电阻率ρ≥1MΩ·cm。
②N型重掺杂(N+)GaAs接触层。厚度500nm，掺杂浓度4×1018cm-3。
③电子倍增层。量子点APD的倍增层包括5层不掺杂的InAs量子点，每层量子点沉积量为2.25个原子层。相邻量子点层之间为厚度50nm的P-掺杂GaAs间隔层，掺杂浓度为8×1015cm-3。总共6层间隔层，总厚度300nm。对照APD的倍增层包括厚度300nm的P-掺杂GaAs层，掺杂浓度为8×1015cm-3。
④P型中等掺杂GaAs电荷层。厚度70nm，掺杂浓度为6×1017cm-3。
⑤P-掺杂的GaAs光吸收层，厚度1500nm，掺杂浓度为8×1015cm-3。
⑥P型重掺杂(P+)GaAs接触层。厚度100nm，掺杂浓度为6×1018cm-3。
器件材料的分子束外延生长过程如下：
(1)通过预备生长确定在GaAs(001)衬底上生长沉积量为2.25原子层的InAs量子点和掺杂浓度分别为N型4×1018cm-3，P型6×1017、6×1018、8×1015cm-3的GaAs单层材料的衬底温度、束源炉温度等生长条件；
(2)在对2片Epi-Ready GaAs(001)衬底(半绝缘)进行600℃脱附氧化物处理后，分别用于生长量子点APD器件和对照器件。量子点APD器件依次生长材料②至材料⑥，其中材料③的结构采用量子点倍增结构，每层的厚度、沉积量及掺杂浓度均如上所述。对照APD器件依生长材料②至材料⑥，其中材料③的结构采用无量子点的GaAs体材料，厚度及掺杂浓度均如上所述。
(3)生长完毕后结束生长，在As2保护气氛下降低衬底温度和源炉温度至200℃以下，取出外延材料。
台面型APD器件的制备工艺过程如下：
(1)旋涂光刻胶，通过光刻工艺对材料进行图形曝光、显影，并进行化学溶液湿法腐蚀或者干法离子刻蚀，去除光刻胶，制备探测器台面。
(2)ICP-CVD生长SiNx钝化膜300nm。
(3)再次进行涂胶、光刻套刻、显影，获得电极图形，并进行CF4反应离子刻蚀，去除台面上和N型接触层表面电极区域的SiNx薄膜。
(4)第三次进行涂胶、光刻套刻、显影，获得电极图形，并利用电子束蒸发蒸镀Ti/Pt/Au金属材料，厚度为20nm/20nm/300nm。并同通过剥离工艺，去除光刻胶，获得完整的器件结构。
对所获得的InAs/GaAs量子点APD器件和对照APD器件分别进行直流暗电流、光电流测试，获得器件的增益系数，实际测量结果如图3所示。可以看出，量子点APD器件增益为100左右，而对照APD器件的增益仅为11左右，增益增强了约10倍。图4为量子点APD和对照APD的实际过剩噪声系数测量结果，可以看出，量子点APD的过剩噪声系数下降至接近k＝0的理想值，比对照APD的过剩噪声有显著降低。图3和4的测量结果，充分证实了本发明器件结构在增强雪崩探测器增益和降低过剩噪声方面的可行性。
Claims (5)
1.一种采用低维量子点倍增层的半导体雪崩光电探测器，其特征在于：在半导体雪崩光电探测器的倍增层中包含有若干层量子点层，所述量子点层具有比倍增层更窄的禁带宽度，且与倍增层材料形成I型能带结构；其中，采用电子倍增架构时，量子点与倍增层材料的导带带阶大于价带带阶；采用空穴倍增架构时，量子点与倍增层材料的价带带阶大于导带带阶；量子点层为多层时，相邻量子点层之间的间隔层厚度大于量子点之间的受限激子波函数相互作用距离。
2.根据权利要求1所述的一种采用低维量子点倍增层的半导体雪崩光电探测器，其特征在于：所述半导体雪崩光电探测器的结构如下：
倍增层材料碰撞离化系数比大于1，采用电子倍增架构，P+-P--P+-P--N+的整体掺杂构型：由下至上器件依次包含衬底层、P+缓冲层、P+接触层、包含有量子点层的P-倍增层、P+电场控制层、P-能带过渡层、P-光吸收层、P+包覆层和P+接触层；
或者倍增层材料碰撞离化系数比小于1，采用空穴倍增架构，P+-N--N+-N--N+的整体掺杂构型：由下至上器件依次包含衬底层、N+缓冲层、N+接触层、N+包覆层、N-光吸收层、N-能带过渡层、N+电场控制层、包含有量子点层的N-倍增层和N+接触层。
3.根据权利要求1所述的一种采用低维量子点倍增层的半导体雪崩光电探测器，其特征在于：所述量子点层采用比倍增层材料晶格常数更大的材料制备。
4.根据权利要求1所述的一种采用低维量子点倍增层的半导体雪崩光电探测器，其特征在于：所述半导体雪崩光电探测器通过台面结结构制备或者通过平面结结构制备。
5.根据权利要求1所述的一种采用低维量子点倍增层的半导体雪崩光电探测器，其特征在于：所述半导体雪崩光电探测器为Si-Ge、GaAs-InAs、InP-InGaAs、InAlAs-InGaAs、GaAs-GaSb或GaAs-AlSb雪崩光电探测器。
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