CN106298681A - A kind of MOSFET element and preparation method thereof - Google Patents
A kind of MOSFET element and preparation method thereof Download PDFInfo
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- CN106298681A CN106298681A CN201510295716.3A CN201510295716A CN106298681A CN 106298681 A CN106298681 A CN 106298681A CN 201510295716 A CN201510295716 A CN 201510295716A CN 106298681 A CN106298681 A CN 106298681A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
Abstract
The invention discloses a kind of MOSFET element and preparation method thereof, including: on the substrate of the first conduction type, sequentially form the epitaxial layer of the first conduction type, gate oxide and polysilicon layer；Etch described polysilicon layer and form the first polysilicon layer, the second polysilicon layer and the 3rd polysilicon layer, and the first time carrying out the second conductive type ion injects, and forms body district in described epitaxial layer；The second time carrying out the second conductive type ion is injected and carries out high annealing for the first time, forms heavy doping body district in described body district and forms spaced second conductive type ion doped region in described second polysilicon layer；The first time carrying out the first conductive type ion injects and carries out second time high annealing, forms source region and form the first conductive type ion doped region being arranged alternately with described second conductive type ion doped region in described second polysilicon layer in described body district；Use the method, it is to avoid the puncturing of gate oxide.
Description
Technical field
The present invention relates to semiconductor chip fabrication process technical field, more particularly relate to a kind of MOSFET
Device and preparation method thereof.
Background technology
Along with MOSFET (Metal-Oxide-Semiconductor Field-Effect Fransistor, metal oxygen
Compound semiconductor field) development of device process technology, the gate oxide of MOSFET element exists
Between about 100nm or tens nm, to ESD (Electro Static Discharge, static discharge)
The injury of phenomenon becomes more sensitive.The input resistance of ESD itself is the highest, and between gate-source
Electric capacity is the least, so ESD device is highly prone to external electromagnetic field or the sensing of electrostatic and charged,
It is difficult to, because of the occasion stronger at electrostatic, electric charge of releasing again, easily causes electrostatic breakdown, thus cause the thin of grid
Oxide layer punctures, and forms pin hole so that form open circuit between grid and source class.
Therefore, there is ESD and puncture pressure relatively low in MOSFET element of the prior art, is easily caused grid
The problem that pole oxide layer punctures.
Summary of the invention
The embodiment of the present invention provides a kind of MOSFET element and preparation method thereof, in order to solve prior art
There is ESD and puncture pressure relatively low in middle MOSFET element, be easily caused that grid oxic horizon punctures asks
Topic.
The embodiment of the present invention provides the making of a kind of metal oxide semiconductor field effect tube MOSFET element
Method, including:
The substrate of the first conduction type sequentially forms the epitaxial layer of the first conduction type, gate oxide and many
Crystal silicon layer；
Etch described polysilicon layer and form the first polysilicon layer, the second polysilicon layer and the 3rd polysilicon layer, and
The first time carrying out the second conductive type ion injects, and forms body district in described epitaxial layer；
The second time carrying out the second conductive type ion is injected and carries out high annealing for the first time, in described body district
Interior formation heavy doping body district and formed in described second polysilicon layer spaced second conduction type from
Sub-doped region, described second conductive type ion doped region includes the second conductive type ion heavily doped region and position
The second conductive type ion around described second conductive type ion heavily doped region is lightly doped district；
The first time carrying out the first conductive type ion injects and carries out second time high annealing, in described body district
Interior formation source region and formation and described second conductive type ion doped region friendship in described second polysilicon layer
For the first conductive type ion doped region arranged, described first conductive type ion doped region includes that first leads
Electricity types of ion heavily doped region and the first conduction being positioned at around described first conductive type ion heavily doped region
Types of ion is lightly doped district；
Described first polysilicon layer is formed source electrode, described 3rd polysilicon layer forms grid, in institute
State substrate back and form drain electrode.
It is preferred that the described polysilicon layer of described etching forms the first polysilicon layer, the second polysilicon layer and the 3rd
Polysilicon layer, and carry out the first time injection of the second conductive type ion, in described epitaxial layer, form body district,
Particularly as follows:
Described polysilicon layer arranges photoresist, the first photoresist mask that etching is formed, described first light
Photoresist mask covers at described first polysilicon layer, described second polysilicon layer and described 3rd polysilicon layer
On；
After described body district is formed, remove described first photoresist mask.
Carry out the second time of the second conductive type ion described in it is preferred that to inject and carry out high temperature for the first time and move back
Fire, particularly as follows:
At described gate oxide, described first polysilicon layer, described second polysilicon layer and described 3rd polycrystalline
Silicon layer arranges photoresist, and etching forms the second photoresist mask, and described second photoresist mask covers described the
One polysilicon layer, described second polysilicon layer and the surface of described 3rd polysilicon layer and side, and described
In the first fragmentation state on second polysilicon layer；
After described second time is injected, remove described second photoresist mask.
Carrying out first time of the first conductive type ion described in it is preferred that injects and carries out second time high temperature and move back
Fire, particularly as follows:
At described gate oxide, described first polysilicon layer, described second polysilicon layer and described 3rd polycrystalline
Silicon layer arranges photoresist, and etching forms the 3rd photoresist mask, and described 3rd photoresist mask covers described heavy
Doped body region, and in the second fragmentation state on described second polysilicon layer, each point of described second segmentation
The length of section is more than the second conductive type ion doped region of corresponding part；
After described third time is injected, remove described 3rd photoresist mask.
It is preferred that the distance between the photoresist mask of described first fragmentation state and described second fragmentation state
The distance of photoresist mask equal.
It is preferred that the temperature of described first time high annealing is higher than the temperature of described second time high annealing.
The embodiment of the present invention also provides for a kind of metal oxide semiconductor field effect tube MOSFET element, bag
Include:
The first conductive type epitaxial layer being arranged on substrate；
It is arranged on described first conductive type epitaxial layer Nei Ti district and the heavy doping formed in described body district
Body district and source region；
It is arranged on the first polysilicon layer on described first conductive type epitaxial layer, the second polysilicon layer and the 3rd
Polysilicon layer；
The second conductive type ion doped region it is arranged at intervals with and with described second in described second polysilicon layer
The first conductive type ion doped region that conductive type ion doped region is arranged alternately；
Described second conductive type ion doped region includes the second conductive type ion heavily doped region and is positioned at institute
The second conductive type ion stated around the second conductive type ion heavily doped region is lightly doped district；
Described first conductive type ion doped region includes the first conductive type ion heavily doped region and is positioned at institute
The first conductive type ion stated around the first conductive type ion heavily doped region is lightly doped district；
It is provided with source electrode on described first polysilicon layer, described 3rd polysilicon layer is provided with grid, described
Substrate back is provided with drain electrode.
It is preferred that the width of described second conductive type ion doped region and described first conductive type ion are mixed
The width in miscellaneous district is equal.
It is preferred that the width of described second conductive type ion heavily doped region and described first conduction type from
The width of sub-heavily doped region is equal.
In the embodiment of the present invention, the substrate of the first conduction type sequentially forms the extension of the first conduction type
Layer, gate oxide and polysilicon layer；Etch described polysilicon layer and form the first polysilicon layer, the second polysilicon
Layer and the 3rd polysilicon layer, and carry out the first time injection of the second conductive type ion, in described epitaxial layer
Form body district；The second time carrying out the second conductive type ion is injected and carries out high annealing for the first time, in institute
Shu Ti district forms heavy doping body district and forms spaced second conductive-type in described second polysilicon layer
Type ion doped region, described second conductive type ion doped region includes the second conductive type ion heavily doped region
And the second conductive type ion being positioned at around described second conductive type ion heavily doped region is lightly doped district；Enter
The first time of row the first conductive type ion injects and carries out second time high annealing, is formed in described body district
Source region and being formed in described second polysilicon layer is arranged alternately with described second conductive type ion doped region
The first conductive type ion doped region, described first conductive type ion doped region includes the first conduction type
Ion heavily doped region and the first conduction type of being positioned at around described first conductive type ion heavily doped region from
Son is lightly doped district；Described first polysilicon layer is formed source electrode, described 3rd polysilicon layer is formed grid
Pole, forms drain electrode at described substrate back.In said method, by traditional handicraft between grid and source class
ESD protection structure replaces with the back-to-back zener diode of array, and the voltage of zener diode is higher than grid
Pole running voltage, when MOSFET element works, always has part Zener diode to be in reverse-biased,
Do not interfere with the current potential on grid.When grid and source electrode produce instantaneous pressure because of electrostatic, Zener diode two
Pole pipe will puncture, and forms conductive channel static electricity discharge electric current, grid potential is clamped at ratio relatively low
Voltage (relative to the breakdown voltage of gate oxide), it is to avoid puncturing of gate oxide.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, institute in embodiment being described below
The accompanying drawing used is needed to briefly introduce, it should be apparent that, the accompanying drawing in describing below is only the present invention's
Some embodiments, from the point of view of those of ordinary skill in the art, in the premise not paying creative work
Under, it is also possible to other accompanying drawing is obtained according to these accompanying drawings.
Fig. 1 is the process chart of the manufacture method of a kind of MOSFET element disclosed in the embodiment of the present invention；
Fig. 2 a is to make epitaxial layer, gate oxide and the knot of polysilicon layer in the embodiment of the present invention on substrate
Structure schematic diagram；
Fig. 2 b is the structural representation forming photoresist mask in the embodiment of the present invention on the polysilicon layer；
Fig. 2 c is the structural representation of etches polycrystalline silicon layer in the embodiment of the present invention；
Fig. 2 d is the structural representation of ion implanting for the first time in the embodiment of the present invention；
Fig. 2 e is the structural representation of second time ion implanting in the embodiment of the present invention；
Fig. 2 f is the structural representation in the embodiment of the present invention after first time high annealing；
Fig. 2 g is the structural representation of third time ion implanting in the embodiment of the present invention；
Fig. 2 h is the structural representation in the embodiment of the present invention after second time high annealing；
Fig. 2 i is to make dielectric layer and the structural representation of metal level in the embodiment of the present invention；
Fig. 3 is the ESD protection structural representation that in the embodiment of the present invention, the second polysilicon layer makes.
Detailed description of the invention
In the embodiment of the present invention, the substrate of the first conduction type sequentially forms the extension of the first conduction type
Layer, gate oxide and polysilicon layer；Etch described polysilicon layer and form the first polysilicon layer, the second polysilicon
Layer and the 3rd polysilicon layer, and carry out the first time injection of the second conductive type ion, in described epitaxial layer
Form body district；The second time carrying out the second conductive type ion is injected and carries out high annealing for the first time, in institute
Shu Ti district forms heavy doping body district and forms spaced second conductive-type in described second polysilicon layer
Type ion doped region, described second conductive type ion doped region includes the second conductive type ion heavily doped region
And the second conductive type ion being positioned at around described second conductive type ion heavily doped region is lightly doped district；Enter
The first time of row the first conductive type ion injects and carries out second time high annealing, is formed in described body district
Source region and being formed in described second polysilicon layer is arranged alternately with described second conductive type ion doped region
The first conductive type ion doped region, described first conductive type ion doped region includes the first conduction type
Ion heavily doped region and the first conduction type of being positioned at around described first conductive type ion heavily doped region from
Son is lightly doped district；Described first polysilicon layer is formed source electrode, described 3rd polysilicon layer is formed grid
Pole, forms drain electrode at described substrate back.In said method, by traditional handicraft between grid and source class
ESD protection structure replaces with the back-to-back zener diode of array, and the voltage of zener diode is higher than grid
Pole running voltage, when MOSFET element works, always has part Zener diode to be in reverse-biased,
Do not interfere with the current potential on grid.When grid and source electrode produce instantaneous pressure because of electrostatic, Zener diode two
Pole pipe will puncture, and forms conductive channel static electricity discharge electric current, grid potential is clamped at ratio relatively low
Voltage (relative to the breakdown voltage of gate oxide), it is to avoid puncturing of gate oxide.
In order to make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to this
Bright it is described in further detail, it is clear that described embodiment is only some embodiments of the present invention,
Rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not doing
Go out all other embodiments obtained under creative work premise, broadly fall into the scope of protection of the invention.
Fig. 1 is the process chart of the manufacture method of a kind of MOSFET element disclosed in the embodiment of the present invention,
Specifically include following steps:
Step 101, sequentially forms the epitaxial layer of the first conduction type, grid on the substrate of the first conduction type
Oxide layer and polysilicon layer；
Step 102, etches described polysilicon layer and forms the first polysilicon layer, the second polysilicon layer and more than the 3rd
Crystal silicon layer, and carry out the first time injection of the second conductive type ion, in described epitaxial layer, form body district；
Step 103, carries out the second time of the second conductive type ion and injects and carry out high annealing for the first time,
Form heavy doping body district in described body district and in described second polysilicon layer, form spaced second lead
Electricity types of ion doped region, described second conductive type ion doped region includes that the second conductive type ion is heavily doped
Miscellaneous district and the second conductive type ion being positioned at around described second conductive type ion heavily doped region are lightly doped
District；
Step 104, carrying out first time of the first conductive type ion injects and carries out second time high annealing,
In described body district formed source region and in described second polysilicon layer formed with described second conduction type from
The first conductive type ion doped region that sub-doped region is arranged alternately, described first conductive type ion doped region
Including the first conductive type ion heavily doped region and be positioned at around described first conductive type ion heavily doped region
The first conductive type ion district is lightly doped；
Step 105, forms source electrode on described first polysilicon layer, is formed on described 3rd polysilicon layer
Grid, forms drain electrode at described substrate back.
Each step institute in the manufacturing process of the MOSFET element that Fig. 2 a-Fig. 2 i provides for the embodiment of the present invention
The device architecture schematic diagram obtained.
In a step 101, the substrate of the first conduction type sequentially forms the first conduction type epitaxial layer,
Gate oxide and polysilicon layer.
Making epitaxial layer, gate oxide and the structural representation of polysilicon layer on substrate as shown in Figure 2 a,
Wherein, 1 is substrate, and 2 is epitaxial layer, and 3 is gate oxide, and 4 is polysilicon layer.In the embodiment of the present invention
In, the first conductivity type substrate can be first provided, this first conductive substrates generates outside the first conduction type
Prolonging layer, this first conductivity type substrate can be N-type substrate, it is also possible to be P type substrate, when this first is led
When the substrate of electricity type is N-type substrate, the first conduction epitaxial layer being arranged in N-type substrate is outside N-type
Prolong layer；When the substrate of this first conduction type is P type substrate, the first conduction being arranged in P type substrate
Epitaxial layer is p-type epitaxial layer.
As shown in Figure 2 a, gate oxide 3, high temperature furnace pipe are generated at the first conductive type epitaxial layer 2 upper surface
Certain generation temperature, typically its growth temperature is provided to include but not limited to 900-1200 DEG C so that it is oxygen occurs
Change reaction and form gate oxide, it is also possible under other oxidizing condition, form the gate oxidation meeting condition
Layer, the gate oxide of generation has certain thickness, includes but not limited to 0.01 μm-10 μm, the present embodiment
In preferably silicon oxide layer be gate oxide；After forming gate oxide 3, under certain temperature conditions
On this gate oxide 3, the growth temperature of growing polycrystalline silicon layer 4, typically this polysilicon includes but not limited to
500-900 DEG C, thickness includes for but is not limited to 0.01 μm-10 μm.
In a step 102, etch described polysilicon layer and form the first polysilicon layer, the second polysilicon layer and
Three polysilicon layers, and carry out the first time injection of the second conductive type ion, in described epitaxial layer, form body
District.
In embodiments of the present invention, applying a layer photoetching glue on polysilicon layer 4, then photoresist is by covering
Lamina membranacea exposure forms photoresist mask, forms the first photoresist mask 51, and concrete structure is as shown in Figure 2 b；
On the basis of forming photoresist mask 51, polysilicon layer 4 is etched into the first polysilicon layer more than 41, second
Crystal silicon layer 42 and the 3rd polysilicon layer 43, concrete structure is as shown in Figure 2 c.Lithographic method in the present embodiment
Include but not limited to that dry etching, wet etching, dry etching and wet etching are used in mixed way, wherein mix
Using method includes but not limited to: first use dry etching to re-use wet etching, first use wet etching again
Use dry etching, first use dry etching re-use wet etching finally use dry etching, first use wet
Method etching re-uses dry etching and finally uses wet etching.
In embodiments of the present invention, if the first conductive type epitaxial layer is N-type, then note to this N-type epitaxy layer
Enter boron ion or aluminium ion, in this first conductive-type epitaxial layer, form the second conductivity type body region of p-type；
If on the contrary, the first conductive type epitaxial layer is p-type, then to this p-type epitaxial layer inject phosphonium ion or arsenic from
Son, forms the second conductivity type body region of N-type in this first conductive-type epitaxial layer.
If injecting ion is boron ion or aluminium ion, the dosage of injection is 1.0E12-1.0E15/cm2, energy
Amount is 60KEV-150KEV；The second conduction type body of p-type is formed in described first conductive-type epitaxial layer
District forms Equations of The Second Kind conductivity type body region 6, and concrete structure is as shown in Figure 2 d；If on the contrary, the ion injected
For phosphonium ion or arsenic ion, the dosage of injection is 1.0E12-1.0E15/cm2, energy is
60KEV-150KEV；The second conductivity type body region 6 of N-type is formed in described first conductive-type epitaxial layer,
Concrete structure is as shown in Figure 2 d.
After forming the second conductivity type body region in the first conductive-type epitaxial layer, remove the first polysilicon layer,
The first photoresist mask on second polysilicon layer and the 3rd polysilicon layer.
In step 103, carry out the second time of the second conductive type ion to inject and carry out high temperature for the first time and move back
Fire, forms heavy doping body district and forms spaced second in described second polysilicon layer in described body district
Conductive type ion doped region.
Coat on gate oxide, on the first polysilicon layer, on the second polysilicon layer and on the 3rd polysilicon layer
Photoresist mask, then photoresist forms photoresist mask 52 by mask plate exposure, concrete such as Fig. 2 e institute
Showing, wherein, photoresist mask 52 is by the first polysilicon layer 41 and the surface of the 3rd polysilicon layer 43 and side
Face all covers, and the side of the second polysilicon layer 42 is all covered by photoresist mask 52, but second
The first fragmentation state is presented on polysilicon layer 42.In embodiments of the present invention, on the second polysilicon layer 42
The number of fragments of the photoresist mask 52 forming the first fragmentation state is relevant with the width of the second polysilicon layer,
If the width of the second polysilicon layer is the biggest, the segmentation of the photoresist mask 52 of the most corresponding first fragmentation state
Quantity is the most.
Photoresist is formed on the first polysilicon layer, the second polysilicon layer and the surface of the 3rd polysilicon layer and side
After photoresist mask on mask, and second pair of crystal silicon layer is the first fragmentation state, proceeds by second and lead
The second time of electricity types of ion is injected.Wherein, the ion concentration that the second conductive type ion injects for the first time is
1.013～9.913, the ion concentration that the second conductive type ion second time is injected is 1.015～9.915。
If the second conduction type is p-type, then the dosage injected is 1.0E14～1.0E15/cm2, energy is
The phosphonium ion of 90KEV～150KEV or arsenic ion, form the second of p-type in the first conductive-type epitaxial layer
Heavy doping body district is formed in conductivity type body region；If the second conduction type is N-type, the dosage of injection is
1.0E14～1.0E15/cm2, energy is boron ion or the aluminium ion of 90KEV～150KEV, leads first
Heavy doping body district is formed in forming the second conductivity type body region of N-type in electricity class epitaxial layer.
Owing to, in the embodiment of the present invention, the photoresist mask on the second polysilicon layer is the first fragmentation state, then
Correspondingly, in the second polysilicon layer, form spaced second conductive type ion heavily doped region, wherein,
In second polysilicon layer, the width of spaced second conductive type ion heavily doped region is equal in first point
The width of the photoresist mask of section state.
As shown in Figure 2 e, 7 represent formation weight in the interior formation of the first conductive-type epitaxial layer the second conductivity type body region
Doped body region；421 represent that interior spaced second conductive type ion formed of the second polysilicon layer is heavily doped
Miscellaneous district.
Owing to first kind conductivity type regions has certain thickness, in order to ensure the second conductive type ion second
Ion depth that secondary injection can reach technological requirement and the heavily doped region formed in the second polysilicon layer
Both sides can be formed and district is lightly doped, and can carry out high temperature after the second time of the second conductive type ion is injected
Drive in, so that the heavy doping ion in the second conductivity type body region can be diffused into the deep of needs
Degree, and the two of the spaced second conductive type ion heavily doped region formed in the second polysilicon layer
Side can be formed and district is lightly doped.Wherein, the temperature that high temperature drives in can control for 1100 DEG C～1200 DEG C
Between, the time is about 90～180min, carries out annealing process after ion implantation.
As shown in figure 2f, the heavy doping body district in the second conduction type in 8 expression the first conductive-type epitaxial layers
Doped region after high temperature drives in；Wherein, the second conduction type doped region 8 includes the second conduction type body
Heavy doping body district 7 in district and the second conductivity type body region 6.4211 represent the interior formation of the second polysilicon layer
Spaced second conductive type ion doped region, wherein, the second conductive type ion doped region includes
Two conductive type ion heavily doped regions 421 and be positioned at around the second conductive type ion heavily doped region 421
Two conductive type ions are lightly doped district.
In step 104, the first time carrying out the first conductive type ion injects and carries out second time high annealing,
In described body district formed source region and in described second polysilicon layer formed with described second conduction type from
The first conductive type ion doped region that sub-doped region is arranged alternately.
Coat on gate oxide, on the first polysilicon layer, on the second polysilicon layer and on the 3rd polysilicon layer
Photoresist mask, then photoresist forms photoresist mask 53 by mask plate exposure, concrete such as Fig. 2 g institute
Showing, wherein, photoresist mask 53 covers the heavy doping body district 7 in the second conductivity type body region, and
The second fragmentation state is formed on two polysilicon layers 42.In embodiments of the present invention, at the second polysilicon layer 42
In the number of fragments of the photoresist mask 53 of upper formation the second fragmentation state and the second polysilicon layer 42 second
The order of magnitude width of conductive type ion doped region 4211 is correlated with, if the second electricity class on the second polysilicon 42
The quantity of type ion doped region 4211 is the most, then the number of fragments of the photoresist mask 53 of the second fragmentation state
The most, if the width of the second electricity types of ion doped region 4211 is the biggest, then the photoresist of the second fragmentation state
Mask 53 width can be the biggest, and, the width of the photoresist mask 53 of the second fragmentation state is more than the
The width of two electricity types of ion doped regions 4211.
It is preferred that the distance between the photoresist mask of the first fragmentation state and the light of described second fragmentation state
The distance of photoresist mask is equal.
In embodiments of the present invention, if the first conductive type epitaxial layer is N-type, then to this second conduction type
Injecting phosphonium ion or arsenic ion in body district, wherein, the implantation dosage of phosphonium ion or arsenic ion is
1.0E14-1.0E15 individual/cm2, energy is 60KEV-120KEV, forms the first conduction type source of N-type
District；Contrary, if the first conductive type epitaxial layer is p-type, then inject in this second conduction type well region
Boron ion or aluminium ion, wherein, inject boron ion or aluminum ions dosage be 1.0E14-1.0E15/cm2,
Energy is 60KEV-120KEV, forms the first conduction type source region of p-type.
Owing to, in the embodiment of the present invention, the photoresist mask on the second polysilicon layer is the second fragmentation state, then
Correspondingly, in the second polysilicon layer, form first be arranged alternately with the second conductive type ion doped region to lead
Electricity types of ion doped region, wherein, the first conductive type ion heavily doped region formed in the second polysilicon layer
Width equal to the width of photoresist mask in the second fragmentation state.
As shown in Figure 2 g, 9 represent interior the first conduction type source region formed of the first conductive-type epitaxial layer；422
The the first conductive type ion heavily doped region formed in representing the second polysilicon layer.
Owing to first kind conductivity type regions has certain thickness, in order to ensure the first conductive type ion first
Secondary injection can reach technological requirement ion depth and in the second polysilicon layer formed the first conductive-type
The both sides of type ion heavily doped region can be formed and district is lightly doped, can be in the first time of the first conductive type ion
(simultaneously) carry out high temperature after injection to drive in, so that the heavy doping in the first conductivity type body region
Ion can be diffused into the degree of depth of needs, and spaced first formed in the second polysilicon layer is led
The both sides of electricity types of ion heavily doped region can be formed and district is lightly doped.Wherein, the temperature that high temperature drives in can be controlled
System is between for 850～950 DEG C, and the time is about 60～120min, carries out annealing process after ion implantation.
As shown in fig. 2h, 91 represent that interior the first conduction type source region formed of the first conductive-type epitaxial layer is at high temperature
Doped region after driving in；In embodiments of the present invention, owing to the temperature of first time high annealing is higher than second
The temperature of secondary high annealing, so after second time high annealing, the formed in the first conductive-type epitaxial layer
One conduction type source region high temperature drive in the doped region that formed afterwards than the first conduction type source region the degree of depth only
There is small change.4221 represent interior the first conductive type ion doped region formed of the second polysilicon layer, its
In, the first conductive type ion doped region includes the first conductive type ion heavily doped region 422 and is positioned at first
The first conductive type ion around conductive type ion heavily doped region 422 is lightly doped district.
In step 105, described first polysilicon layer forms source electrode, on described 3rd polysilicon layer
Form grid, form drain electrode at described substrate back.
As shown in fig. 2i, at the first polysilicon layer the 41, second polysilicon layer 42 and the 3rd polysilicon layer 43
And on gate oxide 3, generating dielectric layer 10, the dielectric layer of growth can be silicon oxide or silicon nitride, and thickness is
1 μm-12 μm, after the growth completing dielectric layer 10, needs to carry out at the first polysilicon layer 41 and the 3rd
On polysilicon layer 43, perforate forms source class 11 and grid 12.Source electrode 11 He is made at dielectric layer 10 upper surface
Grid 12 metal level 13, metal level 13 is connected with source region 9 and grid by contact hole, forms source electrode and grid
Electrode structure；Make drain metal layer 13 at substrate 1 lower surface, form drain electrode structure, wherein source class and grid
Metal level be titanium, nickel, aluminum one or more layers, drain metal layer be titanium, nickel, aluminum one or more layers.
In embodiments of the present invention, in the second polysilicon layer, spaced second conductive type ion is formed
Doped region and the first conductive type ion doped region of being arranged alternately with the second conductive type ion doped region are such as
Shown in Fig. 3, wherein, the second conductive type ion doped region 3 in the second polysilicon layer includes the second conduction
Types of ion heavily doped region 30 and the second conductive-type being positioned at around the second conductive type ion heavily doped region 30
Type ion is lightly doped district 31；First conductive type ion doped region 4 includes the first conductive type ion heavy doping
District 40 and the first conductive type ion being positioned at around described first conductive type ion heavily doped region 40 are gently mixed
Miscellaneous district 41.
In above-described embodiment, diode N district and P district between source class and grid are respectively adopted N-type
Formed with p-type heavy doping, inject in the second time carrying out the second conductive type ion and carry out high temperature for the first time
After annealing, in the second polysilicon layer, form spaced second conductive type ion doped region, entering
After the first time of row the first conductive type ion injects and carries out second time high annealing, at the second polysilicon
The the first conductive type ion doped region being arranged alternately with the second conductive type ion doped region is formed in layer, its
In, described second conductive type ion doped region includes the second conductive type ion heavily doped region and is positioned at described
The second conductive type ion around second conductive type ion heavily doped region is lightly doped district；First conduction type
Ion doped region includes the first conductive type ion heavily doped region and is positioned at described first conductive type ion weight
The first conductive type ion around doped region is lightly doped district.Thus can be formed N+_N-/P-_P+ structure or
, owing to there is N-/P-graded transition junction in this structure, when grid and source electrode are because of electrostatic in person's P-_P+/N+_N-structure
When producing instantaneous pressure, N+_N-/P-_P+ structure or P-_P+/N+_N-structure will puncture, shape
Become conductive channel static electricity discharge electric current, grid potential is clamped at than relatively low voltage (relative to gate oxide
Breakdown voltage), it is to avoid the puncturing of gate oxide.
Based on identical inventive concept, the embodiment of the present invention also provides for a kind of metal oxide semiconductor field-effect
Pipe MOSFET element, a kind of metal oxide semiconductcor field effect present invention provided below in conjunction with Fig. 2 i
Should the concrete structure of pipe MOSFET element be illustrated.
The first conductive type epitaxial layer 2 on substrate 1 is set.
Be arranged on described first conductive type epitaxial layer 2 Nei Ti district 8 and in described body district formed heavily doped
Za Ti district 7 and source region 9.
First polysilicon layer the 41, second polysilicon layer being arranged on described first conductive type epitaxial layer 2
42 and the 3rd polysilicon layer 43.
Be arranged at intervals with in described second polysilicon layer 42 second conductive type ion doped region 4211 and with institute
State the first conductive type ion doped region 4221 that the second conductive type ion doped region is arranged alternately.
Described second conductive type ion doped region 4211 includes second conductive type ion heavily doped region (Fig. 2 i
Not shown in) and be positioned at described second conductive type ion heavily doped region (not shown in Fig. 2 i) second around
Conductive type ion is lightly doped district (not shown in Fig. 2 i).
Described first conductive type ion doped region 4221 includes first conductive type ion heavily doped region (Fig. 2 i
Not shown in) and be positioned at described first conductive type ion heavily doped region (not shown in Fig. 2 i) first around
Conductive type ion is lightly doped district (not shown in Fig. 2 i).
It is provided with source electrode 11 on described first polysilicon layer 41, described 3rd polysilicon layer 43 is provided with grid
Pole 12, described substrate back is provided with drain electrode (not shown in Fig. 2 i).
Further, the width of described second conductive type ion doped region 4211 and described first conductive-type
The width of type ion doped region 4221 is equal.
Further, the width of described second conductive type ion heavily doped region (not shown in Fig. 2 i) and institute
The width stating the first conductive type ion heavily doped region (not shown in Fig. 2 i) is equal.
In the present embodiment, if the first conduction type is N-type, then the second conduction type is p-type；If first leads
Electricity type is p-type, then the second conduction type is N-type.
Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.
Claims (9)
1. a manufacture method for metal oxide semiconductor field effect tube MOSFET element, its feature exists
In, including:
The substrate of the first conduction type sequentially forms the epitaxial layer of the first conduction type, gate oxide and many
Crystal silicon layer；
Etch described polysilicon layer and form the first polysilicon layer, the second polysilicon layer and the 3rd polysilicon layer, and
The first time carrying out the second conductive type ion injects, and forms body district in described epitaxial layer；
The second time carrying out the second conductive type ion is injected and carries out high annealing for the first time, in described body district
Interior formation heavy doping body district and formed in described second polysilicon layer spaced second conduction type from
Sub-doped region, described second conductive type ion doped region includes the second conductive type ion heavily doped region and position
The second conductive type ion around described second conductive type ion heavily doped region is lightly doped district；
The first time carrying out the first conductive type ion injects and carries out second time high annealing, in described body district
Interior formation source region and formation and described second conductive type ion doped region friendship in described second polysilicon layer
For the first conductive type ion doped region arranged, described first conductive type ion doped region includes that first leads
Electricity types of ion heavily doped region and the first conduction being positioned at around described first conductive type ion heavily doped region
Types of ion is lightly doped district；
Described first polysilicon layer is formed source electrode, described 3rd polysilicon layer forms grid, in institute
State substrate back and form drain electrode.
2. the method for claim 1, it is characterised in that the described polysilicon layer of described etching is formed
First polysilicon layer, the second polysilicon layer and the 3rd polysilicon layer, and carry out the of the second conductive type ion
Once inject, in described epitaxial layer, form body district, particularly as follows:
Described polysilicon layer arranges photoresist, the first photoresist mask that etching is formed, described first light
Photoresist mask covers at described first polysilicon layer, described second polysilicon layer and described 3rd polysilicon layer
On；
After described body district is formed, remove described first photoresist mask.
3. the method for claim 1, it is characterised in that described in carry out the second conductive type ion
Second time inject and carry out for the first time high annealing, particularly as follows:
At described gate oxide, described first polysilicon layer, described second polysilicon layer and described 3rd polycrystalline
Silicon layer arranges photoresist, and etching forms the second photoresist mask, and described second photoresist mask covers described the
One polysilicon layer, described second polysilicon layer and the surface of described 3rd polysilicon layer and side, and described
In the first fragmentation state on second polysilicon layer；
After described second time is injected, remove described second photoresist mask.
4. the method for claim 1, it is characterised in that described in carry out the first conductive type ion
First time inject and carry out second time high annealing, particularly as follows:
At described gate oxide, described first polysilicon layer, described second polysilicon layer and described 3rd polycrystalline
Silicon layer arranges photoresist, and etching forms the 3rd photoresist mask, and described 3rd photoresist mask covers described heavy
Doped body region, and in the second fragmentation state on described second polysilicon layer, each point of described second segmentation
The length of section is more than the second conductive type ion doped region of corresponding part；
After described third time is injected, remove described 3rd photoresist mask.
5. the method as described in claim 3 or 4, it is characterised in that the light of described first fragmentation state
Distance between photoresist mask is equal with the distance of the photoresist mask of described second fragmentation state.
6. the method for claim 1, it is characterised in that the temperature of described first time high annealing
Temperature higher than described second time high annealing.
7. a metal oxide semiconductor field effect tube MOSFET element, it is characterised in that including:
The first conductive type epitaxial layer being arranged on substrate；
It is arranged on described first conductive type epitaxial layer Nei Ti district and the heavy doping formed in described body district
Body district and source region；
It is arranged on the first polysilicon layer on described first conductive type epitaxial layer, the second polysilicon layer and the 3rd
Polysilicon layer；
The second conductive type ion doped region it is arranged at intervals with and with described second in described second polysilicon layer
The first conductive type ion doped region that conductive type ion doped region is arranged alternately；
Described second conductive type ion doped region includes the second conductive type ion heavily doped region and is positioned at institute
The second conductive type ion stated around the second conductive type ion heavily doped region is lightly doped district；
Described first conductive type ion doped region includes the first conductive type ion heavily doped region and is positioned at institute
The first conductive type ion stated around the first conductive type ion heavily doped region is lightly doped district；
It is provided with source electrode on described first polysilicon layer, described 3rd polysilicon layer is provided with grid, described
Substrate back is provided with drain electrode.
8. device as claimed in claim 7, it is characterised in that described second conductive type ion doping
The width in district and the width of described first conductive type ion doped region are equal.
9. device as claimed in claim 8, it is characterised in that described second conductive type ion is heavily doped
The width in miscellaneous district and the width of described first conductive type ion heavily doped region are equal.
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| CN111063618A (en) * | 2019-12-28 | 2020-04-24 | 无锡紫光微电子有限公司 | ESD (electro-static discharge) protection structure of VDMOS (vertical double-diffused metal oxide semiconductor) device and manufacturing process thereof |
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| US20050156267A1 (en) * | 2004-01-13 | 2005-07-21 | Shogo Mori | Semiconductor device provided with temperature detection function |
| CN102097433A (en) * | 2009-12-10 | 2011-06-15 | 力士科技股份有限公司 | Trench metal-oxide semiconductor field effect transistor (MOSFET) and manufacture method thereof |
| CN102254859A (en) * | 2010-05-17 | 2011-11-23 | 北大方正集团有限公司 | Method for manufacturing metal oxide semiconductor integrated circuit comprising Zener diode |
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| JPH0945905A (en) * | 1995-07-28 | 1997-02-14 | Nec Kansai Ltd | Semiconductor device and its manufacture |
| US20050156267A1 (en) * | 2004-01-13 | 2005-07-21 | Shogo Mori | Semiconductor device provided with temperature detection function |
| CN102097433A (en) * | 2009-12-10 | 2011-06-15 | 力士科技股份有限公司 | Trench metal-oxide semiconductor field effect transistor (MOSFET) and manufacture method thereof |
| CN102254859A (en) * | 2010-05-17 | 2011-11-23 | 北大方正集团有限公司 | Method for manufacturing metal oxide semiconductor integrated circuit comprising Zener diode |
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| CN111063618A (en) * | 2019-12-28 | 2020-04-24 | 无锡紫光微电子有限公司 | ESD (electro-static discharge) protection structure of VDMOS (vertical double-diffused metal oxide semiconductor) device and manufacturing process thereof |
| CN111063618B (en) * | 2019-12-28 | 2023-05-26 | 无锡紫光微电子有限公司 | ESD protection structure of VDMOS device and manufacturing process thereof |
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