CN106293636A - The implementation method of a kind of pipelining-stage, pipelining-stage and streamline - Google Patents
The implementation method of a kind of pipelining-stage, pipelining-stage and streamline Download PDFInfo
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Abstract
The embodiment of the invention discloses the implementation method of a kind of pipelining-stage, pipelining-stage and streamline, be applied to hardware circuit design technical field.For the specification that the design offer of the streamline in hardware circuit is unified, it is achieved the modularized design of streamline.Specifically include that in pipelining-stage, the storage depth of data is 1；The state of pipelining-stage, for time full, writes out enable signal effective；Pipelining-stage is for full and write out ready signal effectively or pipelining-stage is for time empty, and write ready signal is effective；The most described method comprises determining that the state of pipelining-stage, and if it is empty, and write enables signal effectively, then write data and the control signal of these data；If full, and it is effective to write out ready signal, then write ready signal is effective, writes out the control signal of data and these data；If it is effective that write enables signal, then write data and the control signal of these data.
Description
Technical field
The present invention relates to hardware design technique field, particularly relate to the implementation method of a kind of pipelining-stage, flowing water
Level and streamline.
Background technology
Streamline is control strategy conventional in hardware designs.The control of its corresponding state machine has higher effect
Rate, thus by the favor of senior Hardware Engineers.
Existing the pipeline design is to be designed with streamline for entirety, and this design is primarily present following
Problem: be designed without unified standard, particularly during joint development, be difficult to check the code safeguarding others；
During using streamline as global design, (control protocol is such as real for pipeline series and flowing water control strategy
The most predetermined function, gives the variable assignments of regulation, the computing etc. of data) bound, it is all first at literary composition
Plan in Dang, then (register transfer level refers to by this rank of depositor to do RTL
Describing mode describes the stream socket of circuit) design, when needs change pipeline series, need
Corresponding amendment flowing water control strategy.This amendment is modified using streamline as entirety, often changes
Relatively big, even need to redesign, checking also to be done again, takes time and effort.It is unfavorable for the liter of streamline
Level.
Summary of the invention
Inventor finds through numerous studies, and existing the pipeline design exists the basic reason of the problems referred to above and is
There is presently no the pipelining-stage worked alone, so that existing streamline can not realize modularized design, can only
Entirety is designed.Embodiments provide the implementation method of a kind of pipelining-stage, pipelining-stage and flowing water
Line, design realizes a kind of self-existent pipelining-stage, uses unified connection side on the basis of pipelining-stage
Formula realizes the modularized design of streamline, and the design for streamline provides a kind of unified design standard, makes
The structure obtaining streamline has versatility, autgmentability, conveniently carries out insertion and the cutting of pipelining-stage, and
The later maintenance of streamline and upgrading, reduce the design difficulty of streamline.
In view of this, first aspect present invention provides the implementation method of a kind of pipelining-stage, including:
In described pipelining-stage, the storage depth of data is 1；The state of pipelining-stage is for, time full, writing out enable signal
Effectively；Pipelining-stage is for full and write out ready signal effectively or pipelining-stage is for time empty, and write ready signal is effective；
The most described method includes:
Judging the state of pipelining-stage, if it is empty, and write enables signal effectively, then write data and be somebody's turn to do
The control signal of data；
If full, and it is effective to write out ready signal, then write ready signal is effective, writes out data and is somebody's turn to do
The control signal of data；If it is effective that write enables signal, then write data and the control signal of these data.
Preferably, the state of described judgement pipelining-stage includes:
Judge that the numerical value being used for the first bit and the second bit indicating pipelining-stage state is the most equal,
If equal, then pipelining-stage state is empty；Otherwise it is full；Wherein, the first bit enables signal in write
Upset during with write ready signal all effectively；Second bit is writing out enable signal and is writing out ready signal
Upset time all effectively.
The embodiment of the present invention also provides for the implementation method of a kind of pipelining-stage, the storage of data in described pipelining-stage
The degree of depth is more than 1；When the state of pipelining-stage is non-full, write ready signal is effective；When pipelining-stage is non-NULL,
Write out enable signal effective；The most described method includes:
Judging the state of pipelining-stage, if the state of pipelining-stage is not only non-NULL but also non-full, and write enables signal
Effectively, then data and the control signal of these data are write according to first in first out mechanism to pipelining-stage；If writing
Go out ready signal effective, then write out the control of data and these data according to first in first out mechanism from pipelining-stage
Signal；
If it is empty, and write enables signal effectively, then according to first in first out mechanism to pipelining-stage write data
And the control signal of these data；
If full, and it is effective to write out ready signal, then write out data according to first in first out mechanism from pipelining-stage
And the control signal of these data.
Preferably, the state of described judgement pipelining-stage includes:
Judge to indicate the whether phase of the low level numerical value in the first dibit of pipelining-stage state and the second dibit
Deng；
If low level numerical value is unequal, then the state of pipelining-stage is not only non-NULL but also non-full；If low level numerical value is equal,
Then judge that the high-order numerical value in the first dibit and the second dibit is the most equal；
If high-order numerical value is equal, then pipelining-stage is empty；If high-order numerical value is unequal, then pipelining-stage is full；
Wherein, the first dibit numerical value when write enables signal and write ready signal is all effective adds 1；Second pair
Bit write out enable signal and data write out ready signal all effectively time numerical value add 1.
The embodiment of the present invention also provides for a kind of pipelining-stage, including: the storage depth of data in described pipelining-stage
It is 1；The state of pipelining-stage, for time full, writes out enable signal effective；Pipelining-stage be empty or pipelining-stage for full and
Write out ready signal effective time, write ready signal effective；The most described pipelining-stage includes:
First judge module, for judging the state of pipelining-stage；
First writing module, when the first judge module judges pipelining-stage state as sky, if write enables
Signal is effective, write data and the control signal of these data；
First writes out module, for the first judge module judge pipelining-stage as time full, if writing out ready signal
Effectively, the control signal of data and these data is write out；
First determines module, judges that pipelining-stage, as time full, determines that write prepares letter for the first judge module
Number effectively；
Second writing module, for first determine module judge write enable signal effective time, if data are write
Go out successfully, write data and the control signal of these data.
The embodiment of the present invention also provides for a kind of pipelining-stage, and in described pipelining-stage, the storage depth of data is more than 1；
When the state of pipelining-stage is non-full, write ready signal is effective；When pipelining-stage is non-NULL, write out enable letter
Number effectively；The most described pipelining-stage includes:
Second judge module, for judging the state of pipelining-stage；
3rd writing module, the state for pipelining-stage be not only non-NULL but also non-full time, if write enables signal
Effectively, then data and the control signal of these data are write according to first in first out mechanism to pipelining-stage；
Second writes out module, the state for pipelining-stage be not only non-NULL but also non-full time, if writing out ready signal
Effectively, write out the control signal of data and these data from pipelining-stage according to first in first out mechanism；
4th writing module, for pipelining-stage be empty time, if write to enable signal effective, according to advanced person first
Go out mechanism to pipelining-stage write data and the control signal of these data；
3rd writes out module, for pipelining-stage for time full, if it is effective to write out ready signal, according to advanced person first
Go out mechanism and write out the control signal of data and these data from pipelining-stage.
The embodiment of the present invention also provides for a kind of streamline, and described streamline includes: any of the above-described described depositing
The storage degree of depth is multiple pipelining-stages and/or any of the above-described described storage depth multiple pipelining-stages more than 1 of 1；
Previous pipelining-stage connects at least one next stage pipelining-stage, and previous stage pipelining-stage is selected by gating signal
Select next stage pipelining-stage；
Connection between the pipelining-stage of adjacent two-stage is as follows: the enable signal that writes out of previous stage pipelining-stage inputs
To rear stage pipelining-stage, the write as next stage pipelining-stage enables signal；Writing out of previous stage pipelining-stage
Control signal inputs to rear stage pipelining-stage, as the write control signal of rear stage pipelining-stage；Previous stage
The data that pipelining-stage writes out input to rear stage pipelining-stage, as the input data of rear stage pipelining-stage；After
The write ready signal of one-level pipelining-stage inputs to previous stage pipelining-stage, as writing out of previous stage pipelining-stage
Ready signal.
Preferably, when previous stage pipelining-stage connects multiple next stage pipelining-stage, the control letter of corresponding data
The mark of the next stage pipelining-stage of data flow, and the sequence identification of data is carried in number.
Preferably, the write ready signal of part pipelining-stage passes through inside pipelining-stage with writing out ready signal
Depositor is isolated, to reach the streamline requirement to sequential.
As can be seen from the above technical solutions, the embodiment of the present invention has the advantage that
The embodiment of the present invention is that pipelining-stage provides a kind of independent work-based logic, under this work-based logic,
Pipelining-stage is considered as an independent module and is operated.
Further, after obtaining having the pipelining-stage of the logic that works alone as, pipelining-stage is regarded a mould
Block, when being cascaded into streamline, inputs to previous stage except the data of rear stage pipelining-stage write ready signal
Pipelining-stage, outside writing out ready signal as the data of previous stage pipelining-stage, only needs the defeated of prime pipelining-stage
Go out class signal and be connected to subordinate's pipelining-stage as input signal.Above-mentioned connected mode provides for pipelining-stage cascade
A kind of general connected mode.In the manner described above, streamline can be carried out the cutting of pipelining-stage with
And insert, it is achieved simple so that the work of streamline is the most flexible.
Accompanying drawing explanation
Fig. 1 is the flow chart of the implementation method embodiment 1 of a kind of pipelining-stage in the embodiment of the present invention；
Fig. 2 is the structural representation of a kind of pipelining-stage embodiment 1 in the embodiment of the present invention；
Fig. 3 is the sequential chart of a kind of pipelining-stage corresponding to the embodiment of the present invention；
Fig. 4 is the flow chart of the implementation method embodiment 2 of a kind of pipelining-stage in the embodiment of the present invention；
Fig. 5 is the structural representation of a kind of pipelining-stage embodiment 2 in the embodiment of the present invention；
Fig. 6 is the another kind of pipelining-stage sequential chart that the embodiment of the present invention is corresponding；
Fig. 7 is a unidirectional strip streamline schematic diagram in the embodiment of the present invention；
Fig. 8 is a crossed flow shop schematic diagram in the embodiment of the present invention.
Detailed description of the invention
In order to make those skilled in the art be more fully understood that the present invention program, real below in conjunction with the present invention
Execute the accompanying drawing in example, the technical scheme in the embodiment of the present invention be clearly and completely described, it is clear that
Described embodiment is only the embodiment of a present invention part rather than whole embodiments.Based on
Embodiment in the present invention, those of ordinary skill in the art are obtained under not making creative work premise
, every other embodiment, all should belong to the scope of protection of the invention.
Technical scheme to the embodiment of the present invention does description detailed, disclosed below.
First introduce the port signal that pipelining-stage is arranged, mainly include clock signal (clk), reset
Signal (rst), write enable signal (upen), write ready signal (uprdy), write control letter
Number (upctrl), write data signal (upda), write out enable signal (dnen), write out preparation letter
Number (dnrdy), write out control signal (dnctrl), write out data signal (dnda).
Wherein clock signal (clk), reset signal (rst) are system level signals.Write enables signal (upen)
It is foundation during pipelining-stage write data, when both is effective, stream with write ready signal (uprdy)
Water level could write data (write data signal (upda)).In like manner, write out enable signal (dnen),
Writing out ready signal (dnrdy) is pipelining-stage foundation when writing out data, when both is effective, flowing water
Level just can write out data (writing out data signal (dnda)).
With data signal (write data signal, write out data signal) corresponding (writing for control signal
Control signal (upctrl), write out control signal (dnctrl)), control signal is according to the merit implemented
Can arrange, the data operation set when i.e. implementing certain function on the basis of pipelining-stage or transmission
Agreement, such as under a certain concrete function, does following control protocol: when the data of write set more than a certain
During fixed number value, data are deducted setting numerical value.
The signal occurred in following example, with reference to foregoing description, repeats no more.
The present invention provides the implementation method embodiment 1 of a kind of pipelining-stage, with reference to the flow chart shown in Fig. 1, this
In pipelining-stage described in embodiment, the storage depth of data is 1, and described storage depth refers to that pipelining-stage can be deposited
The number of the data of storage certain length, such as, the storage data set in pipelining-stage are as 32, if flowing water
In Ji, the storage depth of data is 1, then pipelining-stage can only store the data of 1 32, if in pipelining-stage
The storage depth of data is 3, then pipelining-stage can store the data of 3 32.
The present embodiment specifically may include steps of:
S11, judge the state of pipelining-stage；
In pipelining-stage described in the present embodiment, the storage depth of data is 1, therefore its state has two kinds: empty (stream
Water level does not has data) and full (pipelining-stage has data).
When the state of pipelining-stage is empty, i.e. pipelining-stage does not has data, then can write in pipelining-stage
Data, now write ready signal is effective, in order to prepare for writing data in pipelining-stage.
When the state of pipelining-stage is for, time full, can read data from pipelining-stage, write out enable signal effective,
So that preparing for writing out data from pipelining-stage.If it is also effective now to write out ready signal, the most permissible
Writing out data from pipelining-stage, once data are written out, then pipelining-stage is in the state of sky, so at this
In the case of Zhong, i.e. pipelining-stage for full and write out ready signal effective time, write ready signal is effective, in order to
After being written out in data, prepare for writing data in pipelining-stage.
When this step judging pipelining-stage state as sky, enter step S12, when pipelining-stage state is full,
Enter step S14.
S12, judge write enable signal the most effective；
When the state of pipelining-stage is empty, can write data in pipelining-stage, now write out enable signal without
Effect, write ready signal is effective.Due to write out enable signal with when writing out ready signal all effectively, just meeting
Output data, so, when writing out enable invalidating signal, it is not necessary to judge again to write out whether ready signal has
Effect, only need to judge that write enables signal the most effective.
When write ready signal is effective and write enable signal is effective, then perform step S13, to pipelining-stage
Middle write data and the control signal of these data.If now write ready signal is effective, and writes enable
Invalidating signal, then write data failure.
Wherein, in the present embodiment, the signal of indication effectively says that signal is in high level or low level,
As for high level the most still Low level effective, can be arranged by User Defined, repeat no more here.
S13, write data and the control signal of these data；
S14, judge that to write out ready signal the most effective；
The state of pipelining-stage, for, time full, reading data from pipelining-stage, writes out enable signal effective,
Judgement is needed to write out ready signal the most effective.
When write out enable signal effectively and write out ready signal effective time, enter step S15.When writing out enable
Signal effectively write out ready signal invalid time, write out data failure.Owing to the state of pipelining-stage is full,
So, once data write out failure, the most now write relevant signal the most effective, write data
It is all failed.
S15, write out the control signal of data and these data.
In the case of the state of pipelining-stage is full, when writing out ready signal and being all effective, write prepares to believe
Number also effective, so after execution of step S15, entering step S16 and determine whether to write data.
S16, judge write enable signal the most effective；
Result based on step S15 understands, and write ready signal is also effective, if now write enables signal
Also effective, then can write data, enter step S17.
S17, write data and the control signal of these data.
When the state of pipelining-stage is empty, then can only receive the data (write ready signal is effective) of input,
Can not outwards write out data (writing out enable invalidating signal)；When pipelining-stage state is for time full, then can be to
Write out outward data (writing out enable signal effective), the data of write can be received then by pipelining-stage simultaneously
Write out data the most successfully to determine.
Owing to prior art not having independent pipelining-stage, so streamline is to carry out with entirety when design
Design, it has not been convenient to the upgrading in later stage.The technical scheme that the present embodiment provides, predominantly realizes a kind of only
Vertical pipelining-stage provides a kind of feasible method, and the modularized design for streamline lays the foundation.
Preferably, on the basis of embodiment 1, when judging the state of pipelining-stage, can be by arranging
The mode of indicating bit indicates the state of pipelining-stage, such as, arranges two bits and is designated as the first bit respectively
Position and the second bit, (be such as " 0 " when the numerical value of the first bit and the second bit is equal
Or it is " 1 "), instruction pipelining-stage state is empty, otherwise is full.It is of course also possible to set the first ratio
When the numerical value of special position and the second bit is equal, pipelining-stage state be full, otherwise is sky, does not makees to have
Body limits.
It will be understood by those skilled in the art that the instruction of pipelining-stage state can be by the self-defined reality of designer
Existing, it is not limited to aforesaid way.
In the course of normal operation of pipelining-stage, along with data write with write out, the state of pipelining-stage is
Real-time change, so the reaction pipelining-stage that the indicating bit of instruction pipelining-stage state should be real-time is true
Real state, can be accomplished in that in this practical operation
When write enables signal and write ready signal is all effective, the first bit upset；Write out enable
Signal with write out ready signal all effectively time, the second bit upset.
In pipelining-stage work process, judge the state of pipelining-stage in real time according to the numeric state of indicating bit,
Carry out the write of data according to judged result or write out.Pipelining-stage is once reset, then pipelining-stage returns to
Original state, the indicating bit of instruction pipelining-stage state is entered as 0.
Accordingly, the embodiment of the present invention also provides for a kind of pipelining-stage embodiment 1, with reference to shown in Fig. 2, for right
The structural representation answered, wherein, in described pipelining-stage, the storage depth of data is 1；The state of pipelining-stage is
Man Shi, writes out enable signal effective；Pipelining-stage for full and write out ready signal effectively or pipelining-stage is for time empty,
Write ready signal is effective, and the most described pipelining-stage includes:
First judge module 21, for judging the state of pipelining-stage；
First writing module 22, when the first judge module judges pipelining-stage state as sky, if write makes
Energy signal is effective, write data and the control signal of these data；
First writes out module 23, judges that pipelining-stage, as time full, is believed if writing out preparation for the first judge module
Number effectively, the control signal of data and these data is write out；
First determines module 24, judges that pipelining-stage, as time full, determines that write prepares for the first judge module
Signal is effective；
Second writing module 25, for first determine module judge write enable signal effective time, if data
Write out successfully, write data and the control signal of these data.
Preferably, the judgement of pipelining-stage state is referred to above-mentioned to arranging the description of indicating bit, the most not
Repeat again.
For the ease of the understanding to the technical scheme that the embodiment of the present invention provides, below by citing to above-mentioned
Content is briefly described.
Shown in reference table 1, for the port design reference of pipelining-stage, arrange with reference to the port of aforementioned pipelining-stage,
In practical operation, arrange clock signal (clk), reset signal (rst), write enable signal (upen),
Write control signal (upctrl), data to be written and to write out ready signal (dnrdy) be flowing water lineman
The input signal received during work.Write control signal (upctrl), data to be written are write together
Enter pipelining-stage.
The port design of table 1 pipelining-stage
Shown in corresponding work-based logic reference table 2, with the first bit as wp1, the second bit is as rp1
Schematically illustrate, wherein wp1 and rp1 can realize with depositor in actual applications.
Table 2 pipelining-stage work-based logic explanation
Shown in truth table reference table 3 corresponding to logic that table 2 describes, wherein represent the shape of signal with " 1 "
State is effectively, represents that with " 0 " state of signal is invalid.
The truth table of the pipelining-stage logic of table 3 table 2 correspondence
Under corresponding logical design, illustrate obtained according to the logical design of Tables 1 and 2
Concrete sequential chart, with reference to shown in Fig. 3.Table 4 is corresponding sequential explanation.
Sequential explanation shown in table 4 corresponding diagram 3
On the basis of embodiment 1, the present invention also provides for the implementation method embodiment 2 of a kind of pipelining-stage, ginseng
Examining the flow chart shown in Fig. 4, wherein, in described pipelining-stage, the storage depth of data is more than 1；Set flowing water
When the state of level is non-full, write ready signal is effective；When pipelining-stage is non-NULL, writing out enable signal has
Effect；Then the present embodiment specifically includes that
S401, judge the state of pipelining-stage；
Unlike said method embodiment 1, in the present embodiment, the storage depth of pipelining-stage is more than 1, institute
With the state of pipelining-stage except empty and full in addition to, also have the most non-full but also non-NULL.Such as, data in pipelining-stage
Storage depth be 3, and in pipelining-stage storage data only have 2.
If the state of pipelining-stage is not only non-NULL but also non-full, enter step S402, if the state of pipelining-stage is
Sky, enters step S404, if the state of pipelining-stage is full, enters step S405.
If S402 write to enable signal effective, then according to first in first out mechanism to pipelining-stage write data with
And the control signal of these data；
When pipelining-stage is in non-NULL the most non-full state, the write that both can carry out data can also count
According to write out, simultaneously according to the content set, when pipelining-stage is in non-NULL the most non-full state, write
Enter ready signal with write out enable signal the most effective.When writing ready signal and being effective, write enables signal
Also effective, then can carry out the write of data, owing in pipelining-stage, the storage depth of data is more than 1, so
Preferably, first in first out mechanism is used to carry out write and the reading of data here, it is ensured that the order of data.
Otherwise, if write enables invalidating signal, then write data failure.
If S403 to write out ready signal effective, according to first in first out mechanism from pipelining-stage write out data and
The control signal of these data；
When writing out enable signal and being effective, if it is invalid to write out ready signal, then write out data failure.When writing
Go out to enable signal effectively and write out ready signal effective time, then write out from pipelining-stage according to first in first out mechanism
Data and the control signal of these data.
Due to the state of pipelining-stage be not only non-NULL but also non-full time, the write that can carry out data can also be carried out
Writing out of data, so it will be understood by those skilled in the art that and there is no between step S402 and S403 admittedly
Fixed priority execution sequence.
If S404 write to enable signal effective, then according to first in first out mechanism to pipelining-stage write data with
And the control signal of these data；
In step, pipelining-stage is empty, can equivalence be interpreted as a kind of special non-full state, then write
Ready signal is effective, if now write enables signal also effectively, then according to first in first out mechanism to pipelining-stage
Write data and the control signal of these data.If write enables invalidating signal, then write data failure.
The state of pipelining-stage is empty, then can not write out data, can only write data, so writing out enable letter
Number invalid.
If S405 to write out ready signal effective, then according to first in first out mechanism from pipelining-stage write out data with
And the control signal of these data.
According to the logic set, the state of pipelining-stage is for (regarding as a kind of non-time full in the present embodiment
Dummy status), write out enable signal effective, also effective, then according to first in first out if the write out ready signal
Mechanism writes out the control signal of data and these data from pipelining-stage.
The present embodiment is specifically as follows the pipelining-stage a kind of feasible method of offer realizing storage depth more than 1.
Preferably, on the basis of described embodiment of the method 2, the bit arranging two two identifies
Two bits such as, are designated as the first dibit position and the second dibit position by the state of pipelining-stage, and two
The numerical value of bit includes " 00,01,10,11 " four kinds, specifically in practical operation, pipelining-stage state
Judge process can be in the following way:
Judge that the low level numerical value in the first dibit and the second dibit is the most equal；If low level numerical value not phase
Deng, then judge that the state of pipelining-stage is as not only non-NULL but also non-full；If low level numerical value is equal, then judge first pair
High-order numerical value in bit and the second dibit is the most equal；If high-order numerical value is equal, then judge pipelining-stage
State be empty；If high-order numerical value is unequal, then judge that the state of pipelining-stage is as full.
In order to the state of real-time instruction pipelining-stage, when pipelining-stage writes and writes out data, instruction
Position to be also changed accordingly, concrete in the following way: write enable signal with write prepare letter
Time number all effectively, the first dibit bit value adds 1；Write out enable signal to write out ready signal with data and all have
During effect, the second dibit bit value adds 1.
Corresponding, the embodiment of the present invention also provides for a kind of pipelining-stage embodiment 2, as it is shown in figure 5, wherein,
In described pipelining-stage, the storage depth of data is more than 1；Setting the state of pipelining-stage as time non-full, write prepares
Signal is effective；When pipelining-stage is non-NULL, write out enable signal effective；The most described pipelining-stage includes:
Second judge module 51, for judging the state of pipelining-stage；
3rd writing module 52, the state for pipelining-stage be not only non-NULL but also non-full time, if write enables letter
Number effectively, then according to first in first out mechanism to pipelining-stage write data and the control signal of these data；
Second writes out module 53, the state for pipelining-stage be not only non-NULL but also non-full time, if writing out preparation letter
Number effectively, the control signal of data and these data is write out from pipelining-stage according to first in first out mechanism；
4th writing module 54, for pipelining-stage be empty time, if write to enable signal effective, according to advanced person
First go out mechanism to pipelining-stage write data and the control signal of these data；
3rd writes out module 55, for pipelining-stage for time full, if it is effective to write out ready signal, according to advanced person
First go out mechanism and write out the control signal of data and these data from pipelining-stage.
Preferably, in the present embodiment, the second judge module can come by arranging the bit of two two
Determine the state of pipelining-stage, such as, two bits be designated as the first dibit position and the second dibit position,
The numerical value of dibit includes " 00,01,10,11 " four kinds, specifically in practical operation, it is judged that process can
With in the following way:
Judge that the low level numerical value in the first dibit and the second dibit is the most equal；If low level numerical value not phase
Deng, then the state of pipelining-stage is not only non-NULL but also non-full；If low level numerical value is equal, then judge the first dibit
The most equal with the high-order numerical value in the second dibit；If high-order numerical value is equal, then the state of pipelining-stage is
Empty；If high-order numerical value is unequal, then the state of pipelining-stage is full.
For the change of instruction pipelining-stage that can be real-time, the state of indicating bit also to write along with pipelining-stage
Data or write out data variation, particularly as follows: write enable signal with write ready signal all effectively time, the
A pair of bit numerical value adds 1；Write out enable signal and data write out ready signal all effectively time, second pair of ratio
Special bit value adds 1.With reference to previous example, in this example with the first dibit position as wp2, the second dibit position
State for rp2 mark pipelining-stage.In the present embodiment, the work-based logic of pipelining-stage is as follows:
Table 5 pipelining-stage work-based logic explanation
The sequential chart that the logic of table 5 description is corresponding is referred to a kind of example that Fig. 6 provides.Corresponding is true
Shown in value table reference table 6:
Truth table corresponding to logic that table 6 table 5 describes
The embodiment of the present invention also provides for a kind of streamline embodiment, including multiple such as above-mentioned pipelining-stage embodiment 1
Described pipelining-stage and/or multiple pipelining-stage as described in above-mentioned pipelining-stage embodiment 2.Previous flowing water cascade
Connecing at least one next stage pipelining-stage, previous stage pipelining-stage selects next stage pipelining-stage by gating signal；
Connection between the pipelining-stage of adjacent two-stage is as follows:
The enable signal that writes out of previous stage pipelining-stage inputs to rear stage pipelining-stage, as next stage pipelining-stage
Write enable signal；Previous stage pipelining-stage write out control signal input to rear stage pipelining-stage, as
The write control signal of rear stage pipelining-stage；The data that previous stage pipelining-stage writes out input to rear stage flowing water
Level, as the input data of rear stage pipelining-stage；The write ready signal input of rear stage pipelining-stage is to front
One-level pipelining-stage, writes out ready signal as previous stage pipelining-stage.
Streamline can be a unidirectional strip system, as it is shown in fig. 7, the n-th gppipe (stream
Water level) outfan and (n+1)th gppipe input be connected, it is possible to complete the cascade of pipelining-stage,
Form complete streamline.Streamline can also be a network morphology, and such as, previous pipelining-stage connects
During multiple next stage pipelining-stage, wherein, previous stage pipelining-stage (such as can be by opening by gating signal
Close the gating realizing signal) select next stage pipelining-stage.Owing to the control signal of corresponding data carrying
The mark of the next stage pipelining-stage of data flow, and the sequence identification of data, though current flowing water cascade
Connecing multiple next stage pipelining-stage, data also can be passed by current pipelining-stage according to the control signal information in data
It is passed in correct pipelining-stage.
As shown in Figure 8, pipelining-stage 1 (being designated as nod1) and pipelining-stage 2 (being designated as nod2) and pipelining-stage 3
(being designated as nod3) constitutes a network, and the upper level of pipelining-stage 1 (being designated as nod1) has a pipelined data
D0-> d1-> d2-> d3 flows to nod1.Nod1 assigns to nod2 according to the control signal in data just d0, d2,
D1, d3 assign to the data of nod3, nod2 and eventually flow into nod3, nod3 by data according to d0-> d1-> d2-> d3
Order flow to subordinate.
The technical scheme that the present embodiment provides, the flowing water that described streamline obtains based on said method embodiment
Level cascade forms, and the connected mode of every one-level pipelining-stage is similar to, except the data of rear stage pipelining-stage write standard
Standby signal input is to previous stage pipelining-stage, outside writing out ready signal as the data of previous stage pipelining-stage,
The output class signal only needing prime pipelining-stage is connected to subordinate's pipelining-stage as input signal, for pipelining-stage level
Connection provides a kind of general connected mode.In the manner described above, can be using each pipelining-stage as one
Individual independent module, carries out cutting and the insertion of pipelining-stage, connects according to unified interface connected mode
, it is achieved that the modularized design of streamline so that the design of streamline is the most flexible.
Streamline described in above-described embodiment, dnrdy can be connected in series in uprdy, and the direction of sequential series connection is
The opposite direction of flowing water, if pipelining-stage number is a lot, flowing water is long, it may appear that timing (sequential) is inadequate
Situation.In order to optimize the sequential of streamline further, it is preferred that can be further by part pipelining-stage
Write ready signal isolated by depositor inside pipelining-stage with writing out ready signal, by data time
Sequence becomes from being input to output: from being input to depositor, from depositor to depositor, from depositor to defeated
Go out.Realize the optimization of sequential, and do not change while Improving Working Timing streamline port design and
Internal work-based logic.
It should be noted that designer can randomly choose part according to actual needs when practical operation
The write ready signal of pipelining-stage is isolated by depositor inside pipelining-stage with writing out ready signal, as long as
Final streamline can reach the requirement of sequential.
The above, above example only in order to technical scheme to be described, is not intended to limit；
Although being described in detail the present invention with reference to previous embodiment, those of ordinary skill in the art should
Work as understanding: the technical scheme described in foregoing embodiments still can be modified by it, or to it
Middle part technical characteristic carries out equivalent；And these amendments or replacement, do not make appropriate technical solution
Essence depart from various embodiments of the present invention technical scheme spirit and scope.
Claims (9)
1. the implementation method of a pipelining-stage, it is characterised in that the storage depth of data in described pipelining-stage
It is 1；The state of pipelining-stage for time full, writes out enable signal with to write out ready signal effective；The shape of pipelining-stage
When state is empty, write ready signal is effective；The most described method includes:
Judging the state of pipelining-stage, if it is empty, and write enables signal effectively, then write data and be somebody's turn to do
The control signal of data；
If full, and it is effective to write out ready signal, then write ready signal is effective, writes out data and is somebody's turn to do
The control signal of data；If it is effective that write enables signal, then write data and the control signal of these data.
Method the most according to claim 1, it is characterised in that the state bag of described judgement pipelining-stage
Include:
Judge that the numerical value being used for the first bit and the second bit indicating pipelining-stage state is the most equal,
If equal, then pipelining-stage state is empty, otherwise is full；
Or, when the numerical value of the first bit and the second bit is unequal, pipelining-stage state is empty, otherwise
It is full；Wherein, the first bit enables signal and upset when writing ready signal all effectively in write；The
Two bits write out enable signal and write out ready signal all effectively time upset.
3. the implementation method of a pipelining-stage, it is characterised in that the storage depth of data in described pipelining-stage
More than 1；When the state of pipelining-stage is non-full, write ready signal is effective；When pipelining-stage is non-NULL, write out
Enable signal is effective；The most described method includes:
Judging the state of pipelining-stage, if the state of pipelining-stage is not only non-NULL but also non-full, and write enables signal
Effectively, then data and the control signal of these data are write according to first in first out mechanism to pipelining-stage；If writing
Go out ready signal effective, then write out the control of data and these data according to first in first out mechanism from pipelining-stage
Signal；
If it is empty, and write enables signal effectively, then according to first in first out mechanism to pipelining-stage write data
And the control signal of these data；
If full, and it is effective to write out ready signal, then write out data according to first in first out mechanism from pipelining-stage
And the control signal of these data.
Method the most according to claim 3, it is characterised in that the state bag of described judgement pipelining-stage
Include:
Judge to indicate the whether phase of the low level numerical value in the first dibit of pipelining-stage state and the second dibit
Deng；
If low level numerical value is unequal, then the state of pipelining-stage is not only non-NULL but also non-full；If low level numerical value is equal,
Then judge that the high-order numerical value in the first dibit and the second dibit is the most equal；
If high-order numerical value is equal, then pipelining-stage is empty；If high-order numerical value is unequal, then pipelining-stage is full；
Wherein, the first dibit numerical value when write enables signal and write ready signal is all effective adds 1；Second pair
Bit write out enable signal and data write out ready signal all effectively time numerical value add 1.
5. a pipelining-stage, it is characterised in that including: in described pipelining-stage, the storage depth of data is 1；
The state of pipelining-stage, for time full, writes out enable signal effective；Pipelining-stage is full for empty or pipelining-stage and writes out
When ready signal is effective, write ready signal is effective；The most described pipelining-stage includes:
First judge module, for judging the state of pipelining-stage；
First writing module, when the first judge module judges pipelining-stage state as sky, if write enables
Signal is effective, write data and the control signal of these data；
First writes out module, for the first judge module judge pipelining-stage as time full, if writing out ready signal
Effectively, the control signal of data and these data is write out；
First determines module, judges that pipelining-stage, as time full, determines that write prepares letter for the first judge module
Number effectively；
Second writing module, for first determine module judge write enable signal effective time, if data are write
Go out successfully, write data and the control signal of these data.
6. a pipelining-stage, it is characterised in that in described pipelining-stage, the storage depth of data is more than 1；Stream
When the state of water level is non-full, write ready signal is effective；When pipelining-stage is non-NULL, write out enable signal
Effectively；The most described pipelining-stage includes:
Second judge module, for judging the state of pipelining-stage；
3rd writing module, the state for pipelining-stage be not only non-NULL but also non-full time, if write enables signal
Effectively, then data and the control signal of these data are write according to first in first out mechanism to pipelining-stage；
Second writes out module, the state for pipelining-stage be not only non-NULL but also non-full time, if writing out ready signal
Effectively, write out the control signal of data and these data from pipelining-stage according to first in first out mechanism；
4th writing module, for pipelining-stage be empty time, if write to enable signal effective, according to advanced person first
Go out mechanism to pipelining-stage write data and the control signal of these data；
3rd writes out module, for pipelining-stage for time full, if it is effective to write out ready signal, according to advanced person first
Go out mechanism and write out the control signal of data and these data from pipelining-stage.
7. a streamline, it is characterised in that described streamline includes: the most
Individual pipelining-stage and/or multiple pipelining-stage as claimed in claim 6；
Previous pipelining-stage connects at least one next stage pipelining-stage, and previous stage pipelining-stage is selected by gating signal
Select next stage pipelining-stage；
Connection between the pipelining-stage of adjacent two-stage is as follows: the enable signal that writes out of previous stage pipelining-stage inputs
To rear stage pipelining-stage, the write as next stage pipelining-stage enables signal；Writing out of previous stage pipelining-stage
Control signal inputs to rear stage pipelining-stage, as the write control signal of rear stage pipelining-stage；Previous stage
The data that pipelining-stage writes out input to rear stage pipelining-stage, as the input data of rear stage pipelining-stage；After
The write ready signal of one-level pipelining-stage inputs to previous stage pipelining-stage, as writing out of previous stage pipelining-stage
Ready signal.
Streamline the most according to claim 7, it is characterised in that when previous stage pipelining-stage connects many
During individual next stage pipelining-stage, the control signal of corresponding data is carried the next stage pipelining-stage of data flow
Mark, and the sequence identification of data.
Streamline the most according to claim 7, it is characterised in that the write of part pipelining-stage prepares
Signal is isolated by depositor inside pipelining-stage with writing out ready signal, to reach streamline to sequential
Requirement.
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| US5920899A (en) * | 1997-09-02 | 1999-07-06 | Acorn Networks, Inc. | Asynchronous pipeline whose stages generate output request before latching data |
| CN1540494A (en) * | 2003-04-26 | 2004-10-27 | 华为技术有限公司 | Threading metod for processing data packets based on FIFO queue and device of |
| CN1731529A (en) * | 2005-07-13 | 2006-02-08 | 北京中星微电子有限公司 | FIFO data buffering method and full up space accessing FIFO memory |
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