CN106257655A - A kind of power device packaging structure - Google Patents
A kind of power device packaging structure Download PDFInfo
- Publication number
- CN106257655A CN106257655A CN201610712108.2A CN201610712108A CN106257655A CN 106257655 A CN106257655 A CN 106257655A CN 201610712108 A CN201610712108 A CN 201610712108A CN 106257655 A CN106257655 A CN 106257655A
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- China
- Prior art keywords
- pin
- source
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- substrate
- prong
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The present invention relates to a kind of power device packaging structure.Power device packaging structure of the present invention has 4 external pins, the external pin newly increased drives source electrode as grid, bypass the stray inductance of main power source source lead and pin, thus the impact of grid drive circuit will be eliminated by the source inductance of main power source, the pressure drop that source inductance causes no longer affects gate source voltage, thus the grid reducing device drive loss；On the other hand, not having big electric current to flow through due on the external pin that newly increases, almost without pressure drop on its wire and pin, thus well chip is clamped at 0V, this makes the running voltage of device be substantially reduced, thus reduces break-over of device loss；Additionally send out the present invention also by increasing by the first pin, the width of the second pin, and first, the distance between two pins, reduce the purpose of electromagnetic interference between high voltage power device pin, thus meet the encapsulation requirement of High voltage power device.
Description
Technical field
The invention belongs to semiconductor device packaging technique field, be specifically related to a kind of power device packaging structure.
Background technology
Along with the development of technology, increasing electronic equipment develops towards high efficiency, high reliability, low-power consumption direction,
Power device, as the main devices of electronic equipment, is also being devoted to high reliability, high efficiency, low-power consumption.Wherein, power
One of direction of device low-power consumption is to reduce the switching loss brought due to chip package.For merits such as DC/DC power supply, crystal oscillators
The power device that loss-rate is bigger, owing to the power density of encapsulating structure is more and more higher, the power problems brought due to encapsulation is got over
Coming the most prominent, the switching loss the most how as far as possible reducing power device under conditions of guaranteed output device high reliability becomes
One of power device package design technical issues that need to address.
For single-chip power device, at present frequently with packing forms as shown in Figure 1, conventional plastic encapsulation is main by pacifying
Dress screw or the fixing hole 9 of fin, the plastic case 8 being made up of epoxide resin material, the outer pin 101,121 of chip,
131 and the heat-radiating substrate 10 at the back side form, but along with power device chip is pressure and power increases, it is desirable to can hold between pin
Be subject to is pressure more and more higher, owing to power device is mainly used in DC/DC and inverter, device need constantly to open and
Turning off, under high-power, the power problems brought due to chip package is more and more significant, becomes restriction power device low-power consumption
Development a key factor, three traditional pinned encapsulating structures due to power supply and switch source electrode share a stitch
(as shown in Figure 2), due to the interaction between loop, the big electric current that main power source source electrode flows through can affect grid drive circuit, increases
Grid drive loss；The electric current flow through additionally, due to main power source is relatively big, and the stray inductance on wire 12 and pin 121 is under big electric current
Produce bigger pressure drop, and chip source electrode 11 be clamped at a higher voltage, cause the running voltage of device to be greatly increased,
Thus add break-over of device loss.
Summary of the invention
The purpose of the present invention, it is simply that for the problems referred to above, it is proposed that the encapsulating structure of a kind of four pins, meets low simultaneously
Power consumption, high efficiency, the requirement of high reliability power device packaging structure.
The technical scheme is that, a kind of power device packaging structure, including substrate 10, described substrate 10 upper end center
Position is provided with fixing hole 9, and in the middle part of substrate 10, center position has chip 11, described chip 11 by have conductive characteristic and
The binding agent of heat conductivity is fixing on the substrate 10；Side, described substrate 10 lower end has the first pin 101, described first pin
101 are structure as a whole with substrate 10；From the opposite side of the first pin 101 to substrate 10 lower end, there is the second pin the most successively
121, the 4th pin 141 and three-prong 131, described second pin 121 passes through the first wire 12 by the output signal of chip 11
Drawing from the second pin 121, described three-prong 131 passes through the second wire 13 by the output signal of chip 11 from three-prong
131 draw；The output signal of chip 11 is drawn from the 4th pin 141 by described 4th pin 141 by privates 14；Described
Three-prong 131 is for bypassing the stray inductance of main power source source lead and pin, and grid are driven by the source inductance eliminating main power source
The impact on galvanic electricity road, the pressure drop that source inductance causes no longer affects gate source voltage, thus the grid reducing device drive loss；Described
Three-prong 131 is additionally operable to chip 11 is clamped at 0V so that the running voltage of device reduces；Described first pin 101 and
Spacing between two pins 121 is more than the spacing between the 4th pin 141 and three-prong 131.
Beneficial effects of the present invention is, power device packaging structure provided by the present invention has 4 external pins, newly-increased
The external pin added drives source electrode as grid, has bypassed the stray inductance of main power source source lead and pin, thus main electricity
The impact of grid drive circuit will be eliminated by the source inductance in source, and the pressure drop that source inductance causes no longer affects gate source voltage, thus
The grid reducing device drive loss；On the other hand, big electric current is not had to flow through, at its wire due on the external pin that newly increases
With on pin almost without pressure drop, thus well chip 11 is clamped at 0V, this makes the running voltage of device be substantially reduced,
Thus reduce break-over of device loss；Additionally the present invention is also by increasing by the first pin, the width of the second pin, and first,
Distance between two pins, reduces the purpose of electromagnetic interference between high voltage power device pin, thus meets the big merit of high pressure
The encapsulation requirement of rate device；By reducing three-prong, the width of the 4th pin, and the 3rd, the distance between four pins, reach
To the purpose reducing power device package area.
Accompanying drawing explanation
Fig. 1 is that tradition TO220 encapsulates schematic diagram；
Fig. 2 is the traditional TO2203 pin package application circuit model simplified；
Fig. 2 is the structural representation of lead frame of the present invention；
Fig. 3 is the structural representation of the present invention；
Fig. 4 is the present invention 4 pin package application circuit model simplified；
Fig. 5 is the present invention 4 pin package schematic diagram；
Fig. 6 is the sectional view in A-A ' direction along Fig. 5.
Detailed description of the invention
Below in conjunction with the accompanying drawings the detailed description of the invention of the present invention is described
In order to make technical problem solved by the invention, technical scheme and beneficial effect clearer, below in conjunction with
TO220 encapsulating structure figure, the present invention is described in more detail.Should be appreciated that described herein be embodied as only in order to
Explain that this reality is invented, be not intended to limit the present invention.
A kind of high voltage power device encapsulating structure, as it is shown on figure 3, include:
1, substrate 10, substrate 10 is provided with the first pin 101；
2, chip 11, it is connected on described substrate 10 center with binding agent, described binding agent has conductive characteristic, by core
Sheet output signal is drawn from the first pin 101；
3, the first wire 12, the output signal of chip 11 is drawn from the second pin 121；
4, the second wire 13, the output signal of chip 11 is drawn from three-prong 131；
5, privates 14, the output signal of chip 11 is drawn from the 4th pin 141；
6, last molding molding (as shown in Figure 5 and Figure 6)；
7, described novel TO220 encapsulating structure has 4 external pins, and the three-prong 131 newly increased drives as grid
Source electrode, bypassed main power source connect source inductance (as shown in Figure 4), the source inductance of the main power source shadow to grid drive circuit
Ringing and will be eliminated, the pressure drop that source inductance causes no longer affects gate source voltage, thus the grid reducing device drive loss；Its feature
Being, the three-prong 131 newly increased does not has big electric current to flow through, almost without pressure drop on its wire and pin, thus very well
Chip 11 is clamped at 0V by ground, and this makes the running voltage of device be substantially reduced, thus reduces break-over of device loss；Described
One pin 101, the distance between the second supervisor 121 is bigger, in order to meet the encapsulation of high Breakdown Voltage Power device；Described chip
Three-prong 131, the spacing of the 4th pin 141 is less, and pin narrower width, reaches to reduce the mesh of power device package area
's；
8, described chip 11 can be metal-oxide-semiconductor, it is also possible to being IGBT pipe, MCT manages, power diode, IGCT constant power
Device.
Power device packaging structure of the present invention has 4 external pins, and the external pin newly increased drives as grid
Source electrode, has bypassed the stray inductance of main power source source lead and pin, thus the source inductance of main power source is to grid drive circuit
Impact will be eliminated, and the pressure drop that source inductance causes no longer affects gate source voltage, thus the grid reducing device drive loss；Another
Aspect, does not has big electric current to flow through, almost without pressure drop on its wire and pin, thus very due on the external pin that newly increases
Well chip 11 being clamped at 0V, this makes the running voltage of device be substantially reduced, thus reduces break-over of device loss；Additionally
Send out the present invention also by increasing by the first pin, the width of the second pin, and first, the distance between two pins, reduce
The purpose of electromagnetic interference between high voltage power device pin, thus meet the encapsulation requirement of High voltage power device；By reducing
Three-prong, the width of the 4th pin, and the 3rd, the distance between four pins, reach to reduce power device package area
Purpose；Thus realize small size simultaneously, high reliability power device package.
The above four pin configuration based on TO220 encapsulation is intended merely to the brightest present invention, and need not
To limit the present invention, all any amendment, equivalent and improvement etc. made within the spirit and principles in the present invention, all should wrap
Within being contained in protection scope of the present invention.
Claims (1)
1. a power device packaging structure, including substrate (10), described substrate (10) upper end center position is provided with fixing hole
(9), substrate (10) middle part center position has chip (11), and described chip (11) is by having conductive characteristic and heat conductivity
Binding agent is fixed on substrate (10)；Described substrate (10) side, lower end has the first pin (101), described first pin
(101) it is structure as a whole with substrate (10)；From the first pin (101) to the opposite side of substrate (10) lower end, have the most successively
Two pins (121), the 4th pin (141) and three-prong (131), described second pin (121) passes through the first wire (12) will
The output signal of chip (11) is drawn from the second pin (121), and described three-prong (131) passes through the second wire (13) by chip
(11) output signal is drawn from three-prong (131)；Described 4th pin (141) passes through privates (14) by chip (11)
Output signal draw from the 4th pin (141)；Described three-prong (131) is for bypassing main power source source lead and pin
Stray inductance, the impact on grid drive circuit of the source inductance of elimination main power source, the pressure drop that source inductance causes no longer affects grid source
Voltage, thus the grid reducing device drive loss；Described three-prong (131) is additionally operable to chip (11) is clamped at 0V, makes
The running voltage obtaining device reduces；Spacing between described first pin (101) and the second pin (121) is more than the 4th pin
(141) spacing and between three-prong (131).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610712108.2A CN106257655A (en) | 2016-08-23 | 2016-08-23 | A kind of power device packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610712108.2A CN106257655A (en) | 2016-08-23 | 2016-08-23 | A kind of power device packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106257655A true CN106257655A (en) | 2016-12-28 |
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ID=57714221
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610712108.2A Pending CN106257655A (en) | 2016-08-23 | 2016-08-23 | A kind of power device packaging structure |
Country Status (1)
| Country | Link |
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| CN (1) | CN106257655A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108233897A (en) * | 2018-02-05 | 2018-06-29 | 电子科技大学 | A kind of pulse forming network based on cathode short circuit grid-controlled transistor |
| CN110010577A (en) * | 2019-04-08 | 2019-07-12 | 深圳市鹏源电子有限公司 | Direct insertion power device, semiconductor subassembly, In-wheel motor driving device or bus drive and new-energy automobile |
| CN110149108A (en) * | 2019-06-05 | 2019-08-20 | 浙江明德微电子股份有限公司 | A kind of composite S J-MOS pipe of low-power consumption and preparation method thereof |
| WO2020206867A1 (en) * | 2019-04-08 | 2020-10-15 | 深圳市鹏源电子有限公司 | In-line power device, semiconductor assembly, in-wheel motor driver or automobile driver, and new energy vehicle |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070064313A1 (en) * | 2005-09-21 | 2007-03-22 | Kazuyuki Hosokawa | Zoom optical system and image pickup apparatus provided with the same |
| CN205050829U (en) * | 2015-10-27 | 2016-02-24 | 南京晟芯半导体有限公司 | High power packaging structure who can be used to surface mounting |
-
2016
- 2016-08-23 CN CN201610712108.2A patent/CN106257655A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070064313A1 (en) * | 2005-09-21 | 2007-03-22 | Kazuyuki Hosokawa | Zoom optical system and image pickup apparatus provided with the same |
| CN205050829U (en) * | 2015-10-27 | 2016-02-24 | 南京晟芯半导体有限公司 | High power packaging structure who can be used to surface mounting |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108233897A (en) * | 2018-02-05 | 2018-06-29 | 电子科技大学 | A kind of pulse forming network based on cathode short circuit grid-controlled transistor |
| CN110010577A (en) * | 2019-04-08 | 2019-07-12 | 深圳市鹏源电子有限公司 | Direct insertion power device, semiconductor subassembly, In-wheel motor driving device or bus drive and new-energy automobile |
| WO2020206867A1 (en) * | 2019-04-08 | 2020-10-15 | 深圳市鹏源电子有限公司 | In-line power device, semiconductor assembly, in-wheel motor driver or automobile driver, and new energy vehicle |
| CN110149108A (en) * | 2019-06-05 | 2019-08-20 | 浙江明德微电子股份有限公司 | A kind of composite S J-MOS pipe of low-power consumption and preparation method thereof |
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| PB01 | Publication | ||
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161228 |
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| RJ01 | Rejection of invention patent application after publication |