CN106257622A - Semiconductor element and manufacture method thereof - Google Patents
Semiconductor element and manufacture method thereof Download PDFInfo
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- CN106257622A CN106257622A CN201510332823.9A CN201510332823A CN106257622A CN 106257622 A CN106257622 A CN 106257622A CN 201510332823 A CN201510332823 A CN 201510332823A CN 106257622 A CN106257622 A CN 106257622A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 238000000034 method Methods 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000010410 layer Substances 0.000 claims abstract description 165
- 238000006396 nitration reaction Methods 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 238000005530 etching Methods 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims abstract description 22
- 239000011241 protective layer Substances 0.000 claims abstract description 21
- 230000003647 oxidation Effects 0.000 claims description 14
- 238000007254 oxidation reaction Methods 0.000 claims description 14
- 125000006850 spacer group Chemical group 0.000 claims description 14
- 239000011435 rock Substances 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 9
- -1 spacer nitride Chemical class 0.000 claims description 9
- 229910018503 SF6 Inorganic materials 0.000 claims description 7
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 7
- 229960000909 sulfur hexafluoride Drugs 0.000 claims description 7
- BLIQUJLAJXRXSG-UHFFFAOYSA-N 1-benzyl-3-(trifluoromethyl)pyrrolidin-1-ium-3-carboxylate Chemical compound C1C(C(=O)O)(C(F)(F)F)CCN1CC1=CC=CC=C1 BLIQUJLAJXRXSG-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims 2
- 238000002955 isolation Methods 0.000 description 10
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 5
- 230000006378 damage Effects 0.000 description 5
- 229910052717 sulfur Inorganic materials 0.000 description 5
- 239000011593 sulfur Substances 0.000 description 5
- IGELFKKMDLGCJO-UHFFFAOYSA-N xenon difluoride Chemical compound F[Xe]F IGELFKKMDLGCJO-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 229910020776 SixNy Inorganic materials 0.000 description 1
- JDZCKJOXGCMJGS-UHFFFAOYSA-N [Li].[S] Chemical compound [Li].[S] JDZCKJOXGCMJGS-UHFFFAOYSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- PQIOSYKVBBWRRI-UHFFFAOYSA-N methylphosphonyl difluoride Chemical group CP(F)(F)=O PQIOSYKVBBWRRI-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention proposes the manufacture method of a kind of semiconductor element.The manufacture method of semiconductor element includes: provide substrate；Semiconductor stack stack structure is formed on substrate；Forming at least some of of stacking cover layer on semiconductor stack stack structure, wherein stack cover layer includes nitration case at least partially；Remove a part for nitration case；Complete to stack all parts of cover layer；Forming protective layer, and etch protection layer on stacking cover layer, to form at least one perforate, wherein nitration case is not exposed by perforate；And it is passed through an etching material from perforate, to etch substrate.The present invention separately proposes a kind of semiconductor element using said method to be formed.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, particularly relate to one and there is heap
Superimposition cap rock, and nitration case can be made to be protected from etching semiconductor element and the system thereof of material damage
Make method.
Background technology
Refer to Figure 1A-1B, the flow process section view of the manufacture method of its existing semiconductor element of display
Schematic diagram.As shown in Figure 1A, in the manufacture method of the semiconductor element 10 of prior art, base
Semiconductor stack stack structure 19 it is formed with on plate 11.On semiconductor stack stack structure 19, form one
Stacking cover layer 15.Semiconductor stack stack structure 19 includes grid structure 13 and a wall
14.Wherein, the generation type of semiconductor stack stack structure 19 is: form shallow trench on substrate 11
Isolation (shallow trench isolation, STI) structure 12, and formed on this sti structure 12
Grid structure 13 and wall 14.Wherein, regard it according to the sectional view of Figure 1A, from bottom to top,
Grid structure 13 includes: first grid layer 131, gate nitridation dielectric layer 132, grid oxygen
Change dielectric layer 133 and second grid layer 134.Wall 14 include spacer oxide layer 14b and
Spacer nitride layer 14a.Sectional view according to Figure 1A regards it, from bottom to top, stacks cover layer 15
Include: first covers oxide layer 151, nitration case 152 and the second covering oxide layer 153.Heap
Being formed with a protective layer 16 on superimposition cap rock 15, wherein this protective layer 16 is after overetch, shape
Cheng Youyi perforate 161.
Then, as shown in Figure 1B, in the manufacture method of the semiconductor element of prior art, when
During substrate 11 to be etched, an etching material, such as sulfur hexafluoride (SF can be passed through from perforate 1616)。
Unfortunately, due to sulfur hexafluoride (SF6) nitration case 152 stacking cover layer 15 can be attacked, such as figure
In 1B shown in arrow, this will make nitration case 152 impaired, affect the structure of semiconductor element 10.
In view of this, the present invention, i.e. for above-mentioned the deficiencies in the prior art, proposes one and has heap
Superimposition cap rock, and nitration case can be made to be protected from etching the system of the semiconductor element of the destruction of material
Make method.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art and defect, it is provided that a kind of quasiconductor
Element and manufacture method thereof, this semiconductor element has stacking cover layer, and nitration case can be made to exempt from
In being destroyed by etching material.
For reaching above-mentioned purpose, a wherein viewpoint speech, the invention provides a kind of semiconductor element
Manufacture method.It comprises the following steps.First, it is provided that a substrate.Then, in this substrate
Upper formation semiconductor stacked structure.Then, on this semiconductor stack stack structure, a stacking is formed
Cover layer at least some of, this of wherein this stacking cover layer includes a nitridation at least partially
Layer.Then, a part for this nitration case is removed.Then, all of this stacking cover layer are completed
Part.Then, on this stacking cover layer, form a protective layer, and etch this protective layer, with
Forming at least one perforate, wherein this nitration case is not exposed by this perforate.Then, from this perforate
It is passed through an etching material, to etch this substrate.
Preferably implement in kenel in one, on this substrate, form this semiconductor stack stack structure
Method step comprises the following steps.First, on this substrate, an insulation structure of shallow groove is formed.
Then, on this insulation structure of shallow groove, a grid structure and a wall are formed.
Preferably implementing in kenel in one, the method step forming this grid structure includes following
Step.First, a first grid layer is formed on this insulation structure of shallow groove.Then, formed
One gate nitridation dielectric layer is on this first grid layer.Then, a gate oxidation dielectric layer is formed
On this gate nitridation dielectric layer.Then, a second grid layer is formed in this gate oxidation dielectric
On layer.
Preferably implementing in kenel in one, the method step forming this wall includes following step
Suddenly.First, a spacer oxide layer is formed outside the sidewall of this grid structure.Then, one is formed
Spacer nitride layer is outside the sidewall of this spacer oxide layer.
Preferably implement in kenel in one, on this semiconductor stack stack structure, form this heap superimposition
At least one of method step of cap rock comprises the following steps.First, one first covering is formed
Oxide layer is on this semiconductor stack stack structure.Then, a nitration case is formed in this first covering oxygen
Change on layer.
Preferably implement in kenel in one, the method completing all parts of this stacking cover layer
Step includes forming this second covering oxide layer on the remainder of this nitration case.
Preferably implementing in kenel in one, this etching material includes sulfur hexafluoride (SF6) or difluoro
Change xenon (XeF2)。
For reaching above-mentioned purpose, another viewpoint is sayed, the invention provides a kind of semiconductor element
Manufacture method.It comprises the following steps.First, it is provided that a substrate.Then, on this substrate
Form semiconductor stacked structure.Then, on this semiconductor stack stack structure, a pile superimposition is formed
Cap rock, wherein this stacking cover layer includes a nitration case.Then, shape on this stacking cover layer
Becoming a protective layer, and etch this protective layer, to form at least one perforate, wherein this perforate exposes
Go out this at least part of nitration case.Then, the sidewall in this perforate forms a protection oxide layer, with
Cover this at least part of nitration case.Then, it is passed through an etching material from this perforate, should with etching
Substrate.
Preferably implement in kenel in one, on this semiconductor stack stack structure, form this heap superimposition
The method step of cap rock comprises the following steps.First, one first covering oxide layer is formed in this partly
In conductor stack structure.Then, this nitration case is formed in this first covering oxide layer.Then,
Form one second covering oxide layer on this nitration case.
For reaching above-mentioned purpose, another viewpoint is sayed, the invention provides a kind of semiconductor element.
It includes a substrate, semiconductor stacked structure, a pile superimposition cap rock and a protective layer.Half
Conductor stack structure is configured on this substrate.Stacking cover layer is covered in this semiconductor stack stack structure
On, wherein this stacking cover layer is sequentially stacked with one first covering oxide layer, a nitration case and
Second covers oxide layer.Protective layer is configured on this stacking cover layer and has at least one perforate,
Wherein this perforate exposes part this second covering oxide layer of this first covering oxide layer and part,
And this nitration case is not exposed by this perforate.
Below by specific embodiment elaborate, when being easier to understand the purpose of the present invention, skill
Art content, feature and the effect reached thereof.
Accompanying drawing explanation
Figure 1A-1B shows the flow process cross-sectional schematic of the manufacture method of existing semiconductor element；
The flow process cross-sectional schematic of first embodiment of Fig. 2 A-2F display present invention；
The flow process cross-sectional schematic of second embodiment of Fig. 3 A-3E display present invention.
Symbol description in figure
(prior art)
10 existing semiconductor elements
11 existing substrates
12 existing fleet plough groove isolation structures
13 existing grid structures
131 existing first grid layers
132 existing gate nitridation dielectric layers
133 existing gate oxidation dielectric layers
134 existing second grid layers
14 existing walls
14a existing spacer nitride layer
The existing spacer oxide layer of 14b
15 existing stacking cover layers
151 existing first cover oxide layer
152 existing nitration cases
153 existing second cover oxide layer
16 existing protective layers
161 existing perforates
19 existing semiconductor stack stack structures
The existing lines of AA '
(present invention)
20,30 semiconductor element
21 substrates
22 fleet plough groove isolation structures
23 grid structures
231 first grid layers
232 gate nitridation dielectric layers
233 gate oxidation dielectric layers
234 second grid layers
24 walls
24a spacer nitride layer
24b spacer oxide layer
25 stacking cover layers
251 first cover oxide layer
252 nitration cases
253 second cover oxide layer
26 protective layers
261 perforates
272 protection oxide layers
29 semiconductor stack stack structures
BB ' lines
Detailed description of the invention
For the present invention aforementioned and other technology contents, feature and effect, coordinate ginseng following
Examine in the detailed description of a graphic preferred embodiment, can clearly present.In the present invention
Graphic all belong to signal, be mostly intended to represent the function relation between each device and each element,
Then and draw not according to ratio with width as shape, thickness.
Refer to Fig. 2 A-2F, the flow process section view signal of first embodiment of its display present invention
Figure.It should be noted that the present embodiment be intended to illustrate the present invention principal character, therefore,
Such as micro-photographing process step (figure required in the manufacture method of the semiconductor element of general standard
Do not show) with ion implantation manufacture process step (not shown) or other steps unrelated with the emphasis of the present invention
Suddenly it is well known to those skilled in the art, at this by it will not go into details.
As shown in Figure 2 A, in the manufacture method of the semiconductor element of the present embodiment, first, carry
Substrate 21, and on substrate 21, form semiconductor stacked structure 29.In semiconductor stack
In structure 29, form a pile superimposition cap rock 25.Semiconductor stack stack structure 29 includes a grid
Structure 23 and a wall 24.In one embodiment, the formation side of semiconductor stack stack structure 29
Formula can be prior to forming shallow trench isolation (shallow trench isolation, STI) on substrate 21
Structure 22, forms grid structure 23 and wall 24 afterwards on sti structure 22.Wherein,
In one embodiment, substrate 21 is for example and without limitation to P-type silicon substrate, in another embodiment,
Substrate 21 can also be other semiconductor substrates.The present embodiment is to form one on substrate 21
Sti structure 22 is as an example.In another embodiment, it is possible to oxidation on substrate 21
Processing procedure forms a zone oxidation (local oxidation of silicon, LOCOS) structure and replaces
The sti structure 22 stated, above are only illustration, but is not limited to this.
Sectional view according to Fig. 2 A regards it, and from bottom to top, grid structure 23 includes one first
Grid layer 231, one gate nitridation dielectric layer 232, gate oxidation dielectric layer 233 and one second
Grid layer 234.Wherein, first grid layer 231 is formed on fleet plough groove isolation structure 22.Grid
Pole nitridation dielectric layer 232 is formed on first grid layer 231.Gate oxidation dielectric layer 233 is formed
On gate nitridation dielectric layer 232.Second grid layer 234 is formed at gate oxidation dielectric layer 233
On.
In the present embodiment, first grid layer 231 and second grid layer 234 are in order to as grid
The electrical contact of structure 23, it includes conductive material, is for example and without limitation to metal or has P
Type or the polysilicon (Poly-Si) of N-type impurity doping.
Sectional view according to Fig. 2 A regards it, and from bottom to top, wall 24 includes spacer oxide layer
24b and spacer nitride layer 24a.Spacer oxide layer 24b is formed at the sidewall of grid structure 23
Outer and the sidewall of wrapped-gate electrode structure 23.Spacer nitride layer 24a is formed at spacer oxide layer 24b
Sidewall outside.In the present embodiment, spacer oxide layer 24b and spacer nitride layer 24a includes
Insulant.
It should be noted that, the invention is not limited in and apply at above-mentioned grid structure and wall
Structure.For example, grid structure necessarily includes bigrid, and spacer layer configuration is necessarily again
Including the dual wall being combined.
Then, as shown in Figure 2 B, (that is in grid structure on semiconductor stack stack structure 29
On 23 and outside the sidewall of wall 24), form at least some of of stacking cover layer 25.Wherein,
In the present embodiment, at least one of method forming stacking cover layer 25 comprises the following steps.
It is initially formed one first covering oxide layer 251 on semiconductor stack stack structure 29 (that is in grid structure
On 23 and outside the sidewall of wall 24).Then, then formed a nitration case 252 in first cover
In oxide layer 251.That is, " stacking cover layer 25 at least some of " includes nitration case 252.
In one embodiment, nitration case 252 can be SixNyMaterial.
The feature of the present embodiment is step as that shown in fig. 2 c, complete to stack cover layer 25 it
Before, first remove a part (that is the part shown in the arrow of Fig. 2 C) for nitration case 252.Figure
Step shown in 2C can by lithographic with etched.
Then, as shown in Figure 2 D, one second covering oxide layer 253 is formed in nitration case 252
Remainder on.Consequently, it is possible to complete all parts of stacking cover layer 25.That is,
Stacking cover layer 25 includes the first covering oxide layer 251, the remainder of nitration case 252 and the
Two cover oxide layer 253.Especially, the present embodiment is put unlike the prior art and is: existing
In technology, seeing it from the lines AA ' of Figure 1A, from bottom to top, stacking cover layer 15 includes the
One covers oxide layer 151, nitration case 152 and the second covering oxide layer 153.But, in this reality
Executing in example, regard it according to the lines BB ' of Fig. 2 D, from bottom to top, stacking cover layer 25 includes
First covering oxide layer 251 and the second covering oxide layer 253, but in the position of lines BB ' the most not
Including nitration case 252.
Then, as shown in Figure 2 E, on stacking cover layer 25, form a protective layer 26, and lose
Carve protective layer 26, to form a perforate 261.In the present embodiment, the side of etch protection layer 26
Formula can be to use dry-etching or Wet-type etching, isotropic etching or anisotropic etching, wherein
The present embodiment can use anisotropic etching to form above-mentioned perforate 261, and detailed description of the invention can be
Inductively coupled plasma (inductive coupling plasma, ICP) etching method is used to be etched, but
It is not limited to this.
It should be noted that in the present embodiment, owing to removing nitration case in Fig. 2 step C
The part of 252, therefore in Fig. 2 E, nitration case 252 does not adjoins because a part is removed
Perforate 261, therefore, in the present embodiment, nitration case 252 is not exposed by perforate 261.
Then, as shown in Figure 2 F, it is passed through etching material, wherein a present embodiment from perforate 261
It is in the way of isotropic etching is made, to etch substrate 21 to form structure as depicted in Fig. 2 F,
The most just the semiconductor element 20 with stacking cover layer is completed.In the present embodiment, etching
Material can be to use gas or liquid mode, and the present embodiment is with sulfur hexafluoride (SF6) or two
Xenon fluoride (XeF2) be illustrated.
Significantly, since nitration case 252 is not exposed by perforate 261, therefore, nitrogen
The remainder changing layer 252 is protected from etching the destruction of material.Therefore semiconductor element 20 is whole
Body structure is saved from damage.
Refer to Fig. 3 A-3E, the flow process section view signal of second embodiment of its display present invention
Figure.It should be noted that the present embodiment be intended to illustrate the present invention principal character, therefore,
Such as micro-photographing process step (figure required in the manufacture method of the semiconductor element of general standard
Do not show) with ion implantation manufacture process step (not shown) or other steps unrelated with the emphasis of the present invention
Suddenly it is well known to those skilled in the art, at this by it will not go into details.
As shown in Figure 3A, in the manufacture with the semiconductor element stacking cover layer of the present embodiment
In method, first, it is provided that substrate 21, semiconductor stacked structure is formed and on substrate 21
29.On semiconductor stack stack structure 29, form a pile superimposition cap rock 25.Semiconductor stack stack structure
29 include grid structure 23 and a wall 24.In one embodiment, semiconductor stack
The generation type of structure 29 is can be prior to forming a shallow trench isolation (shallow on substrate 21
Trench isolation, STI) structure 22, on sti structure 22, form grid structure 23 afterwards
And wall 24.Substrate 21 shown in the present embodiment, fleet plough groove isolation structure 22, grid structure
23 and wall 24 all similar in appearance to above-mentioned first embodiment, do not repeat them here.
Then, as shown in Figure 3 B, (that is in grid structure on semiconductor stack stack structure 29
On 23 and outside the sidewall of wall 24), form all parts of stacking cover layer 25.Wherein,
In the present embodiment, the method step of all parts forming stacking cover layer 25 includes following step
Suddenly.It is initially formed one first covering oxide layer 251 on semiconductor stack stack structure 29 (that is in grid
In structure 23 and outside the sidewall of wall 24)., then form a nitration case 252 in first then
Cover in oxide layer 251.Then, then formed one second covering oxide layer 253 in nitration case 252
On.Consequently, it is possible to complete all parts of stacking cover layer 25.That is, stacking covers
Layer 25 includes that the first covering oxide layer 251, nitration case 252 and second cover oxide layer 253.
Then, as shown in Figure 3 C, on stacking cover layer 25, form a protective layer 26, and lose
Carve protective layer 26, to form a perforate 261.The material of the protective layer 26 shown in the present embodiment and
The generation type of perforate 261 all similar in appearance to above-mentioned first embodiment, does not repeats them here.
Then, as shown in Figure 3 D, the sidewall in perforate 261 forms a protection oxide layer 272.
Then, as shown in FIGURE 3 E, it is passed through etching material, wherein a present embodiment from perforate 261
It is in the way of isotropic etching is made, to etch substrate 21 to form structure as depicted in Fig. 3 E,
The most just the semiconductor element 30 with stacking cover layer is completed.It is similar to above-mentioned first real
Executing example, etching material can be to use gas or liquid mode, and the present embodiment is with lithium
Sulfur (SF6) or xenon difluoride (XeF2) be illustrated.
It should be noted that the present embodiment is unlike prior art shown in Figure 1B: at figure
In prior art shown in 1B, the sidewall of perforate 161 is formed without any other material.But,
In Fig. 3 D of the present embodiment, owing to the sidewall of perforate 261 has protection oxide layer 272, and
Owing to protection oxide layer 272 can tolerate etching material sulfur hexafluoride (SF6) or xenon difluoride
(XeF2) etching, therefore the overall structure of semiconductor element 30 is saved from damage.
In one embodiment, the manufacture method of the semiconductor element of this case can be applicable to manufacture infrared
Temperature sensor in line temperature sensing module.
More than having been for preferred embodiment so that the present invention to be described, simply the above, only make this
Skilled person is apparent to present disclosure, is not used for limiting the right model of the present invention
Enclose.Under the same spirit of the present invention, those skilled in the art can think and various equivalence change.
All this kind, all can analogize according to teachings of the present invention and obtain, and therefore, the scope of the present invention should
Contain above-mentioned and other all equivalence changes.Additionally, arbitrary enforcement kenel of the present invention is necessarily
Reaching all of purpose or advantage, therefore, any one of claim the most should be as limit.
Claims (14)
1. the manufacture method of a semiconductor element, it is characterised in that including:
One substrate is provided；
Semiconductor stacked structure is formed on this substrate；
On this semiconductor stack stack structure, form at least some of of a pile superimposition cap rock, wherein should
This of stacking cover layer includes a nitration case at least partially；
Remove a part for this nitration case；
Complete all parts of this stacking cover layer；
On this stacking cover layer, form a protective layer, and etch this protective layer, to be formed at least
One perforate, wherein this nitration case is not exposed by this perforate；And
It is passed through an etching material, to etch this substrate from this perforate.
2. the manufacture method of semiconductor element as claimed in claim 1, wherein, in this substrate
The method of this semiconductor stack stack structure of upper formation includes:
An insulation structure of shallow groove is formed on this substrate；And
A grid structure and a wall is formed on this insulation structure of shallow groove.
3. the manufacture method of semiconductor element as claimed in claim 2, wherein, forms this grid
The method of electrode structure includes:
Form a first grid layer on this insulation structure of shallow groove；
Form a gate nitridation dielectric layer on this first grid layer；
Form a gate oxidation dielectric layer on this gate nitridation dielectric layer；And
Form a second grid layer on this gate oxidation dielectric layer.
4. the manufacture method of semiconductor element as claimed in claim 2, wherein, is formed between being somebody's turn to do
The method of interlayer includes:
Form a spacer oxide layer outside the sidewall of this grid structure；And
Form a spacer nitride layer outside the sidewall of this spacer oxide layer.
5. the manufacture method of semiconductor element as claimed in claim 1, wherein, partly leads in this
At least one of method forming this stacking cover layer on body stacked structure includes:
Form one first covering oxide layer on this semiconductor stack stack structure；And
Form a nitration case in this first covering oxide layer.
6. the manufacture method of semiconductor element as claimed in claim 5, wherein, completes this heap
The method of all parts of superimposition cap rock includes:
Form this second covering oxide layer on the remainder of this nitration case.
7. the manufacture method of semiconductor element as claimed in claim 1, wherein, this etching material
Material includes sulfur hexafluoride or xenon difluoride.
8. the manufacture method of a semiconductor element, it is characterised in that including:
One substrate is provided；
Semiconductor stacked structure is formed on this substrate；
A pile superimposition cap rock, wherein this stacking cover layer bag is formed on this semiconductor stack stack structure
Include a nitration case；
On this stacking cover layer, form a protective layer, and etch this protective layer, to be formed at least
One perforate, wherein this perforate exposes this at least part of nitration case；
Sidewall in this perforate forms a protection oxide layer, to cover this at least part of nitration case；
And
It is passed through an etching material, to etch this substrate from this perforate.
9. the manufacture method of semiconductor element as claimed in claim 8, wherein, in this substrate
The method of this semiconductor stack stack structure of upper formation includes:
An insulation structure of shallow groove, and shape on this insulation structure of shallow groove is formed on this substrate
Become a grid structure and a wall.
10. the manufacture method of semiconductor element as claimed in claim 9, wherein, forms this grid
The method of electrode structure includes:
Form a first grid layer on this insulation structure of shallow groove；
Form a gate nitridation dielectric layer on this first grid layer；
Form a gate oxidation dielectric layer on this gate nitridation dielectric layer；And
Form a second grid layer on this gate oxidation dielectric layer.
The manufacture method of 11. semiconductor elements as claimed in claim 9, wherein, is formed between being somebody's turn to do
The method of interlayer includes:
One spacer oxide layer, is formed at outside the sidewall of this grid structure；And
One spacer nitride layer, is formed at outside the sidewall of this spacer oxide layer.
The manufacture method of 12. semiconductor elements as claimed in claim 9, wherein, partly leads in this
The method forming this stacking cover layer on body stacked structure includes:
Form one first covering oxide layer on this semiconductor stack stack structure；
Form this nitration case in this first covering oxide layer；And
Form one second covering oxide layer on this nitration case.
The manufacture method of 13. semiconductor elements as claimed in claim 8, wherein this etching material
Including sulfur hexafluoride or xenon difluoride.
14. 1 kinds of semiconductor elements, it is characterised in that including:
One substrate；
Semiconductor stacked structure, is configured on this substrate；
A pile superimposition cap rock, is covered on this semiconductor stack stack structure, wherein this stacking cover layer
Sequentially be stacked with one first covering oxide layer, a nitration case and one second covers oxide layer；
And
One protective layer, is configured on this stacking cover layer and has at least one perforate, and wherein this is opened
Hole exposes part this second covering oxide layer of this first covering oxide layer and part, and is somebody's turn to do
Nitration case is not exposed by this perforate.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050059901A (en) * | 2003-12-15 | 2005-06-21 | 매그나칩 반도체 유한회사 | Method for manufacturing semiconductor device |
| KR20060076518A (en) * | 2004-12-29 | 2006-07-04 | 주식회사 하이닉스반도체 | Method of manufacturing in flash memory device |
| CN102832125A (en) * | 2011-06-13 | 2012-12-19 | 联华电子股份有限公司 | Method for manufacturing semiconductor component |
| CN103456641A (en) * | 2012-05-29 | 2013-12-18 | 新加坡商格罗方德半导体私人有限公司 | HKMG device with PMOS eSiGe source/drain regions |
| CN103972293A (en) * | 2014-05-20 | 2014-08-06 | 上海华力微电子有限公司 | Side wall structure, manufacturing method of side wall structure and CMOS device |
| CN104412373A (en) * | 2012-07-16 | 2015-03-11 | 德克萨斯仪器股份有限公司 | Method of reducing formation of SiGe abnormal growths on polycrystalline electrodes for strained-channel PMOS transistors |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6991979B2 (en) * | 2003-09-22 | 2006-01-31 | International Business Machines Corporation | Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs |
| KR100550343B1 (en) * | 2003-11-21 | 2006-02-08 | 삼성전자주식회사 | Method of manufacturing semiconductor device having multiple channels MOS transistor |
| CN102856258B (en) * | 2011-07-01 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
| CN104701136B (en) * | 2013-12-05 | 2018-09-07 | 中芯国际集成电路制造(上海)有限公司 | Capacitor, semiconductor devices and forming method thereof |
-
2015
- 2015-06-16 CN CN201910433747.9A patent/CN110120340B/en active Active
- 2015-06-16 CN CN201510332823.9A patent/CN106257622B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050059901A (en) * | 2003-12-15 | 2005-06-21 | 매그나칩 반도체 유한회사 | Method for manufacturing semiconductor device |
| KR20060076518A (en) * | 2004-12-29 | 2006-07-04 | 주식회사 하이닉스반도체 | Method of manufacturing in flash memory device |
| CN102832125A (en) * | 2011-06-13 | 2012-12-19 | 联华电子股份有限公司 | Method for manufacturing semiconductor component |
| CN103456641A (en) * | 2012-05-29 | 2013-12-18 | 新加坡商格罗方德半导体私人有限公司 | HKMG device with PMOS eSiGe source/drain regions |
| CN104412373A (en) * | 2012-07-16 | 2015-03-11 | 德克萨斯仪器股份有限公司 | Method of reducing formation of SiGe abnormal growths on polycrystalline electrodes for strained-channel PMOS transistors |
| CN103972293A (en) * | 2014-05-20 | 2014-08-06 | 上海华力微电子有限公司 | Side wall structure, manufacturing method of side wall structure and CMOS device |
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| CN106257622B (en) | 2019-06-18 |
| CN110120340A (en) | 2019-08-13 |
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