CN104810389A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN104810389A CN104810389A CN201410032417.6A CN201410032417A CN104810389A CN 104810389 A CN104810389 A CN 104810389A CN 201410032417 A CN201410032417 A CN 201410032417A CN 104810389 A CN104810389 A CN 104810389A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims description 36
- 239000000758 substrate Substances 0.000 claims description 45
- 239000011800 void material Substances 0.000 claims description 31
- 230000004888 barrier function Effects 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 23
- 239000007800 oxidant agent Substances 0.000 claims description 11
- 230000001590 oxidative effect Effects 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 7
- 238000012940 design transfer Methods 0.000 claims description 4
- 239000000725 suspension Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 56
- 238000005520 cutting process Methods 0.000 description 11
- 230000008569 process Effects 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- 230000006378 damage Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 208000027418 Wounds and injury Diseases 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 208000014674 injury Diseases 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Abstract
The invention provides a semiconductor structure, which comprises a base, at least one fin-shaped structure group, a plurality of secondary fin-shaped structures and shallow trench isolation, wherein the at least one fin-shaped structure group and the plurality of secondary fin-shaped structures are located on the base, the fin-shaped structure group is located between two secondary fin-shaped structures, the top surface of each secondary fin-shaped structure is lower than the top surface of the fin-shaped structure group, the shallow trench isolation is located in the base, and the secondary fin-shaped structures are completely covered by the shallow trench isolation.
Description
Technical field
The present invention be relevant semiconductor structure with and preparation method thereof, especially a kind of semiconductor structure with the secondary fin structure that main fin structure can be protected to escape injury.
Background technology
Along with reducing of semiconductor element size, the usefulness maintaining small size semiconductor element is the main target of current industry.In order to improve the usefulness of semiconductor element, develop various multiple-grid poles field effect transistor element (multi-gate MOSFET) at present gradually.Multiple-grid pole field effect transistor element comprises following several advantages.First, the manufacture craft of multiple-grid pole field effect transistor element can be integrated with traditional logic element manufacture craft, therefore has suitable manufacture craft compatibility; Secondly, because stereochemical structure adds the contact area of grid and substrate, therefore the control of grid for passage area electric charge can be increased, thus reduce that the drain electrode that brings of small-sized component causes can be with reduction (Drain Induced Barrier Lowering, DIBL) effect and short-channel effect (short channel effect); In addition, the grid due to same length has larger channel width, therefore also can increase the magnitude of current between source electrode and drain electrode.
Further, multiple-grid pole field effect transistor element is for be formed on fin structure by grid, and fin structure is then formed in substrate.Fin structure is generally the list structure parallel to each other that etching substrate is formed, under the requirement of size micro, the gradually narrow and spacing between each fin structure of the width of each fin structure reduces, and under the considering of the restriction of various manufacture craft parameter and physics limit, how forming the fin structure meeting the requirement of size micro has been the large problem of one of contemporary semiconductor industry.
Summary of the invention
For solving the problem, the invention provides semiconductor structure, comprise a substrate, at least one fin structure group and multiple fin structures are positioned in this substrate, wherein this fin structure group is between two fin structures, and an end face of each fin structure is lower than an end face of this fin structure group, and a shallow isolating trough is arranged in this substrate, and respectively this fin structure is covered completely by this shallow isolating trough.
The present invention also provides the manufacture method of semiconductor structure, at least comprise following steps: first, one substrate is provided, there is multiple void put fin structure and be positioned in this substrate, multiple patterned mask layer is positioned at those void and puts on fin structure, afterwards, remove part to be positioned at those void and to put this patterned mask layer on fin structure, then an etching step is carried out, to form at least one fin structure group and multiple fin structures in this substrate, wherein an end face of this fin structure is lower than an end face of this fin structure group, finally, form a shallow isolating trough in this substrate, and respectively this fin structure is covered completely by this shallow isolating trough
The invention provides a kind of semiconductor structure with and preparation method thereof.In this semiconductor structure, be positioned at except in substrate except including fin structure group, semiconductor structure of the present invention also includes the both sides that multiple fin structures are positioned at this fin structure group.Those time fin structure can protect fin structure group from arriving the destructions such as etching process.Under destruction situation is lowered, the quality of semiconductor structure and production capacity can reach effective lifting.
Accompanying drawing explanation
Fig. 1-11 illustrates the semiconductor structure manufacturing process of the present invention first preferred embodiment.
Figure 12 A illustrates the partial top view of the semiconductor structure of Figure 11.
Figure 12 B illustrates another embodiment of the partial top view of the semiconductor structure of Figure 11.
Main element symbol description
10 substrates
12 mask layers
12 ' mask layer
12A mask layer
12B mask layer
12C mask layer
14 sacrificial pattern
16 sidewall
18 void put fin structure
18A void puts fin structure
18B void puts fin structure
20 patterning photoresist oxidant layer
22 fin structure groups
22A end face
23 main fin structures
23A end face
24 fin structures
24A end face
26 insulating barriers
26A end face
28 layings
X height
Embodiment
For making the general technology person being familiar with the technical field of the invention further can understand the present invention, hereafter spy enumerates preferred embodiment of the present invention, and coordinates institute's accompanying drawings, describe in detail constitution content of the present invention and the effect for reaching.
For convenience of description, each graphic being only of the present invention is illustrated to be easier to understand the present invention, and its detailed ratio can adjust according to the demand of design.The described in the text upper and lower relation for opposed member in figure, people in this area will be understood that its relative position referring to object, therefore all can overturn and present identical component, this all should belong to the scope disclosed by this specification together, first chats bright in this appearance.
Fig. 1-11 illustrates the semiconductor structure manufacturing process of the present invention first preferred embodiment.As shown in Figures 1 to 3, multiple sidewall 16 is formed in a substrate 10.Being described in more detail, as shown in Figure 1, providing a destination layer, such as, is a substrate 10.Substrate 10 can comprise semiconductor base such as silicon base, containing silicon base, silicon base (such as GaN-on-silicon) is covered in one three five races, a Graphene covers silicon base (graphene-on-silicon) or the semiconductor base such as one silicon-coated insulated (silicon-on-insulator, SOI) substrate.One mask layer 12 is formed in substrate 10, and wherein mask layer 12 may be single layer structure or sandwich construction, and the material of mask layer 12 may include silicon nitride or silica, but is not limited thereto.In the present embodiment, mask layer 12 is three-deckers, comprises one and is positioned at bottom and the mask layer 12A be made up of silica; One is positioned at middle level and the mask layer 12B be made up of silicon nitride; And one is positioned at upper strata and the mask layer 12C be made up of silica, but be not limited to this.
Then, multiple sacrifice layer pattern 14 is formed in this substrate 10.In the present embodiment, the manufacture craft forming sacrifice layer pattern 14 can be integrated with the gate fabrication process generally applied, such as can carry out a conventional gate manufacture craft, to form multiple sacrifice grid as sacrificial pattern 14 in substrate 10, but the present invention is not as limit.Therefore, sacrificial pattern 14 is polysilicon gate in one embodiment, but its material is non-is limited to this, depending on actual required.
Afterwards, as shown in Figure 2, form multiple sidewall 16 in substrate 10, and it is other to be positioned at each sacrifice layer pattern 14.Illustrate further, an expendable material (not shown) is conformally covered in each sacrifice layer pattern 14 and substrate 10, then etches this expendable material, to form sidewall 16.This step can be integrated with the gate fabrication process generally applied.Sidewall 16 can be such as a silicon nitride gap wall, but the present invention is not as limit.Sidewall 16 may and sacrificial pattern 14 between there is etching selectivity, in addition, sidewall 16 is also not limited to single layer structure, and it is likely sandwich construction.
As shown in Figure 3, each sacrifice layer pattern 14 is removed, be therefore only left sidewall 16 in substrate 10 to the open air, and the part of substrate 10 be originally positioned at immediately below each sacrifice layer pattern 14 is exposed out.
As shown in Figure 4, carry out a design transfer manufacture craft, by the design transfer of sidewall 16 on mask layer 12, and mask layer 12 is converted to multiple patterned mask layer 12 '.Illustrate, by sidewall 16 as mask, carry out an etching step (not shown) to remove the mask layer 12 of part, therefore form multiple patterned mask layer 12 ' in substrate 10.In general, above-mentionedly utilize sidewall as mask to carry out the method for design transfer manufacture craft, be called " sidewall pattern transfer manufacture craft (sidewall image transfer, SIT) ".Wherein this etching step may comprise dry ecthing or wet etching, or the combination etc. of dry ecthing and wet etching.In the present embodiment, because mask layer 12 is three-deckers, therefore each patterned mask layer 12 ' also may be the three-decker that a silicon nitride layer and two silicon oxide layers combine, but is not limited to this.In other embodiments, the patterned mask layer 12 ' of sidewall 16 and part may shift in the etching process of manufacture craft at sidewall pattern and be consumed, and each patterned mask layer 12 ' formed therefore may be single layer structure or sandwich construction.
Next, as shown in Figure 5, carry out an etching step, to remove the substrate 10 that the not masked layer 12 ' of part covers, and in substrate 10, form multiple void and put fin structure 18.Putting fin structure 18 due to each void in the present invention is by etching substrate 10 and producing, and therefore to put the material of fin structure 18 identical with substrate 10 for each void.In addition, each mask layer 12 ' still may be present in each void and put on fin structure 18, but in the present embodiment, the mask layer 12 ' of part is consumed in etching process, and only have the mask layer 12 ' of part to stay each void and put on fin structure 18, but the present invention is not limited to this, may be single layer structure or sandwich construction in this each patterned mask layer 12 '.
As shown in Figure 6, form a patterning photoresist oxidant layer 20 in substrate 10, the mask layer 12 ' of cover part and the void of part put fin structure 18.In this step, each void puts fin structure 18 can be divided into two kinds of different groups: be that the void being patterned photoresist oxidant layer 20 covering puts fin structure 18A respectively, and the void not being patterned photoresist oxidant layer 20 covering puts fin structure 18B.In the present invention, respectively be patterned the void that photoresist oxidant layer 20 covers to put fin structure 18A and will be made into main fin structure at subsequent step, therefore each void put the position of fin structure 18A will the component structure layout of corresponding semiconductor structure of the present invention, on the other hand, each void not being patterned photoresist oxidant layer 20 covering puts fin structure 18B, main fin structure can not be made at subsequent step, therefore, void is put fin structure 18B and is positioned at the side that void puts fin structure 18A, illustrate further, each void is put fin structure 18A and can be considered as one " group ", this group puts between fin structure 18B two void.In addition, void puts the existence of fin structure 18B, also can reduce semiconductor structure of the present invention in manufacturing process, such as etching or exposure etc., the load effect (1oading effect) of generation.It should be noted that, in this step, after patterning photoresist oxidant layer 20 is formed, can carry out a cutting manufacture craft (cutting process) in passing, with will from top view, each void presenting rectangle ring-type puts fin structure 18A separately, become many strip void be arranged in parallel with each other and put fin structure 18A, but in the present invention, cutting step is not limited to carry out at this moment, also may carry out before this step or afterwards.
Then, as Figure 7-8, remove each void and put mask layer 12 ' above fin structure 18B, that is, carry out an etching step, to remove not being subject to the mask layer 12 ' that patterning photoresist oxidant layer 20 protects.Afterwards, as shown in Figure 8, patterning photoresist oxidant layer 20 removed, the method removed may include an etching step or additive method etc., the present invention is not limited thereto.
Afterwards, as shown in Figure 9, carry out another etching step, again to etch substrate 10, and form at least one fin structure group 22 and multiple fin structures 24 in substrate 10, wherein fin structure group 22 comprises multiple main fin structure 23.Fin structure group 22 is between two fin structures 24.In this step; because each main fin structure 23 is in etching process; be subject to the protection of mask layer 12 '; but each void puts the protection that fin structure 18B is not subject to mask layer 12 '; and be consumed in etching process, therefore an end face 23A of each a main fin structure 23 and end face 24A of each fin structure 24 is not positioned in same level.More clearly state, an end face 23A of each main fin structure 23 is higher than an end face 24A of each fin structure 24.In the present embodiment, by adjustment etching period and etching method, to control the height of main fin structure 23 and time fin structure 24.
Please refer to Figure 10-11, again as shown in Figure 10, one laying 28 and an insulating barrier 26 are sequentially formed in substrate 10, cover main fin structure 23 and secondary fin structure 24, and the space inserted between each main fin structure 23 and secondary fin structure 24, insulating barrier 26 is such as one silica layer, but is not limited thereto.In the present embodiment, insulating barrier 26 will be used to be made into shallow isolating trough (shallow trench isolation, STI) at subsequent manufacturing processes.Then, as shown in figure 11, carry out a planarisation step, such as an etch-back manufacture craft and/or a cmp (chemical mechanical polishing, CMP), to remove the upper unnecessary insulating barrier 26 of mask layer 12 ', it should be noted that in the process of etching, the mask layer 12 ' that left behind is taken as stop-layer and uses, that is, after etching process, the surface of etching will be parked in mask layer 12 ' end face.Finally, in order to shallow isolating trough will be formed in substrate 10, insulating barrier 26 will be carried out to the etch-back step of another time, the insulating barrier 26 of part is removed, and expose the main fin structure 23 of part, but be worth live it is noted that secondary fin structure 24 still completely cover by insulating barrier 26 (or STI).In the present invention, the main fin structure 23 of the part exposed can be regarded as " element fin structure ", other elements in Subsequent semiconductor structure are electrically connected by least one wire (not shown), secondary fin structure 24 is then " suspension joint structure " in the present invention, that is, any element is not electrically connected secondary fin structure 24 with other.In the present invention, each main fin structure 23 (element fin structure) height exposed highly can change by adjusting manufacturing process steps with each fin structure 24.In the present embodiment, as shown in figure 11, suppose that the height (meaning the end face from an end face 26A of insulating barrier 26 to fin structure group 22) of main fin structure 23 is for " X ", then the height (meaning the end face from a bottom surface of insulating barrier 26 to each fin structure 24) of each fin structure 24 is better between 0.9X ~ 2X scope, but is not limited thereto.As long as the end face 24A meeting time fin structure 24 is higher than the end face 23A of main fin structure 23, be namely within the scope of the present invention.
Semiconductor structure provided by the present invention, as shown in figure 11, at least include: a substrate 10, at least one fin structure group 22 and at least one times fin structure 24 are positioned in substrate 10, wherein fin structure group 22 is between twice fin structure 24, and an end face 24A of secondary fin structure 24 comes low compared with an end face 22A of fin structure group 22, an insulating barrier 26 is positioned in substrate 10.In the present invention, fin structure group 22 includes multiple main fin structure 23, and an end face 26A of insulating barrier 26 comes low compared with an end face 22A of fin structure group 22, and the end face 26A of insulating barrier 26 comes high compared with an end face 24A of secondary fin structure 24.In addition, each fin structure group 22 is electrically connected by least one wire (not shown) and semiconductor element, but each fin structure 24 is not connected with other semiconductor element electrics, and belongs to a suspension joint structure.If it should be noted that aforesaid cutting step so far not yet carries out, also can carry out after the step shown in Figure 11, after carrying out cutting step, the laying 28 being partly positioned at main fin structure 23 periphery will be cut.Please refer to Figure 12 A, Figure 12 A is one of the partial top view of Figure 11 embodiment, as illustrated in fig. 12, after cutting step carries out, laying 28 is owing to there being part cut, therefore remaining laying 28 is only positioned at the both sides of main fin structure 23, but is not cut due to secondary fin structure 24, therefore laying 28 still complete covering time fin structure 24.It should be noted that in the present embodiment, the cut direction of cutting step, being the first direction arranged along a vertical main fin structure 23, such as, is the X-axis on figure.In addition, in the present invention, each main fin structure 23 presents long strip type, and is separated from each other each other, and each fin structure 24, because be not cut, from top view, still presents rectangular ring-type.In fig. 12, because cutting step just carries out after laying 28 and insulating barrier all complete, so only have the main fin structure 23 of part can be removed with the laying 28 be covered on the main fin structure 23 of those parts, in the present embodiment, by top view, each main fin structure includes four limits, and wherein at least two limits not cover by laying 28, two other limit then cover by laying 28.
In another embodiment, ask for an interview Figure 12 B, Figure 12 B is another embodiment of the partial top view of Figure 11, and in the present embodiment, the cut direction of cutting step is the direction parallel with each main fin structure 23, such as, be the Y direction on figure.After cutting step carries out, each main fin structure 23 originally presenting ring-type will be separated, and becomes the main fin structure 23 of many long strip types.In addition, the laying 28 of part is also removed after cutting step carries out, the laying 28 especially near main fin structure about 23 two-end-point.Similarly, in the present embodiment, by top view, each main fin structure 23 includes four limits, and wherein at least two limits not cover by laying 28 and expose to the open air out, two other limit then by laying 28 part cover.
The invention is characterized in, semiconductor structure of the present invention also includes the side that multiple fin structures 24 are positioned at fin structure group 22.In general, in follow-up semiconductor fabrication process, in order to form fin-shaped semiconductor element (fin-FET device), some heating manufacture crafts will be carried out, when heating insulating barrier, the inside of insulating barrier may produce stress (as compression stress or tensile stress) because of variations in temperature, and these stress likely can injure fin structure, in order to avoid said circumstances, the secondary fin structure 24 that the present invention comprises, be positioned at fin structure group 22 other, the function of preferential absorption stress can be reached, and then main fin structure 23 injures to the stress produced by variations in temperature in protection fin structure group 22.
In sum, the invention provides semiconductor structure and preparation method thereof.In the semiconductor structure, except general fin structure group is positioned in substrate, also include multiple secondary fin structure being positioned at fin structure group side.Those fin structure can help to protect main fin structure from the injury to stress, and thus, fin structure can reduce destroyed probability, and improves the quality of semiconductor structure and production yield.
The foregoing is only preferred embodiment of the present invention, all equalizations done according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (17)
1. semiconductor structure, comprises;
One substrate;
At least one fin structure group and multiple fin structures, be positioned in this substrate, and wherein this fin structure group is between two fin structures, and an end face of each fin structure is lower than an end face of this fin structure group; And
Shallow isolating trough, is arranged in this substrate, and this shallow isolating trough is made up of an insulating barrier, and respectively this fin structure is covered completely by this shallow isolating trough.
2. semiconductor structure as claimed in claim 1, wherein this fin structure group comprises multiple main fin structure.
3. semiconductor structure as claimed in claim 2, wherein also comprises a laying, and complete covering is respectively on this fin structure, and part covers each main fin structure.
4. semiconductor structure as claimed in claim 3, wherein respectively this main fin structure include at least two limits expose by this laying to the open air.
5. semiconductor structure as claimed in claim 1, wherein an end face to the height of an end face of this fin structure group of this insulating barrier is X, and a bottom surface of this insulating barrier to the height of an end face of this fin structure in the scope of 0.9X ~ 2X.
6. semiconductor structure as claimed in claim 1, wherein an end face of this insulating barrier is low compared with an end face of this fin structure group.
7. semiconductor structure as claimed in claim 1, wherein an end face of this insulating barrier is high compared with an end face of this fin structure.
8. semiconductor structure as claimed in claim 1, wherein respectively this fin structure is a suspension joint structure.
9. a manufacture method for semiconductor structure, at least comprises following steps:
One substrate is provided, there is multiple void and put fin structure and be positioned in this substrate, and multiple patterned mask layer is positioned at those void and puts on fin structure;
Remove part to be positioned at this void and to put this patterned mask layer on fin structure;
Carry out an etching step, to form at least one fin structure group and multiple fin structure substrates in this substrate, wherein an end face of this fin structure is lower than an end face of this fin structure group; And
Form a shallow isolating trough in this substrate, this shallow isolating trough is made up of an insulating barrier, and respectively this fin structure is covered completely by this shallow isolating trough.
10. manufacture method as claimed in claim 9, the method wherein removing this patterned mask layer of part comprises following steps:
Form a patterning photoresist oxidant layer and put fin structure and this patterned mask layer of part with this void of cover part; And
Carry out an etching step, with remove part not this patterned mask layer of part of covering by this patterning photoresist oxidant layer.
11. manufacture methods as claimed in claim 9, wherein also comprise and being covered on this fin structure group and this fin structure by this insulating barrier, and carry out a planarisation step to this insulating barrier.
12. manufacture methods as claimed in claim 11, wherein also comprise and carry out an etch-back step to this insulating barrier, to expose this fin structure group of part.
13. manufacture methods as claimed in claim 11, also comprise and carry out a heating manufacture craft to this insulating barrier.
14. manufacture methods as claimed in claim 9, wherein this fin structure group is between twice fin structure.
15. manufacture methods as claimed in claim 9, wherein respectively this fin structure is a suspension joint structure.
16. manufacture methods as claimed in claim 9, wherein this fin structure group comprises multiple main fin structure.
17. manufacture methods as claimed in claim 9, the method wherein forming this patterned mask layer comprises a sidewall design transfer manufacture craft.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106571364A (en) * | 2015-10-07 | 2017-04-19 | 三星电子株式会社 | Integrated circuit device and method of manufacturing the same |
| CN109273442A (en) * | 2017-07-18 | 2019-01-25 | 联华电子股份有限公司 | Semiconductor element and preparation method thereof |
| CN111106064A (en) * | 2018-10-29 | 2020-05-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111785721A (en) * | 2017-06-27 | 2020-10-16 | 联华电子股份有限公司 | Static random access memory cell array |
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| CN102054741A (en) * | 2009-10-27 | 2011-05-11 | 台湾积体电路制造股份有限公司 | Method of forming integrated circuit structure |
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