CN106257622B - Semiconductor element and its manufacturing method - Google Patents
Semiconductor element and its manufacturing method Download PDFInfo
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- CN106257622B CN106257622B CN201510332823.9A CN201510332823A CN106257622B CN 106257622 B CN106257622 B CN 106257622B CN 201510332823 A CN201510332823 A CN 201510332823A CN 106257622 B CN106257622 B CN 106257622B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000010410 layer Substances 0.000 claims abstract description 108
- 238000000576 coating method Methods 0.000 claims abstract description 40
- 238000006396 nitration reaction Methods 0.000 claims abstract description 40
- 239000011248 coating agent Substances 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims abstract description 19
- 239000011241 protective layer Substances 0.000 claims abstract description 16
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 11
- 125000006850 spacer group Chemical group 0.000 claims description 13
- 229910018503 SF6 Inorganic materials 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 239000011435 rock Substances 0.000 claims description 9
- -1 spacer nitride Chemical class 0.000 claims description 8
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 7
- 229960000909 sulfur hexafluoride Drugs 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims description 6
- 229910052724 xenon Inorganic materials 0.000 claims description 2
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 claims description 2
- 239000011229 interlayer Substances 0.000 claims 1
- PQIOSYKVBBWRRI-UHFFFAOYSA-N methylphosphonyl difluoride Chemical group CP(F)(F)=O PQIOSYKVBBWRRI-UHFFFAOYSA-N 0.000 claims 1
- 238000002955 isolation Methods 0.000 description 10
- BLIQUJLAJXRXSG-UHFFFAOYSA-N 1-benzyl-3-(trifluoromethyl)pyrrolidin-1-ium-3-carboxylate Chemical compound C1C(C(=O)O)(C(F)(F)F)CCN1CC1=CC=CC=C1 BLIQUJLAJXRXSG-UHFFFAOYSA-N 0.000 description 7
- 230000006378 damage Effects 0.000 description 6
- WRQGPGZATPOHHX-UHFFFAOYSA-N ethyl 2-oxohexanoate Chemical compound CCCCC(=O)C(=O)OCC WRQGPGZATPOHHX-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910020776 SixNy Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000010415 tropism Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention proposes a kind of manufacturing method of semiconductor element.The manufacturing method of semiconductor element includes: offer substrate；In formation semiconductor stack stack structure on substrate；In forming at least part for stacking coating on semiconductor stack stack structure, wherein at least part for stacking coating includes nitration case；Remove a part of nitration case；Complete all parts of stacking coating；Protective layer, and etch protection layer are formed on coating in stacking, to form an at least aperture, wherein nitration case is not exposed by aperture；And it is passed through an etching material from aperture, with etching substrate.The present invention separately proposes a kind of semiconductor element formed using the above method.
Description
Technical field
The present invention relates to a kind of semiconductor element and its manufacturing method, particularly relate to it is a kind of have stack coating, and energy
Nitration case is set to be protected from the semiconductor element and its manufacturing method of etching material damage.
Background technique
Figure 1A -1B is please referred to, shows the process schematic cross-sectional view of the manufacturing method of existing semiconductor element.Such as Figure 1A institute
Show, in the manufacturing method of the semiconductor element 10 of the prior art, semiconductor stack stack structure 19 is formed on substrate 11.In semiconductor
19 on stacked structure, a pile superimposition cap rock 15 is formed.Semiconductor stack stack structure 19 includes a gate structure 13 and a wall
14.Wherein, the generation type of semiconductor stack stack structure 19 are as follows: in formation shallow trench isolation (shallow trench on substrate 11
Isolation, STI) structure 12, and in formation gate structure 13 and wall 14 on the sti structure 12.Wherein, according to Figure 1A
Cross-sectional view regard it, from bottom to top, gate structure 13 includes: first grid layer 131, gate nitridation dielectric layer 132, grid oxygen
Change dielectric layer 133 and second grid layer 134.Wall 14 includes spacer oxide layer 14b and spacer nitride layer 14a.According to figure
The cross-sectional view of 1A regards it, and from bottom to top, stacking coating 15 includes: the first covering oxide layer 151, nitration case 152 and second
Cover oxide layer 153.It stacks and is formed with a protective layer 16 on coating 15, wherein the protective layer 16 is formed with after overetch
One aperture 161.
Then, as shown in Figure 1B, in the manufacturing method of the semiconductor element of the prior art, when being intended to etching substrate 11,
An etching material, such as sulfur hexafluoride (SF can be passed through from aperture 1616).Unfortunately, due to sulfur hexafluoride (SF6) stacking can be attacked
The nitration case 152 of coating 15, as shown in arrow in Figure 1B, this will be such that nitration case 152 is damaged, and influence the knot of semiconductor element 10
Structure.
In view of this, the present invention, which i.e. in view of the above shortcomings of the prior art, proposes that one kind has, stacks coating, and can make
Nitration case is protected from the manufacturing method of the semiconductor element of the destruction of etching material.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art and defect, a kind of semiconductor element and its manufacturer are provided
Method, which, which has, stacks coating, and nitration case can be made to be protected from the destruction for etching material.
In order to achieve the above object, just wherein a viewpoint says that the present invention provides a kind of manufacturing methods of semiconductor element.It is wrapped
Include the following steps.Firstly, providing a substrate.Then, in formation semiconductor stacked structure on the substrate.Then, it is partly led in this
At least part of a pile superimposition cap rock is formed on body stacked structure, this of the wherein stacking coating includes one at least partially
Nitration case.Then, a part of the nitration case is removed.Then, all parts of the stacking coating are completed.Then, in the heap
A protective layer is formed on superimposition cap rock, and etches the protective layer, and to form an at least aperture, wherein the nitration case is not by the aperture
It exposes.Then, it is passed through an etching material from the aperture, to etch the substrate.
Preferably implement in kenel a kind of, under the method and step for forming the semiconductor stack stack structure on the substrate includes
Column step.Firstly, in forming an insulation structure of shallow groove on the substrate.Then, in forming a grid on the insulation structure of shallow groove
Pole structure and a wall.
Preferably implement in kenel a kind of, the method and step for forming the gate structure includes the following steps.Firstly, being formed
One first grid layer is on the insulation structure of shallow groove.Then, a gate nitridation dielectric layer is formed on the first grid layer.It connects
, a gate oxidation dielectric layer is formed on the gate nitridation dielectric layer.Then, a second grid layer is formed in the gate oxidation
On dielectric layer.
Preferably implement in kenel a kind of, the method and step for forming the wall includes the following steps.Firstly, forming one
Spacer oxide layer is in outside the side wall of the gate structure.Then, a spacer nitride layer is formed in outside the side wall of the spacer oxide layer.
Preferably implement in kenel a kind of, in forming at least one of the stacking coating on the semiconductor stack stack structure
The method and step divided includes the following steps.Firstly, forming one first covering oxide layer on the semiconductor stack stack structure.Then,
A nitration case is formed in the first covering oxide layer.
It include forming this in a kind of method and step for preferably implementing to complete all parts of the stacking coating in kenel
Second covering oxide layer is on the remainder of the nitration case.
Preferably implement in kenel a kind of, which includes sulfur hexafluoride (SF6) or xenon difluoride (XeF2)。
In order to achieve the above object, saying that the present invention provides a kind of manufacturing methods of semiconductor element with regard to another viewpoint.It includes
The following steps.Firstly, providing a substrate.Then, in formation semiconductor stacked structure on the substrate.Then, in the semiconductor
A pile superimposition cap rock is formed on stacked structure, wherein the stacking coating includes a nitration case.Then, on the stacking coating
A protective layer is formed, and etches the protective layer, to form an at least aperture, wherein the aperture exposes this and at least partly nitrogenizes
Layer.Then, a protection oxide layer is formed in the side wall of the aperture, to cover at least partly nitration case.Then, logical from the aperture
Enter an etching material, to etch the substrate.
Preferably implement in kenel a kind of, in the method and step for forming the stacking coating on the semiconductor stack stack structure
Include the following steps.Firstly, forming one first covering oxide layer on the semiconductor stack stack structure.Then, the nitration case is formed
In in the first covering oxide layer.Then, one second covering oxide layer is formed on the nitration case.
In order to achieve the above object, saying that the present invention provides a kind of semiconductor elements with regard to another viewpoint.It includes a substrate, one
Semiconductor stack stack structure, a pile superimposition cap rock and a protective layer.Semiconductor stack stack structure is configured on the substrate.Stack covering
Layer is covered on the semiconductor stack stack structure, and wherein the stacking coating is sequentially stacked with one first covering oxide layer, a nitridation
Layer and one second covering oxide layer.Protective layer is configured on the stacking coating and has an at least aperture, and wherein the aperture is sudden and violent
The exposed portion first covering oxide layer and part the second covering oxide layer, and the nitration case is not exposed by the aperture.
Below by specific embodiment elaborate, when be easier to understand the purpose of the present invention, technology contents, feature and its
The effect of reached.
Detailed description of the invention
Figure 1A -1B shows the process schematic cross-sectional view of the manufacturing method of existing semiconductor element；
Fig. 2A -2F shows the process schematic cross-sectional view of one embodiment of the invention；
Fig. 3 A-3E shows the process schematic cross-sectional view of second embodiment of the invention.
Symbol description in figure
(prior art)
10 existing semiconductor elements
11 existing substrates
12 existing fleet plough groove isolation structures
13 existing gate structures
131 existing first grid layers
132 existing gate nitridation dielectric layers
133 existing gate oxidation dielectric layers
134 existing second grid layers
14 existing walls
The existing spacer nitride layer of 14a
The existing spacer oxide layer of 14b
15 existing stacking coatings
151 existing first covering oxide layers
152 existing nitration cases
153 existing second covering oxide layers
16 existing protective layers
161 existing apertures
19 existing semiconductor stack stack structures
The existing lines of AA '
(present invention)
20,30 semiconductor element
21 substrates
22 fleet plough groove isolation structures
23 gate structures
231 first grid layers
232 gate nitridation dielectric layers
233 gate oxidation dielectric layers
234 second grid layers
24 walls
24a spacer nitride layer
24b spacer oxide layer
25 stack coating
251 first covering oxide layers
252 nitration cases
253 second covering oxide layers
26 protective layers
261 apertures
272 protection oxide layers
29 semiconductor stack stack structures
BB ' lines
Specific embodiment
For the present invention aforementioned and other technology contents, feature and effect, it is following cooperation with reference to schema one preferably
In the detailed description of embodiment, can clearly it present.Schema in the present invention belongs to signal, be mostly intended to indicate each device with
And the function relationship between each element, it then and not according to ratio is drawn as shape, thickness and width.
Fig. 2A -2F is please referred to, shows the process schematic cross-sectional view of one embodiment of the invention.It is noticeable
It is that the present embodiment is intended to illustrate main feature of the invention, therefore, the institute in the manufacturing method of the semiconductor element of general standard
Such as micro-photographing process step (not shown) that needs and ion implantation manufacture process step (not shown) or other and weight of the invention
The unrelated step of point has been well known to those skilled in the art, herein by it will not go into details.
As shown in Figure 2 A, in the manufacturing method of the semiconductor element of the present embodiment, firstly, providing substrate 21, and in base
Semiconductor stacked structure 29 is formed on plate 21.In on semiconductor stack stack structure 29, a pile superimposition cap rock 25 is formed.Semiconductor stack
Stack structure 29 includes a gate structure 23 and a wall 24.In one embodiment, the formation side of semiconductor stack stack structure 29
Formula can be prior to forming a shallow trench isolation (shallow trench isolation, STI) structure 22 on substrate 21, later
In formation gate structure 23 and wall 24 on sti structure 22.Wherein, in one embodiment, substrate 21 is such as, but not limited to P
Type silicon substrate, in another embodiment, substrate 21 can also be other semiconductor substrates.The present embodiment is in shape on substrate 21
As an example at a sti structure 22.In another embodiment, can also on substrate 21 with oxidation process formed a region oxygen
Change (local oxidation of silicon, LOCOS) structure to replace above-mentioned sti structure 22, above are only and illustrate
It is bright, but not limited to this.
The cross-sectional view of A regards it according to fig. 2, and from bottom to top, gate structure 23 includes a first grid layer 231, a grid
Nitrogenize dielectric layer 232, a gate oxidation dielectric layer 233 and a second grid layer 234.Wherein, first grid layer 231 is formed in shallowly
On groove isolation construction 22.Gate nitridation dielectric layer 232 is formed in 231 on first grid layer.The formation of gate oxidation dielectric layer 233
In on gate nitridation dielectric layer 232.Second grid layer 234 is formed on gate oxidation dielectric layer 233.
In the present embodiment, first grid layer 231 and second grid layer 234 are to being electrically connected with as gate structure 23
Point comprising conductive material, such as, but not limited to metal or the polysilicon (Poly-Si) adulterated with p-type or N-type impurity.
The cross-sectional view of A regards it according to fig. 2, and from bottom to top, wall 24 includes spacer oxide layer 24b and spacer nitride layer
24a.Spacer oxide layer 24b is formed in outside the side wall of gate structure 23 and coats the side wall of gate structure 23.Spacer nitride layer
24a is formed in outside the side wall of spacer oxide layer 24b.In the present embodiment, spacer oxide layer 24b and spacer nitride layer 24a packet
Include insulating materials.
It should be noted that the invention is not limited to apply in above-mentioned gate structure and spacer layer configuration.For example,
Gate structure necessarily includes bigrid, and spacer layer configuration necessarily includes compound dual wall.
Then, as shown in Figure 2 B, on semiconductor stack stack structure 29 (that is, on the gate structure 23 and side of wall 24
Outside wall), form at least part for stacking coating 25.Wherein, in the present embodiment, it is formed and stacks at least the one of coating 25
Partial method includes the following steps.Be initially formed one first covering oxide layer 251 on semiconductor stack stack structure 29 (that is, in grid
In pole structure 23 and outside the side wall of wall 24).Then, a nitration case 252 is re-formed in the first covering oxide layer 251.Also
That is, " at least part for stacking coating 25 " includes nitration case 252.In one embodiment, nitration case 252 can be SixNyMaterial
Material.
The characteristics of the present embodiment is step as shown in Figure 2 C, before completing to stack coating 25, first removes nitration case
252 a part (that is, part shown in the arrow of Fig. 2 C).Step shown in fig. 2 C can be completed by lithographic with etching.
Then, as shown in Figure 2 D, one second covering oxide layer 253 is formed on the remainder of nitration case 252.So
One, complete all parts for stacking coating 25.Also that is, stacking coating 25 includes the first covering oxide layer 251, nitridation
The remainder of layer 252 and the second covering oxide layer 253.Particularly, the present embodiment is put be unlike the prior art: existing
In technology, it is seen from the lines AA ' of Figure 1A, from bottom to top, stacking coating 15 includes the first covering oxide layer 151, nitration case
152 and second covering oxide layer 153.However, in the present embodiment, the lines BB ' of D regards it according to fig. 2, from bottom to top, stack
Coating 25 includes the first covering oxide layer 251 and the second covering oxide layer 253, but does not then include nitrogen in the position of lines BB '
Change layer 252.
Then, as shown in Figure 2 E, in forming a protective layer 26, and etch protection layer 26 on stacking coating 25, to be formed
One aperture 261.In the present embodiment, the mode of etch protection layer 26 can be using dry-etching or wet etching, etc. tropisms
Etching or anisotropic etching, wherein the present embodiment can form above-mentioned aperture 261 using anisotropic etching, and specific embodiment can
To be that etching method is etched, but is not limited to using inductively coupled plasma (inductive coupling plasma, ICP)
This.
It is worth noting that, in the present embodiment, due to removing a part of nitration case 252 in Fig. 2 step C,
In Fig. 2 E, nitration case 252 because a part is removed without adjacent aperture 261, therefore, in the present embodiment, nitration case 252 not by
Aperture 261 exposes.
Then, as shown in Figure 2 F, it is passed through an etching material from aperture 261, wherein the present embodiment is with isotropic etching system
At mode etching substrate 21 to form the structure as depicted in Fig. 2 F, so far just complete with stack coating semiconductor
Element 20.In the present embodiment, etching material can be using gas or liquid mode, and the present embodiment is with sulfur hexafluoride
(SF6) or xenon difluoride (XeF2) be illustrated.
Significantly, since nitration case 252 is not exposed by aperture 261, and therefore, the remainder of nitration case 252
It is protected from the destruction of etching material.Therefore the overall structure of semiconductor element 20 is saved from damage.
Fig. 3 A-3E is please referred to, shows the process schematic cross-sectional view of second embodiment of the invention.It is noticeable
It is that the present embodiment is intended to illustrate main feature of the invention, therefore, the institute in the manufacturing method of the semiconductor element of general standard
Such as micro-photographing process step (not shown) that needs and ion implantation manufacture process step (not shown) or other and weight of the invention
The unrelated step of point has been well known to those skilled in the art, herein by it will not go into details.
As shown in Figure 3A, in the manufacturing method with the semiconductor element for stacking coating of the present embodiment, firstly, mentioning
Substrate 21, and in formation semiconductor stacked structure 29 on substrate 21.In 29 on semiconductor stack stack structure, a pile superimposition is formed
Cap rock 25.Semiconductor stack stack structure 29 includes a gate structure 23 and a wall 24.In one embodiment, semiconductor stack
The generation type of structure 29 is that can be prior to forming a shallow trench isolation (shallow trench on substrate 21
Isolation, STI) structure 22, later in formation gate structure 23 and wall 24 on sti structure 22.Shown in the present embodiment
Substrate 21, fleet plough groove isolation structure 22, gate structure 23 and wall 24 are all similar to above-mentioned first embodiment, refuse herein
It repeats.
Then, as shown in Figure 3B, on semiconductor stack stack structure 29 (that is, on the gate structure 23 and side of wall 24
Outside wall), form all parts for stacking coating 25.Wherein, in the present embodiment, all parts for stacking coating 25 are formed
Method and step include the following steps.Be initially formed one first covering oxide layer 251 on semiconductor stack stack structure 29 (that is, in grid
In pole structure 23 and outside the side wall of wall 24).Then, a nitration case 252 is re-formed in the first covering oxide layer 251.It connects
, one second covering oxide layer 253 is re-formed on nitration case 252.The all of coating 25 are stacked in this way, complete
Part.Also that is, stacking coating 25 includes the first covering oxide layer 251, nitration case 252 and the second covering oxide layer 253.
Then, as shown in Figure 3 C, in forming a protective layer 26, and etch protection layer 26 on stacking coating 25, to be formed
One aperture 261.It is real that the material of protective layer 26 and the generation type of aperture 261 shown in the present embodiment are all similar to above-mentioned first
Example is applied, it will not be described here.
Then, as shown in Figure 3D, the side wall of Yu Kaikong 261 forms a protection oxide layer 272.
Then, as shown in FIGURE 3 E, it is passed through an etching material from aperture 261, wherein the present embodiment is with isotropic etching system
At mode etching substrate 21 to form the structure as depicted in Fig. 3 E, so far just complete with stack coating semiconductor
Element 30.Similar to above-mentioned first embodiment, etching material be can be using gas or liquid mode, the present embodiment be with
Sulfur hexafluoride (SF6) or xenon difluoride (XeF2) be illustrated.
It is worth noting that, the present embodiment is unlike the prior art shown in Figure 1B: the prior art shown in Figure 1B
In, the side wall of aperture 161 does not form any other materials.However, in Fig. 3 D of the present embodiment, due to the side of aperture 261
Wall has protection oxide layer 272, and since protection oxide layer 272 can be resistant to etching material sulfur hexafluoride (SF6) or bifluoride
Xenon (XeF2) etching, therefore the overall structure of semiconductor element 30 is saved from damage.
In one embodiment, the manufacturing method of the semiconductor element of this case can be applied to manufacture infrared temperature sensing module
In temperature sensor.
Illustrate the present invention for preferred embodiment above, it is only described above, only make those skilled in the art easy
In the understanding contents of the present invention, interest field not for the purpose of limiting the invention.Under same spirit of the invention, this field skill
Art personnel can think and various equivalence changes.All this kind, according to the present invention can all teach and analogize and obtain, therefore, the present invention
Range should cover above-mentioned and other all equivalence changes.In addition, any implementation kenel of the invention necessarily reach it is all
Purpose or advantage, therefore, any one of claim also should not be as limits.
Claims (6)
1. a kind of manufacturing method of semiconductor element characterized by comprising
One substrate is provided；
In formation semiconductor stacked structure on the substrate；
In forming a pile superimposition cap rock on the semiconductor stack stack structure, wherein the stacking coating includes a nitration case；
In forming a protective layer on the stacking coating, and the protective layer is etched, to form an at least aperture, wherein the aperture is sudden and violent
Expose at least partly nitration case；
A protection oxide layer is formed in the side wall of the aperture, to cover at least partly nitration case；And
It is passed through an etching material from the aperture, to etch the substrate.
2. the manufacturing method of semiconductor element as described in claim 1, wherein in forming the semiconductor stack knot on the substrate
The method of structure includes:
In forming an insulation structure of shallow groove on the substrate, and in being formed between a gate structure and one on the insulation structure of shallow groove
Interlayer.
3. the manufacturing method of semiconductor element as claimed in claim 2, wherein the method for forming the gate structure includes:
A first grid layer is formed on the insulation structure of shallow groove；
A gate nitridation dielectric layer is formed on the first grid layer；
A gate oxidation dielectric layer is formed on the gate nitridation dielectric layer；And
A second grid layer is formed on the gate oxidation dielectric layer.
4. the manufacturing method of semiconductor element as claimed in claim 2, wherein the method for forming the wall includes:
One spacer oxide layer, is formed in outside the side wall of the gate structure；And
One spacer nitride layer, is formed in outside the side wall of the spacer oxide layer.
5. the manufacturing method of semiconductor element as claimed in claim 2, wherein in forming the heap on the semiconductor stack stack structure
The method of superimposition cap rock includes:
One first covering oxide layer is formed on the semiconductor stack stack structure；
The nitration case is formed in the first covering oxide layer；And
One second covering oxide layer is formed on the nitration case.
6. the manufacturing method of semiconductor element as described in claim 1, wherein the etching material includes sulfur hexafluoride or difluoro
Change xenon.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910433747.9A CN110120340B (en) | 2015-06-16 | 2015-06-16 | Semiconductor device and method for manufacturing the same |
| CN201510332823.9A CN106257622B (en) | 2015-06-16 | 2015-06-16 | Semiconductor element and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510332823.9A CN106257622B (en) | 2015-06-16 | 2015-06-16 | Semiconductor element and its manufacturing method |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910433747.9A Division CN110120340B (en) | 2015-06-16 | 2015-06-16 | Semiconductor device and method for manufacturing the same |
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| Publication Number | Publication Date |
|---|---|
| CN106257622A CN106257622A (en) | 2016-12-28 |
| CN106257622B true CN106257622B (en) | 2019-06-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201910433747.9A Active CN110120340B (en) | 2015-06-16 | 2015-06-16 | Semiconductor device and method for manufacturing the same |
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