CN112510078A - Semiconductor based on nano material and preparation method - Google Patents
Semiconductor based on nano material and preparation method Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 239000002086 nanomaterial Substances 0.000 title claims abstract description 19
- 238000002360 preparation method Methods 0.000 title claims description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000001312 dry etching Methods 0.000 claims abstract description 19
- 238000001039 wet etching Methods 0.000 claims abstract description 10
- 230000005641 tunneling Effects 0.000 claims abstract description 9
- 230000008569 process Effects 0.000 claims abstract description 8
- 238000004140 cleaning Methods 0.000 claims abstract description 7
- 239000002253 acid Substances 0.000 claims abstract description 5
- 150000004767 nitrides Chemical class 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 8
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 6
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229920001665 Poly-4-vinylphenol Polymers 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- FRIKWZARTBPWBN-UHFFFAOYSA-N [Si].O=[Si]=O Chemical compound [Si].O=[Si]=O FRIKWZARTBPWBN-UHFFFAOYSA-N 0.000 claims description 3
- 230000009471 action Effects 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 239000012528 membrane Substances 0.000 claims description 3
- 229920000620 organic polymer Polymers 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 6
- 230000000903 blocking effect Effects 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 5
- 230000006872 improvement Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- -1 etc. Chemical compound 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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Abstract
The invention relates to the technical field of semiconductors, in particular to a semiconductor based on a nano material, which comprises a semiconductor body, wherein the semiconductor body comprises a lower insulating layer and a mask, a base body is arranged on the outer wall of the top of the lower insulating layer, a blocking layer is arranged on the outer wall of the top of the base body, a tunneling oxide layer is arranged on the outer wall of the top of the blocking layer, a floating gate is arranged on the outer wall of the top of the tunneling oxide layer, an ONO layer is arranged on the outer wall of the top of the floating gate, and a control gate layer is arranged on the outer wall. The invention has the beneficial effects that: the method adopts acid to carry out wet etching, easily removes a nitride layer of the ONO layer, reduces the influence caused by over-etching, realizes the function of cleaning the side wall of the ONO layer, prevents the defects of fences and small holes, adopts dry etching which is the balanced result of two processes of physics and chemistry on the surface of the wafer, and uses the dry etching to etch the barrier layer and the mask, thereby having better effect and better selectivity.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor based on a nanometer material and a preparation method thereof.
Background
Semiconductor (Semiconductor) is a substance with conductivity between insulator and conductor, which is easy to control, and can be used as a component material for information processing, and is very important from the viewpoint of technological or economic development, and many electronic products, such as computers, mobile phones, and digital recorders, utilize the conductivity change of Semiconductor to process information, and the common Semiconductor materials include silicon, germanium, gallium arsenide, etc., and silicon is the most influential one of various Semiconductor materials in commercial applications.
Chinese patent No. CN102456613B provides a method for manufacturing a semiconductor structure, in which a second dielectric layer is covered on a first dielectric layer, a first contact hole with a smaller inner diameter is formed in the second dielectric layer, then the first dielectric layer is etched to form a second contact hole with a larger inner diameter, and finally a conductive material is filled in the first contact hole and the second contact hole to form a contact plug.
However, in a method for manufacturing a semiconductor structure, the silicon nitride layer etched to the ONO layer is difficult to etch, which leaves residues on the etched sidewall, resulting in a fence-like shape in the finally formed semiconductor device, and due to the disadvantage of the silicon nitride layer that is difficult to etch, the tunnel oxide layer 130 under the polysilicon layer on the side of the silicon nitride layer may be affected during the etching process, resulting in a void, and meanwhile, the tunnel oxide layer and the tunnel oxide layer are protected without using a mask, resulting in damage to the tunnel oxide layer and the tunnel oxide layer during the etching process, which is not suitable for wide popularization.
Disclosure of Invention
The present invention is directed to provide a semiconductor based on nano-materials and a method for manufacturing the same, so as to solve the problems of the related art that a layer of silicon nitride etched to an ONO layer is difficult to etch, which leaves residues on the etched sidewall, resulting in a fence-like shape left in a finally formed semiconductor device, and that a tunnel oxide layer 130 under polysilicon on the side of the ONO layer is affected during etching due to the disadvantage of the difficult etching of the silicon nitride of the ONO layer, thereby causing a void, and that a tunnel oxide layer and a tunnel oxide layer are protected without using a mask, which may cause damage to the tunnel oxide layer and the tunnel oxide layer during etching.
The technical scheme of the invention is as follows: the utility model provides a semiconductor based on nano-material, includes the semiconductor body, the semiconductor body includes insulating layer and mask down, and is provided with the base member on the outer wall at insulating layer top down, be provided with the barrier layer on the outer wall at base member top, and be provided with the tunnel oxide layer on the outer wall at barrier layer top, be provided with the floating gate on the outer wall at tunnel oxide layer top, and be provided with the ONO layer on the outer wall at floating gate top, be provided with the control gate layer on the outer wall at ONO layer top, and be provided with the ethyl orthosilicate layer on the outer wall at control gate layer top, be provided with the insulating layer on the outer wall at ethyl orthosilicate layer top.
Further, the substrate is a carbon nano material.
Further, the material of the tunnel oxide layer may be silicon dioxide.
Further, the material of the lower insulating layer and the upper insulating layer may be inorganic, such as silicon dioxide, aluminum oxide, silicon nitride, etc., or may be organic polymer, such as polymethyl methacrylate (PMMA) or polyvinyl phenol PVP.
Further, the ONO layer is a silicon dioxide-silicon nitride-silicon dioxide three-layer combination.
Further, SC1 or SC2 is selected when etching the nitride layer in the ONO layer, and the heat of acid is 60-70 ℃.
Further, the mask material may be silicon nitride.
Furthermore, the floating gate and the control gate layer are made of polysilicon.
Further, the mask is formed by processing using a semi-permeable membrane or a diffractive exposure method.
A preparation method of a semiconductor based on nanometer materials comprises the following steps:
s1: covering a substrate on the surface of the lower insulating layer;
s2: covering a barrier layer on the surface of the substrate;
s3: covering a mask on the surface of the barrier layer, and etching the barrier layer into a shallow trench isolation structure by using dry etching;
s4: then, etching the barrier layer and the substrate by using dry etching to form a deep trench isolation structure so as to remove, etch and remove the barrier layer which is not covered by the mask and etch the mask into a patterned mask, and performing hole digging action in the etching process;
s5: reserving a mask and covering the ONO layer on the surface of the mask;
s6: respectively covering the floating gate on the surface of the tunneling oxide layer, covering the ONO layer on the surface of the control gate layer, covering a mask on the surface of the ONO layer, etching the ONO layer by wet etching, and removing the patterned mask by cleaning;
s7: and covering the control gate layer with an ethyl orthosilicate layer, and finally covering the surface of the ethyl orthosilicate layer with an upper insulating layer.
The invention provides a semiconductor based on nanometer material and a preparation method thereof through improvement, compared with the prior art, the semiconductor based on nanometer material has the following improvement and advantages:
(1) the method of wet etching by acid is adopted, so that the nitride layer of the ONO layer is easily removed, the influence caused by over-etching is reduced, the effect of cleaning the side wall of the ONO layer is realized, and the defects of fences and small holes are prevented.
(2) The dry etching is a technique for etching a film by using plasma, and when gas exists in a plasma form, the dry etching has two characteristics: on one hand, the chemical activity of the gases in the plasma is much stronger than that of the gases in a normal state, and the gases can react with the materials more quickly by selecting proper gases according to the difference of the etched materials, so that the aim of etching removal is fulfilled; on the other hand, the electric field can be used for guiding and accelerating the plasma, so that the plasma has certain energy, and when the plasma bombards the surface of the etched object, atoms of the etched object material can be knocked out, thereby achieving the purpose of etching by utilizing physical energy transfer. Therefore, the dry etching is a result of balancing the physical and chemical processes of the surface of the wafer, and the barrier layer and the mask are etched by using the dry etching, so that the effect is better, and the selectivity is better.
(3) The adopted mask is used for protecting the blocking layer and the ONO layer before the dry etching of the substrate, the blocking layer and the tunnel oxide layer and before the wet etching of the ONO layer, so that the damage to the tunnel oxide layer and the ONO layer during the dry etching and before the wet etching can be avoided.
Drawings
The invention is further explained below with reference to the figures and examples:
FIG. 1 is a schematic perspective view of a semiconductor structure according to the present invention;
FIG. 2 is a schematic view of the shallow trench structure in the semiconductor of the present invention;
FIG. 3 is a schematic diagram of the semiconductor internal deep trench structure of the present invention;
fig. 4 is a schematic view of the internal structure of the present invention.
Description of reference numerals:
1 semiconductor body, 2 lower insulating layers, 3 substrates, 4 blocking layers, 5 tunneling oxide layers, 6 floating gates, 7 control gate layers, 8 ethyl orthosilicate layers, 9 upper insulating layers, 10 masks and 11 ONO layers.
Detailed Description
The present invention will be described in detail with reference to fig. 1 to 4, and the technical solutions in the embodiments of the present invention will be clearly and completely described, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When a component is referred to as being "disposed on" another component, it can be directly on the other component or intervening components may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The invention provides a semiconductor based on a nano material through improvement, as shown in fig. 1-4, the semiconductor based on the nano material comprises a semiconductor body 1, the semiconductor body 1 comprises a lower insulating layer 2 and a mask 10, a base body 3 is arranged on the outer wall of the top of the lower insulating layer 2, a barrier layer 4 is arranged on the outer wall of the top of the base body 3, a tunneling oxide layer 5 is arranged on the outer wall of the top of the barrier layer 4, a floating gate 6 is arranged on the outer wall of the top of the tunneling oxide layer 5, an ONO layer 11 is arranged on the outer wall of the top of the floating gate 6, a control gate layer 7 is arranged on the outer wall of the top of the ONO layer 11, an ethyl orthosilicate layer 8 is arranged on the outer wall of the top of the control gate layer 7, and an upper insulating layer 9 is arranged on.
Further, the substrate 3 is a carbon nanomaterial.
Further, the material of tunnel oxide layer 5 may be silicon dioxide.
Further, the material of the lower insulating layer 2 and the upper insulating layer 9 may be inorganic, such as silicon dioxide, aluminum oxide, silicon nitride, etc., or may be organic polymer, such as polymethyl methacrylate (PMMA) or polyvinyl phenol PVP.
Further, the ONO layer 11 is a silicon dioxide-silicon nitride-silicon dioxide triple layer combination.
Further, SC1 or SC2 is selected when etching the nitride layer in the ONO layer 11, and the heat of acid is 60-70 degrees.
Further, the mask 10 material may be silicon nitride.
Further, the material of the floating gate 6 and the control gate layer 7 is polysilicon.
Further, the mask 10 is formed by processing through a semi-permeable membrane or a diffraction exposure mode, the mask 10 is reserved in the preparation process, and the barrier layer 4, the ONO layer and the base layer 3 are protected from being polluted in the preparation processes of etching or cleaning the barrier layer 4 and the ONO layer.
A preparation method of a semiconductor based on nanometer materials comprises the following steps:
s1: covering the substrate 3 on the surface of the lower insulating layer 2;
s2: covering a barrier layer 4 on the surface of the substrate 3;
s3: covering a mask 10 on the surface of the barrier layer 4, and etching the barrier layer 4 into a shallow trench isolation structure by using dry etching;
s4: then, etching the barrier layer 4 and the substrate 3 to form a deep trench isolation structure by using dry etching, so as to remove, etch and remove the barrier layer 4 which is not covered by the mask 10 and etch the mask 10 into a patterned mask, wherein hole digging is performed in the etching process, and the dry etching etches the barrier layer 4 and the mask 10, so that the effect is better and the selectivity is better;
s5: the mask 10 is reserved, and the ONO layer 11 covers the surface of the mask 10 to play a role in protection;
s6: respectively covering the floating gate 6 on the surface of the tunneling oxide layer 5, covering the ONO layer 11 on the surface of the control gate layer 7, covering the mask 10 on the surface of the ONO layer 11, etching the ONO layer 11 by wet etching, and removing the patterned mask 10 by cleaning, so that fence and small hole defects on the side wall of the ONO layer 11 can be prevented;
s7: an ethyl orthosilicate layer 8 is covered on the control gate layer 7, and finally an upper insulating layer 9 is covered on the surface of the ethyl orthosilicate layer 8.
The working principle of the invention is as follows: respectively covering a substrate 3 on the surface of the lower insulating layer 2, covering a barrier layer 4 on the surface of the substrate 3 and covering a mask 10 on the surface of the barrier layer 4, and etching the barrier layer 4 into a shallow trench isolation structure by dry etching; then, dry etching is adopted, the barrier layer 4 and the substrate 3 are etched to form a deep trench isolation structure so as to remove, etch and remove the barrier layer 4 which is not covered by the mask 10 and etch the mask 10 into a patterned mask, and a hole digging action is carried out in the etching process to dig out etched substances; the mask 10 is reserved, and then the ONO layer 11 is covered on the surface of the mask 10; then covering the floating gate 6 on the surface of the tunneling oxide layer 5, covering the ONO layer 11 on the surface of the control gate layer 7, covering the mask 10 on the surface of the ONO layer 11, etching the ONO layer 11 by wet etching, and removing the patterned mask 10 by cleaning; the control gate layer 7 is covered with the ethyl orthosilicate layer 8, the upper insulating layer 9 is covered on the surface of the ethyl orthosilicate layer 8, the barrier layer 4 and the mask 10 can be etched in a dry etching mode in a mixed mode of dry etching and wet etching, the effect is better, better selectivity is achieved, and the problem that fence and small hole defects occur on the side wall of the ONO layer 11 can be solved through wet etching.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A nanomaterial-based semiconductor, characterized in that: including semiconductor body (1), semiconductor body (1) includes insulating layer (2) and mask (10) down, and is provided with base member (3) on the outer wall at insulating layer (2) top down, be provided with barrier layer (4) on the outer wall at base member (3) top, and be provided with on the outer wall at barrier layer (4) top and tunnel oxide layer (5), be provided with floating gate (6) on the outer wall at tunnel oxide layer (5) top, and be provided with ONO layer (11) on the outer wall at floating gate (6) top, be provided with control gate layer (7) on the outer wall at ONO layer (11) top, and be provided with ethyl orthosilicate layer (8) on the outer wall at control gate layer (7) top, be provided with insulating layer (9) on the outer wall at ethyl orthosilicate layer (8) top.
2. The method of claim 1, wherein the nanomaterial-based semiconductor is prepared by: the substrate (3) is made of carbon nano materials.
3. The method of claim 1, wherein the nanomaterial-based semiconductor is prepared by: the material of the tunnel oxide layer (5) may be silicon dioxide.
4. The method of claim 1, wherein the nanomaterial-based semiconductor is prepared by: the material of the lower insulating layer (2) and the upper insulating layer (9) can be inorganic substances, such as silicon dioxide, aluminum oxide, silicon nitride and the like, and can also be organic polymers, such as polymethyl methacrylate (PMMA) or polyvinyl phenol (PVP).
5. The method of claim 1, wherein the nanomaterial-based semiconductor is prepared by: the ONO layer (11) is a silicon dioxide-silicon nitride-silicon dioxide three-layer combination.
6. The method of claim 1, wherein the nanomaterial-based semiconductor is prepared by: SC1 or SC2 is selected when etching the nitride layer in the ONO layer (11), and the heat of acid is 60-70 ℃.
7. The method of claim 1, wherein the nanomaterial-based semiconductor is prepared by: the mask (10) material may be silicon nitride.
8. The method of claim 1, wherein the nanomaterial-based semiconductor is prepared by: the floating gate (6) and the control gate layer (7) are made of polysilicon.
9. The method of claim 1, wherein the nanomaterial-based semiconductor is prepared by: the mask (10) is formed by processing using a semi-permeable membrane or a diffractive exposure method.
10. A preparation method of a semiconductor based on nanometer materials is characterized in that: the method comprises the following steps:
s1: covering the surface of the lower insulating layer (2) with a substrate (3);
s2: covering a barrier layer (4) on the surface of the substrate (3);
s3: covering a mask (10) on the surface of the barrier layer (4), and etching the barrier layer (4) into a shallow trench isolation structure by using dry etching;
s4: then, etching the barrier layer (4) and the substrate (3) by using dry etching to form a deep trench isolation structure so as to remove, etch and remove the barrier layer (4) which is not covered by the mask (10) and etch the mask (10) into a patterned mask, and performing hole digging action in the etching process;
s5: retaining the mask (10) and covering the ONO layer (11) on the surface of the mask (10);
s6: respectively covering the floating gate (6) on the surface of the tunneling oxide layer (5), covering the ONO layer (11) on the surface of the control gate layer (7), covering the mask (10) on the surface of the ONO layer (11), etching the ONO layer (11) by wet etching, and removing the patterned mask (10) by cleaning;
s7: and covering the control gate layer (7) with an ethyl orthosilicate layer (8), and finally covering the surface of the ethyl orthosilicate layer (8) with an upper insulating layer (9).
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| KR20040060583A (en) * | 2002-12-30 | 2004-07-06 | 주식회사 하이닉스반도체 | Method for manufacturing of flash memory device |
| KR20100078114A (en) * | 2008-12-30 | 2010-07-08 | 주식회사 동부하이텍 | Mathod of fabricating flash memory device |
| US20130015517A1 (en) * | 2010-02-07 | 2013-01-17 | Yuniarto Widjaja | Semiconductor Memory Device Having Electrically Floating Body Transistor, Semiconductor Memory Device Having Both Volatile and Non-Volatile Functionality and Method of Operating |
| CN110854121A (en) * | 2019-11-27 | 2020-02-28 | 上海华力微电子有限公司 | Semiconductor manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040060583A (en) * | 2002-12-30 | 2004-07-06 | 주식회사 하이닉스반도체 | Method for manufacturing of flash memory device |
| KR20100078114A (en) * | 2008-12-30 | 2010-07-08 | 주식회사 동부하이텍 | Mathod of fabricating flash memory device |
| US20130015517A1 (en) * | 2010-02-07 | 2013-01-17 | Yuniarto Widjaja | Semiconductor Memory Device Having Electrically Floating Body Transistor, Semiconductor Memory Device Having Both Volatile and Non-Volatile Functionality and Method of Operating |
| CN110854121A (en) * | 2019-11-27 | 2020-02-28 | 上海华力微电子有限公司 | Semiconductor manufacturing method |
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