CN106253753B - Semiconductor device with a plurality of semiconductor chips - Google Patents
Semiconductor device with a plurality of semiconductor chips Download PDFInfo
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- CN106253753B CN106253753B CN201610300672.3A CN201610300672A CN106253753B CN 106253753 B CN106253753 B CN 106253753B CN 201610300672 A CN201610300672 A CN 201610300672A CN 106253753 B CN106253753 B CN 106253753B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P1/00—Arrangements for starting electric motors or dynamo-electric converters
- H02P1/16—Arrangements for starting electric motors or dynamo-electric converters for starting dynamo-electric motors or dynamo-electric converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
- H03K17/08122—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P31/00—Arrangements for regulating or controlling electric motors not provided for in groups H02P1/00 - H02P5/00, H02P7/00 or H02P21/00 - H02P29/00
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/08112—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in bipolar transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0081—Power supply means, e.g. to the switch driver
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electronic Switches (AREA)
- Emergency Protection Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Power Conversion In General (AREA)
Abstract
The invention provides a semiconductor device in which the temperature of a power semiconductor element does not increase rapidly even if a load short circuit occurs. When a motor (2) is started, a charge pump circuit (12) generates a gate voltage at which a surge current can flow through a power semiconductor element (11), and when a predetermined time (time until the end of the surge current) has elapsed since the start of the motor (2), a timer circuit (16) operates a gate clamp circuit (17), and the gate clamp circuit (17) reduces the current carrying capacity of the power semiconductor element (11) by suppressing the gate voltage of the power semiconductor element (11). When a short-circuit accident occurs in the motor (2), the gate voltage of the power semiconductor element (11) is reduced by the gate clamp circuit (17) in advance, and therefore only a load short-circuit current corresponding to the reduced gate voltage flows. This reduces heat generation due to the short-circuit current, and also suppresses temperature rise.
Description
Technical Field
The present invention relates to a semiconductor device including a power semiconductor element for controlling a motor or the like, and more particularly, to a semiconductor device for protecting a power semiconductor element from thermal damage when an overcurrent flows due to a short circuit of a load.
Background
A motor and a semiconductor device for controlling the switching of the motor are often mounted in an automobile, and there is a demand for further miniaturization of the semiconductor device and improvement in reliability thereof in accordance with an increase in temperature of a temperature environment. In order to cope with the miniaturization and high reliability of semiconductor devices, a single-chip semiconductor device or a single-package semiconductor device in which a power semiconductor element and a driving circuit for driving the power semiconductor element are integrated into one chip or one package has been developed. The drive circuit includes a control circuit and a protection circuit for protecting the power semiconductor element. The protection circuit monitors, for example, an overheat state of the power semiconductor element, and when the overheat state is detected, notifies the control circuit of the overheat state. The control circuit performs control such as turning off the power semiconductor element when receiving a notification of an overheat state of the power semiconductor element from the protection circuit. The semiconductor device further includes an overcurrent limiting circuit that monitors a current flowing through the power semiconductor element. The overcurrent limiting circuit comprises the following circuits: that is, a circuit that indirectly detects a current flowing through the power semiconductor element and limits the current flowing through the power semiconductor element when the detected current value measures a set overcurrent limit value (see, for example, patent document 1).
Here, in a semiconductor device that performs switching control of an inductive load such as a motor, a surge current flows at the time of starting the motor. That is, when the power semiconductor element is turned on, a current starts to flow through the power semiconductor element and the motor. At this time, the current initially flowing is a current larger than the current value at the time of steady operation, and then the current gradually decreases to be fixed at a steady rated current, and a large current flowing until the current reaches the rated current is an inrush current. Therefore, the power semiconductor element is controlled so as to be able to supply a current in consideration of such a surge current as described above to the motor at the time of on control thereof.
Documents of the prior art
Patent document
Patent document 1: japanese patent laid-open No. Hei 11-195971
Disclosure of Invention
Technical problem to be solved by the invention
However, when the load is driven at its rated current, if a short-circuit accident occurs in the load, a current at least larger than the inrush current continues to flow through the power semiconductor element, and therefore the temperature of the power semiconductor element rapidly rises. In this case, before the protection circuit detects the overheat state and starts the protection operation of the power semiconductor element, the temperature may rise to a temperature at which the power semiconductor element is thermally destroyed. Further, since such a large current flows, there is a possibility that burning of the wiring board, malfunction of peripheral devices due to variation in power supply voltage, and the like may occur. In addition, in a semiconductor device including an overcurrent limiting circuit, since the overcurrent limiting value is set to be larger than the peak value of the inrush current, even when the load is short-circuited, a current larger than the peak value of the inrush current continues to flow through the power semiconductor element. In this case, there is a problem that the power semiconductor element is thermally broken due to a rapid temperature increase because the temperature of the power semiconductor element rapidly increases.
The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device in which a rapid temperature rise of a power semiconductor element does not occur even if a load short circuit occurs.
Means for solving the problems
In order to solve the above problem, the present invention provides a semiconductor device including a driving circuit for driving a power semiconductor element. In the semiconductor device, the drive circuit includes: a gate clamping circuit that clamps a gate voltage of the power semiconductor element; and a timer circuit that starts counting when the power semiconductor element is energized, wherein the timer circuit operates the gate clamp circuit after a predetermined time has elapsed from the start of counting, thereby reducing a current carrying capacity of the power semiconductor element.
Effects of the invention
In the semiconductor device having the above configuration, since the current carrying capacity of the power semiconductor element is reduced after a predetermined time has elapsed from the start of energization of the power semiconductor element, there is an advantage that a short-circuit current can be reduced when a load short-circuit occurs. Thus, the power semiconductor element does not undergo a rapid temperature rise due to a short-circuit current, burning of the power semiconductor element and the substrate wiring can be prevented, and a malfunction of a peripheral device due to a variation in power supply voltage can be prevented, thereby ensuring high reliability. Further, since the current carrying capability of the power semiconductor element is not reduced when the surge current is applied, unnecessary heat generation of the power semiconductor element can be prevented.
Drawings
Fig. 1 is a circuit configuration diagram showing a semiconductor device according to embodiment 1.
Fig. 2 is a circuit diagram showing a configuration example of a charge pump circuit of the semiconductor device according to embodiment 1.
Fig. 3 is a circuit diagram showing a configuration example of a gate clamp circuit of the semiconductor device according to embodiment 1.
Fig. 4 is a diagram showing an operation waveform when the motor operates.
Fig. 5 is a diagram showing an operation waveform in a case where a load short circuit occurs during the operation of the motor.
Fig. 6 is a diagram showing an example of static characteristics of a power MOSFET.
Fig. 7 is a circuit configuration diagram showing the semiconductor device according to embodiment 2.
Fig. 8 is a circuit configuration diagram showing the semiconductor device according to embodiment 3.
Fig. 9 is a circuit diagram showing a configuration example of a charge pump circuit of the semiconductor device according to embodiment 3.
Fig. 10 is a circuit diagram showing an example of an oscillation circuit constituting a charge pump circuit of the semiconductor device according to embodiment 4.
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, taking as an example a case where the present invention is applied to a semiconductor power switch for driving a vehicle-mounted motor. The embodiments can be implemented by combining a plurality of embodiments within a range not to be contradictory. In the following description, the same reference numerals are used for the names of the terminals and the voltages, signals, and the like applied to the terminals.
Fig. 1 is a circuit configuration diagram showing a semiconductor device according to embodiment 1.
The semiconductor device 10 according to embodiment 1 is an IPS (INTELLIGENT POWER SWITCH: smart power switch) in which a power semiconductor element 11 for driving a motor and a driving circuit for driving the power semiconductor element 11 are integrated into a single chip or a single package. The semiconductor device 10 is disposed between the positive electrode terminal of the power source 1 and the motor 2, and is referred to as a high side IPS.
In the Semiconductor device 10, a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is used as the power Semiconductor element 11, but the power MOSFET is not limited to use. For example, another power device such as an IGBT (Insulated Gate Bipolar Transistor) may be used as the power semiconductor element 11.
The power semiconductor element 11 has a drain connected to a terminal VCC, which is an in-vehicle battery, connected to the positive terminal of the power supply 1, and a source connected to a terminal OUT connected to the motor 2. The gate of the power semiconductor element 11 is connected to the output of the charge pump circuit 12 for boosting the gate voltage, the input of the charge pump circuit 12 having the potential of the terminal GND as a reference potential is connected to the output of the control circuit 13 having the potential of the terminal GND as a reference potential, and the input of the control circuit 13 is connected to the terminal IN. The control circuit 13 is also connected to a protection circuit 14 having the potential of the terminal GND (or the internal GND) as a reference potential. The protection circuit 14 detects whether the power semiconductor element 11 is in an overheated state or whether the power supply voltage at the terminal VCC is reduced, for example, and notifies the control circuit 13 of the operation when such a state is detected. By applying a voltage equal to or higher than a predetermined voltage (threshold voltage) with respect to the potential of the terminal OUT to the gate of the power semiconductor element 11, the power semiconductor element 11 can be turned on. Therefore, the output voltage of the charge pump circuit 12 is set in consideration of the potential of the terminal OUT. The internal GND is generated by a power supply line of a voltage VCC (not shown). The potential of the internal GND is lower than the power supply VCC (for example, 12V) by a predetermined voltage (for example, 5V).
The control circuit 13 is further connected to the gate of the power MOSFET15 and to an input of the timer circuit 16. The power MOSFET15 has a drain and a source connected to the gate and the source of the power semiconductor device 11, respectively, and is used to take out the charge charged to the gate capacitance thereof to shorten the switching time when the power semiconductor device 11 is turned off.
The output of the timer circuit 16 is connected to the input of the gate clamp circuit 17, and the output of the gate clamp circuit 17 is connected to the gate of the power semiconductor element 11. The timer circuit 16 starts counting when a signal for turning on the power semiconductor element 11 is input to the terminal IN as an input of the control circuit 13, and outputs a signal for operating the gate clamp circuit 17 after a lapse of a certain time (inrush current supply time). The gate clamp circuit 17 receives a signal from the timer circuit 16, and clamps the gate voltage of the power semiconductor element 11, thereby reducing the current carrying capacity of the power semiconductor element 11.
Since the timer circuit 16 operates with the potential of the terminal GND (or the internal GND) as a reference potential and the gate clamp circuit 17 operates with the potential of the terminal OUT as a reference potential, signal transmission from the timer circuit 16 to the gate clamp circuit 17 is performed by a level shift circuit. The terminal GND of the semiconductor device 10 is connected to the body of the vehicle.
Fig. 2 is a circuit diagram showing a configuration example of a charge pump circuit of the semiconductor device according to embodiment 1.
The charge pump circuit 12 includes an oscillation circuit (oscillator) 21 that oscillates based on a signal output from the control circuit 13, an inverter 22 that logically inverts the signal oscillated by the oscillation circuit 21, and a booster circuit (multistage booster) 23 composed of, for example, three stages.
The oscillation circuit 21 receives a logic signal for turning on or off the power semiconductor element 11 from the control circuit 13, performs an oscillation operation only when a start signal for turning on the power semiconductor element 11 is received, and outputs an oscillation signal.
The inverter 22 inverts the oscillation signal output from the oscillation circuit 21 and outputs the inverted oscillation signal.
In the booster circuit 23, the first stage includes an inverter 24, a capacitor 25, and two diodes 26, 27, the second stage includes an inverter 28, a capacitor 29, and two diodes 30, 31, and the third stage includes an inverter 32, a capacitor 33, and two diodes 34, 35.
The input of the inverter 24 of the first stage is connected to the output of the inverter 22, the output of the inverter 24 is connected to one terminal of the capacitor 25, and the other terminal of the capacitor 25 is connected to the cathode of the diode 26 and the anode of the diode 27. The anode of the diode 26 is connected to the power supply line for the voltage VCC. The power supply line of the voltage VCC is connected to a terminal VCC of the semiconductor device 10.
The input of the inverter 28 of the second stage is connected to the output of the oscillation circuit 21, the output of the inverter 28 is connected to one terminal of the capacitor 29, and the other terminal of the capacitor 29 is connected to the cathode of the diode 30, the anode of the diode 31, and the cathode of the diode 27 of the first stage. The anode of the diode 30 is connected to a power supply line of the voltage VCC.
The input of the inverter 32 of the third stage is connected to the output of the inverter 22, the output of the inverter 32 is connected to one terminal of the capacitor 33, and the other terminal of the capacitor 33 is connected to the cathode of the diode 34 and the anode of the diode 35. The anode of the diode 34 is connected to the power supply line of the voltage VCC, and the cathode of the diode 35 constitutes the output of the charge pump circuit 12.
According to the charge pump circuit 12 having the above configuration, the oscillation circuit 21 starts an oscillation operation by receiving a start signal of the power semiconductor element 11 from the control circuit 13. When the signal output from the oscillation circuit 21 is at L (low) level, for example, the signal is inverted by the inverter 22 to H (high) level and then input to the inverter 24 at the first stage of the booster circuit 23. Thus, since the output of the inverter 24 is at the L level, one terminal of the capacitor 25 is connected to the ground GND, and the capacitor 25 is charged by the voltage VCC of the power supply line via the diode 26. As a result, the terminal voltage of the capacitor 25 is made VCC-Vf (Vf is the forward voltage of the diode 26).
When the signal output from the oscillation circuit 21 is at the H (high) level, for example, the signal is inverted by the inverter 22 to the L (low) level and then input to the inverter 24 at the first stage of the booster circuit 23. Thus, since the output of the inverter 24 is at the H level, the voltage VCC of the power supply line is applied to one terminal of the capacitor 25, and as a result, the voltage of the other terminal of the capacitor 25 is set to 2 VCC-Vf. At this time, the signal of the H level is input to the inverter 28 of the second stage of the booster circuit 23, and therefore, the output of the inverter 28 becomes the L level. Thus, one terminal of the capacitor 29 is connected to the ground GND, and the other terminal of the capacitor 29 is applied with a voltage of 2VCC-Vf via the diode 27 of the first stage. As a result, the terminal voltage of the capacitor 29 is set to 2VCC-2Vf (Vf is the forward voltage of the diodes 26 and 27, and has the same value).
Next, when the signal output from the oscillation circuit 21 is at the L level, the signal is input to the inverter 28 at the second stage, and the output of the inverter 28 is at the H level, that is, the voltage VCC of the power supply line. As a result, the voltage at the other terminal of the capacitor 29 is 3VCC-2Vf obtained by adding VCC to the voltage of 2VCC-2 Vf. At this time, since the H-level signal is input to the inverter 32 of the third stage of the booster circuit 23, the output of the inverter 32 becomes L-level. Thereby, one terminal of the capacitor 33 is connected to the ground GND, and the other terminal of the capacitor 33 is applied with a voltage of 3VCC-2Vf via the diode 31 of the second stage. As a result, the terminal voltage of the capacitor 33 is set to 3VCC-3Vf (Vf is the forward voltage of the diodes 26, 27, 31, and has the same value). The voltage boosted in this manner is output to the output of the charge pump circuit 12 via the diode 35. The output signal can be continuously obtained by alternately repeating the L level and the H level of the signal output from the oscillation circuit 21, and becomes the gate voltage of the power semiconductor element 11.
Fig. 3 is a circuit diagram showing a configuration example of a gate clamp circuit of the semiconductor device according to embodiment 1.
The gate clamp circuit 17 has a diode group 41 and a MOSFET 42. The diode group 41 is configured by connecting a plurality of diodes in series, the anode of the diode group 41 being connected to the gate of the power semiconductor element 11, and the cathode of the diode group 41 being connected to the drain of the MOSFET 42. The gate of MOSFET42 is connected to the output of timer circuit 16 and the source of MOSFET42 is connected to terminal OUT of semiconductor device 10.
When the timer circuit 16 receives a signal indicating the L level during the time counting, the gate clamp circuit 17 turns off the MOSFET42, thereby maintaining the gate voltage of the power semiconductor element 11 at a voltage value equal to or higher than the current that can flow through the inrush current of the motor 2. When a signal of H level indicating that the counting is completed is input from the timer circuit 16, the MOSFET42 is turned on, and the gate voltage of the power semiconductor element 11 is lowered to a value that is the sum of the forward voltages of the diodes constituting the diode group 41. This voltage is a gate voltage through which a current necessary for the operation after the start of the motor 2 can flow, and the value thereof can be adjusted by the number of diodes constituting the diode group 41. For example, the voltage applied to the gate of the power semiconductor element 11 at the time of starting the motor 2 is set to a value higher than the potential of the terminal OUT by about 10 volts as a reference potential. After the motor 2 is started, the gate clamp circuit 17 clamps the voltage applied to the gate of the power semiconductor element 11 to about 4 volts. In this case, if the forward voltage of each of the diodes constituting the diode group 41 is set to 0.7 volt and the voltage drop obtained by the on-resistance of the MOSFET42 is set to 0.5 volt, the diode group 41 may be constituted by 5 diodes.
Next, the operation of the semiconductor device 10 will be described with reference to fig. 4 to 6.
Fig. 4 is a diagram showing an operation waveform during motor operation, fig. 5 is a diagram showing an operation waveform in a case where a load short circuit occurs during motor operation, and fig. 6 is a diagram showing an example of static characteristics of a power MOSFET.
First, IN a normal operation, as shown IN fig. 4, when the H-level signal IN is applied to the terminal IN, the control circuit 13 and the charge pump circuit 12 operate to generate the gate-source voltage VGS of the power semiconductor element 11 and the timer circuit 16 starts. The gate-source voltage VGS at this time is 10 volts in the example of fig. 6.
When a gate-source voltage VGS is applied to the gate of the power semiconductor element 11, the power semiconductor element 11 is turned on and the motor 2 is started. At this time, the inrush current at the start of the motor 2 flows through the power semiconductor element 11, and then the current gradually decreases to be fixed at a stable rated current.
When a certain time (time until the end of the surge current) has elapsed after the timer circuit 16 is started, the gate clamp circuit 17 operates to lower the gate-source voltage VGS of the power semiconductor element 11, and thereafter, maintains the lowered gate-source voltage VGS. The gate-source voltage VGS at this time is 4 volts in the example of fig. 6.
Next, a case where a load short circuit occurs when the motor 2 is started and normally operated will be described. When the load short circuit occurs, since the gate-source voltage VGS of the power semiconductor element 11 is already lowered by the gate clamp circuit 17, the current carrying capacity of the power semiconductor element 11 is lowered, and therefore the load short circuit current is also reduced to a value corresponding to the current carrying capacity. That is, as shown in fig. 6, when the drain-source voltage VDS of the power semiconductor element 11 becomes the voltage VCC of the power supply 1, only the drain current (short-circuit current) flows until the saturation current when the gate-source voltage VGS becomes 4 volts. This current is significantly reduced as compared with the saturation current (the circular mark of the broken line in fig. 6) when the gate-source voltage VGS is not reduced, and therefore, the increase in the short-circuit current due to the load short-circuit is reduced, and the heat generation of the power semiconductor element 11 due to the short-circuit current is also reduced. This is also observed in fig. 5, which shows the change in current, and the current at the time of load short-circuit is significantly reduced as compared with the case where there is no gate voltage clamp as shown by the broken line.
Thus, by limiting the gate voltage of the power semiconductor element 11 in advance after the inrush current of the motor 2 flows, even when a load short circuit occurs, only a short-circuit current of a magnitude specified by the limited gate voltage flows. Therefore, heat generation due to the short-circuit current is reduced, and the power semiconductor element 11 is protected from thermal destruction due to a rapid temperature rise.
In the semiconductor device 10 according to embodiment 1, the gate-source voltage VGS is continuously decreased as shown in fig. 4 and 5, but the gate-source voltage VGS may be decreased in a stepwise manner.
Fig. 7 is a circuit configuration diagram showing the semiconductor device according to embodiment 2. In fig. 7, the same reference numerals are given to the same or equivalent components as those shown in fig. 1, and detailed description thereof will be omitted.
The case where the semiconductor device 50 according to embodiment 2 is applied to a high-side IPS including a current limiting circuit is shown. That is, the current limiting circuit includes a MOSFET51 for current sense (current sense), a resistor 52, and a MOSFET53 for reducing the gate voltage.
The drain of MOSFET51 is connected to terminal VCC, the source of MOSFET51 is connected to one terminal of resistor 52, and the other terminal of resistor 52 is connected to terminal OUT. The gate of MOSFET51 is connected to the output of charge pump circuit 12. The junction of the source of the MOSFET51 and the resistor 52 is connected to the gate of the MOSFET53, the drain of the MOSFET53 is connected to the gate of the MOSFET51, and the source of the MOSFET53 is connected to the terminal OUT.
According to the semiconductor device 50, when the power semiconductor element 11 is turned on by the output of the charge pump circuit 12, the MOSFET51 is also turned on. At this time, a current corresponding to the current flowing through the power semiconductor element 11 flows through the MOSFET51, the current is converted into a voltage by flowing through the resistor 52, and the voltage is applied to the gate of the MOSFET 53.
Here, when an overcurrent flows through the power semiconductor element 11, a current proportional to the overcurrent flows through the MOSFET51, and the terminal voltage of the resistor 52 generated thereby is applied to the gate of the MOSFET53, so that the MOSFET53 becomes conductive. When the MOSFET53 is turned on, the gate-source voltage VGS of the power semiconductor element 11 decreases, and the drain current of the power semiconductor element 11 decreases. The overcurrent limit value when the MOSFET53 is turned on is set by the value of the resistor 52, for example, a value between the peak value of the inrush current of the motor 2 and the drain current value at the time of load short circuit.
In the semiconductor device 50, similarly to the semiconductor device 10, the timer circuit 16 is started when the power semiconductor element 11 is turned on, and the gate clamp circuit 17 is started to lower the gate voltage of the power semiconductor element 11 when the timer circuit 16 finishes counting. Thus, the semiconductor device 50 can suppress the short-circuit current when the load short-circuit occurs without any damage to the starting characteristics of the motor 2, and can suppress heat generation due to the load short-circuit.
Fig. 8 is a circuit configuration diagram showing the semiconductor device according to embodiment 3, and fig. 9 is a circuit diagram showing a configuration example of a charge pump circuit of the semiconductor device according to embodiment 3. In fig. 8 and 9, the same reference numerals are given to the same or equivalent components as those shown in fig. 1 and 2, and detailed descriptions thereof are omitted.
In the semiconductor device 60 according to embodiment 3, the charge pump circuit 12a is changed to function as the gate clamp circuit 17 of the semiconductor device 10, as compared with the semiconductor device 10 according to embodiment 1. That is, the charge pump circuit 12a includes the gate clamp 17a, and receives a signal from the timer circuit 16 to reduce the capacity of the charge pump, and further, the current carrying capacity of the power semiconductor element 11.
To achieve this, the charge pump circuit 12a includes a gate clamp 17a as shown in fig. 9. The gate clamp 17a functions as a switch for receiving a signal from the timer circuit 16 to disable the third stage of the booster circuit 23, and includes the inverter 61 and the MOSFET 62.
The input of inverter 61 is connected to the output of timer circuit 16 and the output of inverter 61 is connected to the gate of MOSFET 62. The drain of MOSFET62 is connected to the output of inverter 22 and the source of MOSFET62 is connected to the input of inverter 32 of the third stage.
Thus, when the timer circuit 16 is started, the L-level signal is input to the inverter 61, and therefore, the inverter 61 outputs the H-level signal to turn on the MOSFET62, thereby enabling the third stage of the booster circuit 23. Then, the signal boosted by the three-stage booster circuit 23 is applied to the gate of the power semiconductor element 11, and the surge current of the motor 2 can flow through the power semiconductor element 11.
When the H-level signal is input to the inverter 61 from the timer circuit 16 that has timed out, the inverter 61 outputs an L-level signal, the MOSFET62 turns off, and the third stage of the booster circuit 23 becomes inactive. Then, the signal boosted by the two-stage booster circuit 23 is applied to the gate of the power semiconductor element 11, and a current capable of maintaining the operation of the motor 2 can flow through the power semiconductor element 11.
Thus, the charge pump circuit 12a has the same function as that of the gate clamp circuit 17, and even if a load short circuit occurs during the operation of the motor 2, a current exceeding the peak value of the surge current does not flow through the power semiconductor element 11. In addition, in the semiconductor device 60 according to embodiment 3, since the gate clamp circuit 17 through which current always flows in the diode group 41 and the MOSFET42 is not used during the motor operation after the motor is started, power consumption can be suppressed to be lower than that of the semiconductor device 10.
Fig. 10 is a circuit diagram showing an example of an oscillation circuit constituting a charge pump circuit of the semiconductor device according to embodiment 4.
The semiconductor device according to embodiment 4 has the same configuration as the semiconductor device 60 shown in fig. 8, but the method of realizing the gate clamping portion 17a is different from that shown in fig. 9. That is, the charge pump circuit 12a in fig. 8 reduces the capability of the charge pump by reducing the number of stages of the booster circuit 23, whereas the semiconductor device according to embodiment 4 reduces the capability of the charge pump by reducing the oscillation frequency of the oscillator circuit 21. Therefore, in the semiconductor device 60 shown in fig. 8, the charge pump circuit 12a has the same configuration as the charge pump circuit 12 shown in fig. 2, and the oscillation circuit 21 is constituted by the oscillation circuit 21a shown in fig. 10.
The oscillation circuit 21a includes: a NAND circuit 71, capacitors 72, 74, inverters 73, 75, and a gate clamping portion 17 b. The gate clamping section 17b includes a switch 76 and a capacitor 77.
The gate clamping portion 17b is formed by connecting a switch 76 and a capacitor 77 in series, and the switch 76 is an element that performs switching in accordance with a signal from the timer circuit 16, and is formed of, for example, a MOSFET or the like. One terminal of the switch 76 is connected to one terminal of the capacitor 74, the other terminal of the switch 76 is connected to one terminal of the capacitor 77, and the other terminal of the capacitor 77 is connected to the other terminal of the capacitor 74. Therefore, the gate clamping portion 17b can connect the capacitor 77 and the capacitor 74 in parallel in accordance with the signal from the timer circuit 16, and can change the capacitance of the capacitor 74.
The outputs of the NAND circuit 71 are connected to one terminal of the capacitor 72 and the input of the inverter 73, respectively, and the other terminal of the capacitor 72 is connected to the terminal GND of the semiconductor device. The output of the inverter 73 is connected to one terminal of the switch 76 of the gate clamping unit 17b, one terminal of the capacitor 74, and the input of the inverter 75. The other terminal of the capacitor 77 and the other terminal of the capacitor 74 of the gate clamping portion 17b are connected to the terminal GND of the semiconductor device. The output of the inverter 75 constitutes the output of the oscillation circuit 21a, and is connected to one terminal of the NAND circuit 71, and the other terminal of the NAND circuit 71 is connected to the output of the control circuit 13.
The NAND circuit 71 outputs a signal of H level when a signal of L level is input to the other terminal, and outputs a signal obtained by inverting the logic level of the signal input to the one terminal when a signal of H level is input to the other terminal. Therefore, the oscillation circuit 21a constitutes a ring oscillator that connects the inverter function of the NAND circuit 71 to the inverters 73 and 75 in a ring shape. The oscillation frequency of the oscillation circuit 21a is determined by the capacitance values of the capacitors 72 and 74 disposed at the outputs of the NAND circuit 71 and the inverter 73, respectively, and is oscillated at a frequency determined by the capacitance values of the capacitors 72 and 74 at the time of starting the motor. In the motor operation after the motor start, the capacitance of the capacitor 74 is increased by the capacitance value of the capacitor 74 of the gate clamp 17b to lower the oscillation frequency of the oscillation circuit 21a, thereby reducing the number of pumping operations of the charge pump, thereby reducing the capacity.
In the above embodiment, the case of application to a high-side IPS was described, but the present invention can be similarly applied to a low-side IPS having no charge pump. Further, although the semiconductor device in which the power semiconductor element 11 and the driver circuit around the power semiconductor element are formed into a single chip or a single package has been described, the present invention can be similarly applied to a driver circuit without the power semiconductor element 11.
Description of the reference symbols
1 Power supply
2 electric motor
10 semiconductor device
11 power semiconductor element
12. 12a charge pump circuit
13 control circuit
14 protective circuit
15 power-taking MOSFET
16 timer circuit
17 gate clamp circuit
17a, 17b gate clamping part
21. 21a oscillating circuit (oscillator)
22 inverter
23 step-up circuit (multistage voltage step-up part)
24 inverter
25 capacitor
26. 27 diode
28 inverter
29 capacitor
30. 31 diode
32 inverter
33 capacitor
34. 35 diode
41 diode group
42 MOSFET
50 semiconductor device
51 MOSFET
52 resistance
53 MOSFET
60 semiconductor device
61 inverter
62 MOSFET
71 NAND circuit
72 capacitor
73 inverter
74 capacitor
75 inverter
76 switch
77 capacitor
GND terminal
IN terminal
OUT terminal
VCC terminal
VDS Drain-Source Voltage
Gate-source voltage of VGS
Claims (6)
1. A semiconductor device including a driving circuit for driving a power semiconductor element,
the drive circuit includes:
a gate clamping circuit that clamps a gate voltage of the power semiconductor element;
a timer circuit that starts counting when the power semiconductor element is energized; and
a booster circuit that generates the gate voltage when the power semiconductor element is turned on, and that includes an oscillator and a multistage booster unit that outputs the gate voltage boosted by a switching operation based on an oscillation signal of the oscillator,
the gate clamp circuit is a circuit for reducing the number of stages of the multistage boosting section based on a signal from the timer circuit to thereby lower the gate voltage,
the timer circuit operates the gate clamp circuit after a predetermined time elapses from the start of counting, the predetermined time being a time until the end of a surge current flowing when the power semiconductor element starts to be energized, thereby reducing the current carrying capacity of the power semiconductor element.
2. The semiconductor device according to claim 1,
the boost circuit is a charge pump circuit.
3. The semiconductor device according to claim 1,
the drive circuit and the power semiconductor element are integrally included.
4. A semiconductor device including a driving circuit for driving a power semiconductor element,
the drive circuit includes:
a gate clamping circuit that clamps a gate voltage of the power semiconductor element;
a timer circuit that starts counting when the power semiconductor element is energized; and
a booster circuit that generates the gate voltage when the power semiconductor element is turned on, and that includes an oscillator and a multistage booster unit that outputs the gate voltage boosted by a switching operation based on an oscillation signal of the oscillator,
the gate clamping circuit is a circuit that lowers the oscillation frequency of the oscillator based on a signal from the timer circuit, thereby lowering the gate voltage,
the timer circuit operates the gate clamp circuit after a predetermined time elapses from the start of counting, the predetermined time being a time until the end of a surge current flowing when the power semiconductor element starts to be energized, thereby reducing the current carrying capacity of the power semiconductor element.
5. The semiconductor device according to claim 4,
the boost circuit is a charge pump circuit.
6. The semiconductor device according to claim 4,
the drive circuit and the power semiconductor element are integrally included.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015-117263 | 2015-06-10 | ||
| JP2015117263A JP6596948B2 (en) | 2015-06-10 | 2015-06-10 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106253753A CN106253753A (en) | 2016-12-21 |
| CN106253753B true CN106253753B (en) | 2020-09-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610300672.3A Active CN106253753B (en) | 2015-06-10 | 2016-05-09 | Semiconductor device with a plurality of semiconductor chips |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US9871513B2 (en) |
| EP (1) | EP3104527B1 (en) |
| JP (1) | JP6596948B2 (en) |
| CN (1) | CN106253753B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6520102B2 (en) * | 2014-12-17 | 2019-05-29 | 富士電機株式会社 | Semiconductor device and current limiting method |
| JP7052452B2 (en) * | 2018-03-19 | 2022-04-12 | 富士電機株式会社 | Semiconductor device |
| JP7163486B2 (en) * | 2019-04-17 | 2022-10-31 | 日立Astemo株式会社 | load driver |
| CN111446705B (en) * | 2020-04-07 | 2021-12-07 | 中科新松有限公司 | Power-on current-limiting circuit |
| JP7449805B2 (en) * | 2020-07-27 | 2024-03-14 | ミネベアミツミ株式会社 | Motor drive control device and motor unit |
| JP2023018810A (en) | 2021-07-28 | 2023-02-09 | 株式会社東芝 | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3230252B2 (en) * | 1991-10-28 | 2001-11-19 | 関西日本電気株式会社 | Current limit circuit |
| JP3036212B2 (en) * | 1992-03-10 | 2000-04-24 | 日本電気株式会社 | Protection circuit |
| DE4316185A1 (en) * | 1993-05-14 | 1994-11-17 | Fahrzeugklimaregelung Gmbh | Circuit arrangement for switching an electrical consumer on and off |
| US5541799A (en) * | 1994-06-24 | 1996-07-30 | Texas Instruments Incorporated | Reducing the natural current limit in a power MOS device by reducing the gate-source voltage |
| DE19511199A1 (en) * | 1995-03-27 | 1996-10-02 | Bosch Gmbh Robert | Circuit arrangement for switching an electrical load |
| US5602794A (en) * | 1995-09-29 | 1997-02-11 | Intel Corporation | Variable stage charge pump |
| JP3601310B2 (en) | 1997-11-06 | 2004-12-15 | 富士電機デバイステクノロジー株式会社 | Power device drive circuit |
| JP3741949B2 (en) * | 2000-07-24 | 2006-02-01 | 矢崎総業株式会社 | Semiconductor switching device |
| JP2002190727A (en) * | 2000-12-21 | 2002-07-05 | Toshiba Microelectronics Corp | Semiconductor protection circuit |
| JP4712519B2 (en) | 2005-05-27 | 2011-06-29 | フリースケール セミコンダクター インコーポレイテッド | Charge pump circuit for high side drive circuit and driver drive voltage circuit |
| JP4339872B2 (en) * | 2006-05-25 | 2009-10-07 | 株式会社日立製作所 | Semiconductor element driving device, power conversion device, motor driving device, semiconductor element driving method, power conversion method, and motor driving method |
| JP2011040942A (en) * | 2009-08-10 | 2011-02-24 | Yazaki Corp | Device and method for controlling load drive |
| US8487689B2 (en) * | 2010-01-06 | 2013-07-16 | Aptus Power Semiconductor | Load switch system driven by a charge pump |
| JP5431994B2 (en) * | 2010-02-10 | 2014-03-05 | ルネサスエレクトロニクス株式会社 | Current limit circuit |
| US8339185B2 (en) * | 2010-12-20 | 2012-12-25 | Sandisk 3D Llc | Charge pump system that dynamically selects number of active stages |
| US8384467B1 (en) * | 2012-03-22 | 2013-02-26 | Cypress Semiconductor Corporation | Reconfigurable charge pump |
| US9195255B1 (en) * | 2012-03-22 | 2015-11-24 | Parade Technologies, Ltd. | Reconfigurable charge pump |
| JP6211822B2 (en) * | 2012-09-28 | 2017-10-11 | 旭化成エレクトロニクス株式会社 | Power supply circuit |
| US8836412B2 (en) * | 2013-02-11 | 2014-09-16 | Sandisk 3D Llc | Charge pump with a power-controlled clock buffer to reduce power consumption and output voltage ripple |
-
2015
- 2015-06-10 JP JP2015117263A patent/JP6596948B2/en active Active
-
2016
- 2016-05-09 CN CN201610300672.3A patent/CN106253753B/en active Active
- 2016-05-10 US US15/150,489 patent/US9871513B2/en active Active
- 2016-05-10 EP EP16169004.5A patent/EP3104527B1/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20160365852A1 (en) | 2016-12-15 |
| EP3104527A2 (en) | 2016-12-14 |
| EP3104527A3 (en) | 2017-04-12 |
| CN106253753A (en) | 2016-12-21 |
| EP3104527B1 (en) | 2021-03-03 |
| JP2017005862A (en) | 2017-01-05 |
| US9871513B2 (en) | 2018-01-16 |
| JP6596948B2 (en) | 2019-10-30 |
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