JP3036212B2 - Protection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection circuit, and more particularly to a protection circuit for preventing damage to an output stage power transistor due to an overcurrent when a load is short-circuited.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing an example of a conventional protection circuit of this kind. The protection circuit shown in this figure is a protection circuit used for an IC mounted on an automobile and for turning on / off a solenoid or a lamp as a load. Referring to FIG. 3, in this circuit, an output NMOS transistor N ₁ and a load resistor _RL are connected in series between a high-level power supply terminal (potential V _DD ) 1 and a ground terminal 2. The load resistance _RL is representative of the above-mentioned solenoid or lamp. Between the gate electrode of the output NMOS transistor N ₁ and the load resistor R _L, the protective NMOS transistor N ₂ and the four diodes D are connected in series. The gate electrode of the protective NMOS transistor N ₂ is connected to the high potential power supply terminal 1 described above. Output NM
The gate electrode of the OS transistor N _1, the high power supply potential V _DD is input is boosted by the charge pump circuit 3. Whether the charge pump circuit 3 is in the operating state or in the halt state is controlled by the state of an input signal S from a preceding microcomputer (not shown).

[0003] The operation of this circuit will be described below using a protection circuit for an IC mounted on a vehicle as an example. In this case, the higher power supply potential V _DD is equal to the battery voltage and is usually 12 V, but since this voltage fluctuates, for example, V _DD = 20 V
And Therefore, the power supply potential of the charge pump circuit 3 is also 20V. The input signal S from the preceding microcomputer is assumed to be a signal having an amplitude of 0 to 5V. The circuit for driving the output NMOS transistor N ₁ is not necessarily a charge pump circuit 3, if there separate circuit capable of providing a voltage higher than 20V, it is of course possible to use it.

In FIG. 3, V _DD (=
When the ON signal (5 V) is input to the signal input terminal 4 and the gate electrode of the output NMOS transistor N ₁ is charged, the charge pump circuit 3
A voltage (for example, 20 + 5 V) that is higher than the higher power supply potential V _DD is applied to the output NMO.
S transistor N ₁ is turned on. Therefore, a current flows through the load resistance R _L (for example, 40Ω). At this time, the high power supply potential V _DD is applied to the gate electrode of the protection NMOS transistor N ₂ , and the source potential is (V _DD −the ON resistance value of the output NMOS transistor N ₁ (for example, 1
00 mΩ) × output current I _O ). Since however the on-resistance is small output MOS transistor N _1,
No voltage exceeding the threshold voltage (V _T2 ) (for example, 1 V) is applied between the gate and source of the protection NMOS transistor N ₂ , and the protection NMOS transistor N ₂ is off.

Next, in the above state, the load resistance R _L
If but it is assumed that the short-circuit, the protective NMOS transistor N ₂ is, down the source potential to the ground potential, the gate
Since the voltage V _DD is applied between the sources, the state changes from off to on. The output NMOS transistor N ₁ is
Since the gate voltage drops to (ground potential + 4 × diode forward voltage (eg, 0.6 V)), the on-resistance increases. Therefore, the output current _IO is suppressed, and the output NMOS
Breakdown of the transistor N ₁ is prevented.

Next, a transient operation when the input signal S to the input terminal 4 is changed from an OFF signal (0 V) to an ON signal (5 V) will be described. In the state of the input signal S is OFF signal, the output NMOS transistor N ₁ because there is no output from the charge pump circuit 3 is turned off. NM for protection
The OS transistor N ₂ has a high power supply potential V
_{Since DD} is applied and the source potential is lowered to the ground potential, it is in the ON state. When the input signal S is turned on, the output of the charge pump circuit 3 increases. NM for output
OS transistor N ₁ is, since the gate potential is going up on-resistance gradually decreases. At this time, since the NMOS transistor N ₂ is turned on for protection, the number 10
A current of about 0 μA flows through the protection NMOS transistor N ₂ and the diode D. Further the output voltage of the charge pump circuit 3 increases, the on-resistance of the output NMOS transistor N ₁ is smaller, protective N
MOS transistor N ₂ is finally reduced the source potential rises the gate-source potential is turned off. Therefore, the outputs of the charge pump circuit 3 are all output NM
It is applied to the gate of the OS transistors N _1, the output NM
OS transistor N ₁ is completely turned on.

[0007]

In the conventional protection circuit described above, a current flows through the protection NMOS transistor while the output NMOS transistor is turned on from off. That is, the current for charging the gate capacitance of the output NMOS transistor is shunted to the protection NMOS transistor and reduced, so that the switching speed is reduced.

[0008]

According to the protection circuit of the present invention, the output current of the output stage transistor is limited by the conduction state of the protection transistor provided between the gate electrode of the output stage transistor and the output terminal. In the protection circuit of the type, a delay control circuit that gives a predetermined time delay to an input signal synchronized with the output stage transistor drive signal and outputs the same, and two transistors having different conductivity types are connected in series, and the connection point is After the output from the delay control circuit is input to the respective gate electrodes of the two transistors and the output stage transistor is turned on, the protection transistor is connected to the gate electrode of the protection transistor. A gate bias circuit for applying a potential that makes this protective transistor conductive to a gate electrode of the transistor; It is characterized in that.

Further, in a protection circuit of a type in which the output current of an output stage transistor is limited by the conduction state of a protection transistor provided between the gate electrode of the output stage transistor and the output terminal, A comparison circuit that compares the potential of the output terminal side electrode with the power supply potential, a signal synchronized with an output stage transistor drive signal and an output of the comparison circuit are input, and the output stage transistor reaches a steady state of an ON operation. Then, a control circuit that latches and outputs the output state of the comparison circuit, and two transistors having different conductivity types are connected in series, and the connection point is connected to the gate electrode of the protection transistor, An output from the control circuit is input to each gate electrode of the two transistors, and the output stage transistor is turned on. After changing to the gate electrode of the protection transistor, it is characterized by a gate bias circuit for applying a potential to allow conduction of this protection transistor.

[0010]

Next, a preferred embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. Referring to FIG 1, the a conventional protective circuit shown in this embodiment and FIG. 3 are different, it is better given gate potential of the protective NMOS transistor N _2. In this embodiment, the connection point where the NMOS transistor N ₀ and the PMOS transistor P ₀ are connected in series is connected to the gate electrode of the protection NMOS transistor N ₂ , and the delay circuit 5 is connected to the gate electrodes of these two MOS transistors. Output terminals are connected. The other electrode of the NMOS transistor N ₀ is connected to the high potential power supply terminal 1, other electrode of the PMOS transistor P ₀ is connected to the load resistor R _L. The input signal S input to the charge pump circuit 3 is simultaneously input to the input terminal of the delay circuit 5. The delay circuit 5 delays the input signal S by a predetermined time and inputs the delayed signal to the gate electrodes of the NMOS transistor N ₀ and the PMOS transistor P ₀ .

The operation of the embodiment will be described below. In FIG. 1, when a potential V _DD is applied to a high-order power supply terminal 1 and an input signal S is an off signal (0 V), the output NM
OS transistor N ₁ is in the OFF state. Since a low level signal is output from the delay circuit 5, the NMOS transistor N ₀ is off and the PMOS transistor P ₀ is on. Protective NMOS transistor N ₂ is therefore turned off. Here, when the ON signal of the input signal S (5V), the output potential of the charge pump circuit 3 begins to rise, the output NMOS transistor N ₁ is going to transition to the ON state. At this time, since the protective NMOS transistor N ₂ still is in the off-state current flowing through the transistor is zero. Thus, the output of the charge pump circuit 3 is applied without waste all the output NMOS transistor N _1. Output NMOS transistor N ₁
Is sufficiently turned on, and the output of the delay circuit 5 goes high when the source potential has risen sufficiently. Then, the NMOS transistor N ₀ is turned on and the PMOS transistor P ₀ is turned off.
The gate of the transistor N ₂ is biased to the high power supply potential V _DD side. However, at this time, this protection NMO
Since the source potential of the S transistor N ₂ is up sufficiently, the transistor remains off. That is,
Since all the output of the charge pump circuit 3 to the output NMOS transistor N ₁ moves fully on from off Cal on the output NMOS transistor N _1, switching speed is faster.

In the first embodiment described above, the output NMOS
NM protective transistor N ₁ is from the transition to the ON state
As a circuit configuration for raising the gate potential of the OS transistor N _2, an example is described using the delay circuit 5, the difference in timing of the operation as described above, the second embodiment shown in FIG. 2 As described above, it can also be realized by a circuit configuration using a comparator.

FIG. 2 is a circuit diagram of a second embodiment of the present invention. Referring to FIG. 2, this embodiment is different from the first embodiment in that the NMOS transistor N ₀ and the PMOS transistor
It is a way of controlling the gate potential of the transistor P _0. In this embodiment, the source potential of the protective NMOS transistor N ₂ and the high potential power supply potential V _DD is compared by the comparator 6, when the both potentials become equal, the comparator 6 outputs a high level signal. The output of the comparator 6 is
The signal is input to the clock input terminal of the D-type flip-flop 7A, and is inverted and input to the clock input terminal of the D-type flip-flop 7B and one input terminal of the two-input NAND circuit 8. Two D-type flip-flops 7
Input signals S input to the charge pump circuit 3 are simultaneously input to the data input terminals of A and 7B. The input signal S is also inverted and input to the other input terminal of the two-input NAND circuit 8. D-type flip-flop 7A, 7
The output of B is input to a two-input OR circuit 9, and the output of the two-input OR circuit 9 and the two-input NAND circuit 8
Are input to a two-input AND circuit 10.
The output of the two-input AND circuit 10 is determined by the gate electrode of the MNOS transistor N ₀ and the PMOS transistor P ₀
Are input to the respective gate electrodes.

[0014] In Now Figure 2, when the input signal S as an initial state is OFF signal (0V), so the charge pump circuit 3 is at rest, the output NMOS transistor N ₁ are turned off, the protective NMOS Transistor N ₂
Is at the ground potential. Therefore, the comparator 6 outputs a low level signal. On the other hand, two-input NA
The ND circuit 8 outputs a low-level signal because a high-level signal obtained by inverting the low-level output signal of the comparator 6 and a high-level signal obtained by inverting the input signal S are input. Each of the two D-type flip-flops 7A and 7B outputs a low-level signal. As a result, the two-input AND circuit 10 outputs a low level signal, the NMOS transistor N ₀ is turned off, and the PMOS transistor P ₀
Is turned on, and the gate potential of the protection NMOS transistor N2 is at the ground potential.

Next, when the input signal S is turned on signals (5V), since the charge pump circuit 3 went up gradually the output voltage starts to operate, from gradually off state output NMOS transistor N ₁ continue to migrate to the oN state, the source potential of the protective NMOS transistor N ₂ rises with it. In this case, to the source potential of the protective NMOS transistor N ₂ reaches the higher power supply potential V _DD (20V), since the comparator 6 outputs a low level signal, D-type flip-flop 7A, the logic state of the subsequent 7B is Henra Instead, the two-input AND circuit 10 outputs a low-level signal as in the initial state. Therefore NMO
Since the S transistor N ₀ keeps the off state and the PMOS transistor P ₀ keeps the on state, the protection NMOS transistor N ₂ keeps the gate potential at the ground potential and keeps the off state. The output NMOS transistor N
_{In the case of 1} , all the output from the charge pump circuit 3 is applied to the gate electrode, and the state rapidly changes to the ON state. Thereafter, when the output NMOS transistor N ₁ is sufficiently turned on and the source potential of the protection NMOS transistor N ₂ reaches 20 V, the comparator 6 outputs a high-level signal. High level, the NMOS transistor N ₀ is turned on,
The PMOS transistors P ₀ shift to the off state, and the gate potential of the protection NMOS transistor N ₂ becomes substantially equal to the higher power supply potential V _DD . At this time, NM for protection
OS transistor N _2, since the source potential already is sufficiently high, remain off.

Next, when the load resistance R _L is assumed to have shorted when in the steady state of the source potential of the protective NMOS transistor N ₂ is reduced to approximately ground potential, the low level output of the comparator 6 from the high level Changes to Therefore, the level of one input (an inverted signal of the output signal of the comparator 6) of the two-input NAND circuit 8 changes, but the output of the other input (an inverted signal of the input signal S) remains low. Remains unchanged at the high level. The output of the D-type flip-flop 7A of the two D-type flip-flops does not change and remains at the high level.
B outputs high-level data because the clock input (inverted signal of the output signal of the comparator 6) changes from low level to high level. As a result, the two-input OR circuit 9 outputs a high-level signal because both inputs are at a high level. As a result, the two-input AND circuit 10 outputs a high-level signal. Therefore, the NMOS transistor N
₀ maintains the ON state, and the PMOS transistor P ₀ maintains the OFF state. As a result of the above operation, a voltage of about 20 V is applied between the gate and the source of the protection NMOS transistor N ₂ , and the protection NMOS transistor N ₂ is turned on.
Since falls to the ground potential through the S transistor N _2, the output NMOS transistor N ₁ is turned off, breakdown due to overcurrent can be prevented.

[0017]

As described above, the protection circuit according to the first aspect of the present invention is provided so as to be connected to the gate electrode of an output transistor and to protect the output transistor from being damaged by overcurrent. A transistor is provided with a gate bias circuit for controlling a gate potential of the transistor and a delay control circuit for controlling a conduction state of a transistor included in the gate bias circuit. Then, the delay control circuit inputs a signal delayed from the gate potential control signal of the output transistor to the gate bias circuit, so that the output transistor is sufficiently turned on.
The protection transistor is configured to be conductive.

Further, the protection circuit according to the present invention has a comparator for comparing the source potential of the protection transistor with the power supply potential, and a gate bias circuit for controlling the gate potential of the protection transistor. . With this configuration, when the output transistor is turned on, while the on-resistance of the transistor is high and the source potential of the protection transistor is low, a low-level potential is applied to the gate electrode of the protection transistor to apply a large potential between the gate and the source. The voltage is not applied, and the transistor is kept off.

Thus, according to the present invention, when the output transistor is turned on from the off state, the output transistor drive signal is not shunted to the protection transistor and the gate capacitance of the output transistor is charged. , The switching time is shorter than that of the conventional protection circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram of an example of a conventional protection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 High power supply terminal 2 Ground terminal 3 Charge pump circuit 4 Input terminal 5 Delay circuit 6 Comparator 7A, 7B D-type flip-flop 8 NAND circuit 9 OR circuit 10 AND circuit

Claims (2)

(57) [Claims] 1. A protection circuit of a type in which an output current of an output stage transistor is limited by a conduction state of a protection transistor provided between a gate electrode of the output stage transistor and an output terminal. A delay control circuit that gives a delay of a predetermined time to an input signal that is synchronized with the output signal, and two transistors having different conductivity types are connected in series, and the connection point is connected to the gate electrode of the protection transistor. After the output from the delay control circuit is input to the respective gate electrodes of the two transistors and the output stage transistor changes to the ON state, the protection transistor is connected to the gate electrode of the protection transistor. A gate bias circuit for applying a potential that enables conduction. 2. A protection circuit of a type in which an output current of an output stage transistor is limited by a conduction state of a protection transistor provided between a gate electrode and an output terminal of the output stage transistor, A comparison circuit that compares the potential of the output terminal side electrode with the power supply potential, a signal synchronized with an output stage transistor drive signal and an output of the comparison circuit are input, and the output stage transistor reaches a steady state of an on operation. After that, a control circuit that latches and outputs the output state of the comparison circuit and two transistors having different conductivity types are connected in series, and the connection point is connected to the gate electrode of the protection transistor. An output from the control circuit is input to each gate electrode of the two transistors,
A protection circuit, comprising: a gate bias circuit that applies, to the gate electrode of the protection transistor, a potential that makes the protection transistor conductive after the output stage transistor changes to an on state.