CN106252388B - Semiconductor crystal wafer and its manufacturing method - Google Patents
Semiconductor crystal wafer and its manufacturing method Download PDFInfo
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- CN106252388B CN106252388B CN201610217204.XA CN201610217204A CN106252388B CN 106252388 B CN106252388 B CN 106252388B CN 201610217204 A CN201610217204 A CN 201610217204A CN 106252388 B CN106252388 B CN 106252388B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 85
- 239000013078 crystal Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 49
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 35
- 239000010410 layer Substances 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 239000011241 protective layer Substances 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 7
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052594 sapphire Inorganic materials 0.000 claims description 6
- 239000010980 sapphire Substances 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000010884 ion-beam technique Methods 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 230000001939 inductive effect Effects 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- 238000012800 visualization Methods 0.000 claims 1
- 239000012634 fragment Substances 0.000 abstract description 5
- 235000012431 wafers Nutrition 0.000 description 99
- 239000000463 material Substances 0.000 description 12
- 238000005520 cutting process Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 5
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- 238000000151 deposition Methods 0.000 description 4
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- 238000000227 grinding Methods 0.000 description 4
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- 238000011161 development Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
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- 230000003628 erosive effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
- 241001062009 Indigofera Species 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
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- 238000003491 array Methods 0.000 description 1
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- 229910003460 diamond Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
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- 229910001751 gemstone Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
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- 239000007924 injection Substances 0.000 description 1
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- 238000001465 metallisation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
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- 238000004544 sputter deposition Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
Abstract
The embodiment of the present invention provides a kind of semiconductor crystal wafer and its manufacturing method.The semiconductor crystal wafer includes multiple spaced chips, and the dicing lane being arranged at intervals between two neighboring chip.Wherein, each chip include the semiconductor devices being formed on one surface of wafer, positioned at the back metal on another surface of wafer and at least one through the wafer and connecting the metal part of semiconductor devices and the through-hole of the back metal.The through-hole is formed in same etching technics with the dicing lane.The embodiment of the present invention can reduce the fragment rate of semiconductor crystal wafer, improve product yield.
Description
Technical field
The present invention relates to microelectronics, semiconductor making method field, in particular to a kind of semiconductor crystal wafer and its system
Make method.
Background technique
It is completed after device by processing steps such as illumination, etching, deposition, cleaning, injections on a semiconductor wafer,
Generally can be by the way of physical mechanical cutting, the circuit devcie that semiconductor crystal wafer is made is cut into multiple independent cores
Piece.Physical mechanical cutting generally uses slicer, its working principle is that using the section of high-speed rotating diamond blade, with every
The feed velocity of several to dozens of millimeters of second carries out physics cutting to semiconductor crystal wafer, along the dicing lane reserved on wafer
Region is particulate substance semiconductive material wafer cutting, achievees the purpose that cutting separation.It is cut using physical mechanical
Mode the circuit devcie on semiconductor crystal wafer can be cut into multiple independent chips.But aforesaid way is lacked there are some
Point because cutter blade itself has certain thickness, and may make chip front side and the back side during cutting
Edge all generate a degree of chipping.As the dicing lane between fruit chip and chip width design it is inadequate, blade is cut
The width and chipping entered influences whether device architecture, leads to device damage, yield decline.If dicing lane width design is enough
Width, the quantity that will lead to make chip on wafer are reduced, and device cost is caused to rise.
In addition, in order to improve device gain, reducing grounded inductor when making semi-conductor discrete device, generalling use logical
Pore structure.This structure introduces through-hole from backside of wafer generally by the mode of etching, which runs through entire semiconductor die
Circle, until semiconductor, then uses filling hole with metal, source electrode is connected with the backside of wafer of ground connection, to reduce source electrode to ground
Inductance.So another method for making semiconductor wafer device be split up into multiple individual chips is using etching technics.It is etching
It is etched while through-hole along semiconductor wafer back street area, being separated between chip and chip.But this method
There are disadvantages, one is control is improper, it can be in chip all etched separation, the through-hole for needing to etch but reaches without etching
The depth needed.The second is, because of the problem of etching depth controls, causing wafer easy in subsequent technique after etching
It is broken.
Summary of the invention
In view of the foregoing, the embodiment of the present invention is designed to provide a kind of semiconductor crystal wafer and its manufacturing method, with
Improve above-mentioned problem.
A kind of semiconductor crystal wafer provided in an embodiment of the present invention, comprising: multiple spaced chips, and interval setting
Dicing lane between two neighboring chip.Wherein, each chip includes the semiconductor being formed on one surface of wafer
Device, positioned at the back metal on another surface of wafer and at least one through the wafer and connecting semiconductor devices
Metal part and the back metal through-hole；Wherein, the through-hole is formed in same etching technics with the dicing lane.
Preferably, the etched surface of the etched surface and through-hole of the dicing lane is same etching surface, straight by adjusting through-hole
The dimension scale of diameter and dicing lane width, so that through-hole, in the metal part for etching into semiconductor devices, the dicing lane is carved
The trench depth that erosion is formed is between 4th/1st to five/5th of the wafer thickness.
Preferably, the diameter of the through-hole is 5 to 50 times of the maximum width of the dicing lane, when through-hole is ellipticity
When, the diameter refers to long side diameter.
Preferably, a dicing lane is set between two chips of arbitrary neighborhood, each dicing lane include first part with
And it is connected to the second part of first part's opposite end, the width of first part is greater than the width of second part.
Preferably, the width of the dicing lane first part is 1 to 10 times of the width of the second part.
Preferably, the wafer is formed by silicon, sapphire, silicon carbide, GaAs, gallium nitride one of which wafer bare die
It either grown one of shape in the epitaxial wafer of epitaxial layer on silicon, sapphire, silicon carbide and gaas wafer bare die
At.
The manufacturing method of a kind of semiconductor crystal wafer provided in an embodiment of the present invention, comprising: semiconductor devices will be formed with
Wafer attaches to substrate supports on piece；It is formed in the wafer far from a surface of the substrate supports piece patterned
Mask layer exposes a part of the wafer；And a part of the wafer exposed is performed etching, formation is passed through
The through-hole of the wafer substrate piece and the dicing lane including first part of different size and second part are worn, wherein described
The width of a part is greater than the second part, and the second part is connected to the opposite end of the first part.
Preferably, after the wafer attaches to the substrate supports on piece, the method also includes: to described
One wafer substrate piece carries out thinned, wherein the wafer is thinned between 50 to 200 microns.
Preferably, the step of wafer forms patterned mask layer far from a surface of the substrate supports piece
It include: to deposit a mask layer far from a surface of the substrate supports piece in the wafer；It is rectangular on the mask layer
At one layer of protection materials, and protection materials are carried out using a reticle to be lithographically formed patterned protective layer；And described in removal
Mask layer does not form the patterned mask layer by the part that the protective layer is blocked.
Preferably, the reticle includes and the through-hole corresponding first light passing portion and corresponding with the dicing lane
Second light passing portion, second light passing portion include the first light passing region corresponding with the first part of the dicing lane and with institute
The second part corresponding second light passing region of dicing lane is stated, the width in first light passing region is greater than second transparent zone
The width in domain.
Preferably, the method also includes: formed in the wafer far from a surface of substrate supports piece patterned
Back metal is electrically connected the back metal by the metal part of the through-hole and the semiconductor devices；And from described
Wafer removes the substrate supports piece, isolates the semiconductor crystal wafer.
Preferably, the method is using reactive ion etching, inductive coupling plasma etch or ion beam etching method to institute
The a part for stating wafer performs etching.
Preferably, the patterned mask layer by nickel, aluminium, silica, silicon nitride, photoresist one of which or
More than one composition is formed.
Compared with prior art, semiconductor crystal wafer provided in an embodiment of the present invention and its manufacturing method, wherein pass through adjusting
Through-hole diameter and dicing lane width dimensions ratio so that via etch to semiconductor devices metal part when, dicing lane etching
Depth is between 4th/1 to five/5ths of wafer thickness.Experiment proves that controlling the etching depth of dicing lane one
Determine in range, when wafer is in technical process after separating from substrate supports on piece, because there are also etching remainders
Connection, it is possible to reduce the fragment rate of wafer.In addition the design of the dicing lane of semiconductor crystal wafer includes two parts of different size,
By designing different in width, realize that the etching depth in different in width region is different, to realize that the connection of chip different zones is strong
Degree is different.Experiment proves that can reduce the fragment rate of semiconductor crystal wafer, product yield is improved.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 shows through-hole and the signal of dicing lane planar structure of semiconductor crystal wafer provided by present pre-ferred embodiments
Figure.
Fig. 2 is a part of plane enlarged diagram of semiconductor die round tube hole shown in FIG. 1 and dicing lane.
Fig. 3 is diagrammatic cross-section of the semiconductor crystal wafer along A-A tangent line shown in FIG. 1.
Fig. 4 is in the embodiment of the present invention for manufacturing the schematic diagram of the reticle of through-hole shown in Fig. 2 and dicing lane.
Fig. 5 is the process flow chart of the manufacturing method of semiconductor crystal wafer described in present pre-ferred embodiments.
Fig. 6-Figure 15 be the semiconductor crystal wafer each process flow steps of manufacturing method in manufacture the semiconductor respectively
The structural schematic diagram of each component part of wafer.
Specific embodiment
Below in conjunction with attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Usually exist
The component of the embodiment of the present invention described and illustrated in attached drawing can be arranged and be designed with a variety of different configurations herein.Cause
This, is not intended to limit claimed invention to the detailed description of the embodiment of the present invention provided in the accompanying drawings below
Range, but it is merely representative of selected embodiment of the invention.Based on the embodiment of the present invention, those skilled in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.
It please refers to Fig.1 to Fig.3, a kind of semiconductor crystal wafer 100 that present pre-ferred embodiments provide includes that multiple intervals are set
The chip 110 set and the dicing lane 120 being set between adjacent chips 110.Preferably, in the present embodiment, the semiconductor
Multiple chips 110 that wafer 100 includes can be arranged in arrays in the plane where semiconductor crystal wafer 100.
In the present embodiment, a dicing lane 120 is set between arbitrary neighborhood two chips 110.In identical extension
Direction, two neighboring dicing lane 120 interconnect.It is handed between each other in the adjacent dicing lane 120 of different extending directions
Fork setting.As shown in Fig. 2, the dicing lane 120 is including first part 121 and is connected to 121 opposite end of first part
Second part 122.The width of the first part 121 is greater than the width of the second part 122.Preferably, first part 121
Width be between 1 to 10 times of width of second part 122.
Further, as shown in figure 3, the chip 110 includes the semiconductor devices for being made in 101 1 surface of wafer
130, it is set to the back metal 140 on another surface of wafer 101 and through the wafer 101 for being connected to described half
(the present embodiment only shows a through-hole to an at least through-hole 150 for the metal part of conductor device 130 and the back metal 140
150).In the present embodiment, when the semiconductor devices 130 is three terminal device, the metal part of the semiconductor devices 130 can
To be source metal.The semiconductor devices 130 is connect by the through-hole 150 with the back metal 140.The back-side gold
Belonging to 140 can be used as grounded metal.It preferably, can be by silicon, indigo plant for making the wafer 101 of the chip 110 in the present embodiment
It is brilliant that jewel, silicon carbide, GaAs, gallium nitride wafer bare die one of which form either silicon, sapphire, silicon carbide, GaAs
The epitaxial wafer one of which that circle bare die grown epitaxial layer is formed.The shape of the through-hole 150 can be round or ellipse.
Secondly, the back side that the dicing lane 120 is the face where forming semiconductor devices 130 from the wafer 101 is carved
Groove made of erosion may be implemented by adjusting through-hole diameter and dicing lane width dimensions ratio when via etch to semiconductor
When the metal part of device, the etching depth of the groove be 101 thickness of wafer 4/1sts to five/5th it
Between.In the present embodiment, the through-hole 150 is formed in same etching technics with the dicing lane 120.
Preferably, in an embodiment, reticle as shown in Figure 4 is can be used in the through-hole 150 and the dicing lane 120
170 implement the processing procedures such as illumination, etching and are formed.Specifically, the light shield 170 includes multiple corresponding with the through-hole 150 the
One light passing portion 171 and multiple with corresponding second light passing of dicing lane 120 portion 172.The shape in first light passing portion 171
Identical as the shape of the through-hole 150, the shape in second light passing portion 172 is identical as the shape of the dicing lane 120.Specifically
Ground, second light passing portion 172 include with corresponding first light passing of first part 121 region 1721 of the dicing lane 120 with
And with corresponding second light passing of second part 122 region 1722 of the dicing lane 120.The width in first light passing region 1721
Degree is greater than the width in second light passing region 1722.
In conclusion dicing lane 120 is designed as of different size two by semiconductor crystal wafer 100 provided in an embodiment of the present invention
Part, experiment proves that, it can reduce the fragment rate of semiconductor crystal wafer 100, improve product yield.
Fig. 5 shows the process flow chart of the manufacturing method of semiconductor crystal wafer 100 described in present pre-ferred embodiments.Under
Face combines Fig. 6 to Figure 15 that the flow chart is described in detail.It should be noted that method of the present invention is not to scheme
5 and specific order as described below be limitation.It should be appreciated that in other embodiments, its middle part of method of the present invention
Sequence step by step can be exchanged with each other according to actual needs or part steps therein also can be omitted or delete.
Step S501, as shown in fig. 6, forming multiple semiconductor devices 130 on a wafer 200.In the present embodiment, institute
Stating semiconductor devices 130 can be illustrated with the metal part of semiconductor devices.It specifically, can be by the wafer 200
One surface by photoetching (photo), deposition (Depositing), etching (etching), etc. techniques formed and patterned partly lead
Body device 130.The wafer 200 can be made of either semiconductor wafer bare die 201 in the semiconductor crystal wafer bare die
It is constituted after 201 grown epitaxial layers 202.
Step S502, as shown in fig. 7, the wafer 200 for being formed with the semiconductor devices 130 is attached to substrate supports
On piece 300, and wafer 200 is carried out thinned.Specifically, the substrate supports piece 300 be attached to wafer 200 formed it is described
The side of semiconductor devices 130.The substrate supports piece 300 can be by materials systems such as sapphire, glass, silicon carbide and silicon wafers
At.In other embodiments, the substrate slice of thinner thickness also can be used as the wafer 200, to omit to described
Wafer 200 carries out thinned step.
, it is preferable to use adhesive 203 (such as optical cement OCA, OCR or Wax) is by substrate supports piece 300 in the present embodiment
It is attached to the side on wafer 200 close to the semiconductor devices 130.Thinned mode packet is carried out to the wafer 200
Include the techniques such as corase grinding, fine grinding and polishing.Corase grinding removal speed is fast, but roughness is big, can reach several hundred nanometers.Fine grinding removal amount
It is relatively slow, coarse about tens nanometers.It is most slow to polish removal amount, but the thick of wafer 200 can be made by polishing this step process
Rugosity meet demand.In addition, wafer 200 is thinned to 50 between 200um, under this thickness, if wafer 200 is again individually
The subsequent photoetching of carry out, etching, the techniques such as metallization, be easily broken.Therefore, in the present embodiment, wafer 200 is pasted first
It is attached on substrate supports piece 300, then carries out the techniques such as thinned again, it is broken to prevent wafer 200 from occurring in processing procedure.
Step S503 forms patterned cover far from a surface of the substrate supports piece 300 in the wafer 200
Film layer 220, to expose a part of the wafer 200.
Specifically, as shown in figure 8, it is heavy on a surface of the wafer 200 far from the substrate supports piece 300 first
One mask layer 210 of product.Specifically, the mask layer 210 can be formed by the methods of sputtering, plating, deposition.The mask layer
210 can be formed by the composition of the wherein one or more in nickel, aluminium, silica, silicon nitride, photoresist.
Then, as shown in figure 9, forming patterned protective layer 220 on the mask layer 210.Specifically, can exist first
One layer of protection materials are formed above the mask layer 210, which can be photoresist, such as positivity photoresist or negativity light
Resistance.Then, illumination and development are carried out to the protection materials, forms the patterned protective layer 220.Wherein, can be used as
Light shield 170 shown in Fig. 4 implements illumination and development, to be formed and the through-hole 150 and dicing lane in the protected material bed of material
The exposed region of 120 correspondingly-shapeds.
Finally, as shown in Figure 10, removing the part formation figure that the mask layer 210 is not blocked by the protective layer 220
The mask layer 210 of shape, to expose a part of the wafer 200.Wherein, the present embodiment can pass through wet etching or dry etching
Etching method performs etching the mask layer 210, to remove the part that do not blocked by the protective layer 220.
Step S504 as shown in figure 11 performs etching a part of the wafer 200 exposed, forms through-hole
150 and dicing lane 120, then remove the mask layer 210 on 200 surface of wafer.Wherein, the dicing lane 120 of formation is wrapped
It includes first part 121 and is connected to the second part 122 of 121 opposite end of first part.The width of the first part 121
Greater than the width of the second part 122.Preferably, the width of first part 121 is the 1 to 10 of the width of second part 122
Between times.
Specifically, RIE (Reactive Ion etching, reactive ion etching), ICP (Inductively can be used
Coupled Plasma, inductive coupling plasma etch), IBE (Ion Beam Etching, ion beam etching), the etchings such as ERC set
Standby a part exposed to the wafer 200 performs etching.In addition, by verifying, for same shape of through holes, etching
Aperture is bigger, and etch rate can be faster.So the design aperture of through-hole 150 is greater than the width of dicing lane 120 in the present embodiment
Degree, it is preferable that the diameter of through-hole 150 is 5 to 50 times of the maximum width (such as width of first part 121) of dicing lane 120.Its
The etching depth of stopping when middle through-hole 150 etches into the position of the semiconductor devices 130, dicing lane 120 passes through dicing lane 120
It is adjusted with the aperture design size ratio of through-hole 150.In this way, when the etching depth of through-hole 150 reaches semiconductor devices 130,
The etching depth of dicing lane 120 may make to control between 1/5 to the 4/5 of 200 thickness of wafer.
Step S505 forms patterned back metal far from the side of substrate supports piece 300 in the wafer 200
140, which is connect by the through-hole 150 with the metal part of the semiconductor devices 130.
Specifically, shown in Figure 12, one is formed far from the side of the substrate supports piece 300 in the wafer 200 first
Metal layer 230.
Then, as shown in figure 13, patterned etching barrier layer 240 is formed in the top of the metal layer 230.Specifically
Ground can form one layer of protection materials by coating method in the top of the metal layer 230 first.The protection materials can be light
Photoresist, such as positivity photoresist or negativity photoresist.Then, photoetching is carried out to the protection materials, forms the patterned etching resistance
Barrier 240.Wherein, illumination can be carried out to the protection materials and development forms the patterned etching barrier layer 240.
Finally, as shown in figure 14, not blocked by the patterned etching barrier layer 240 to the metal layer 230
Part performs etching, and then removes the etching barrier layer 240, forms the patterned back metal 140.
Step S506 removes the substrate supports piece from the wafer 200 close to the side of the semiconductor devices 130
300, form semiconductor crystal wafer 100 as shown in Figure 3.
Finally, the dicing lane 120 along the semiconductor crystal wafer 100 carries out sliver to the semiconductor crystal wafer 100
Form multiple independent chips 110 as shown in figure 15.
In conclusion the manufacturing method of semiconductor crystal wafer 100 provided in an embodiment of the present invention, semiconductor obtained from manufacture
The dicing lane 120 of wafer 100 includes two parts of different size, and passes through the size ratio of adjusting through-hole diameter and dicing lane width
Example, when realizing metal part of the via etch to semiconductor devices, dicing lane etching depth arrives for the 1/5 of 200 thickness of wafer
Between 4/5.Experiment proves that can reduce the fragment rate of semiconductor crystal wafer 200, product yield is improved.
It should also be noted that, in the description of the present invention unless specifically defined or limited otherwise, term " setting ",
" installation ", " connected ", " connection " shall be understood in a broad sense, for example, it may be fixedly connected, may be a detachable connection or one
Connect to body；It can be mechanical connection, be also possible to be electrically connected；It can be directly connected, it can also be indirect by intermediary
It is connected, can be the connection inside two elements.For the ordinary skill in the art, on being understood with concrete condition
State the concrete meaning of term in the present invention.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (11)
1. a kind of semiconductor crystal wafer, which is characterized in that the semiconductor crystal wafer includes:
Multiple spaced chips；And
The dicing lane being arranged at intervals between two neighboring chip, in which:
Each chip includes the semiconductor devices being formed on one surface of wafer, positioned at the back side on another surface of wafer
Metal and at least one through the wafer and connect semiconductor devices metal part and the back metal it is logical
Hole；Wherein, the through-hole is formed in same etching technics with the dicing lane；
Wherein, a dicing lane is set between two chips of arbitrary neighborhood, and each dicing lane includes first part and connection
In the second part of first part's opposite end, the width of first part is greater than the width of second part.
2. semiconductor crystal wafer according to claim 1, which is characterized in that the etched surface of the dicing lane and the etching of through-hole
Face is same etching surface, by adjusting the dimension scale of through-hole diameter and dicing lane width, so that through-hole is partly led etching into
When the metal part of body device, the dicing lane etches 1 to five/5th that the trench depth to be formed is the wafer thickness
Between/tetra-.
3. semiconductor crystal wafer according to claim 2, which is characterized in that the diameter of the through-hole be the dicing lane most
5 to 50 times of big width, when through-hole is ellipticity, the diameter refers to long side diameter.
4. semiconductor crystal wafer according to claim 3, which is characterized in that the width of the dicing lane first part is described
1 to 10 times of the width of second part.
5. semiconductor crystal wafer according to claim 1, which is characterized in that the wafer by silicon, sapphire, silicon carbide,
GaAs, gallium nitride one of which wafer bare die are formed on either silicon, sapphire, silicon carbide and gaas wafer bare die
It grown one of formation in the epitaxial wafer of epitaxial layer.
6. a kind of manufacturing method of semiconductor crystal wafer, which is characterized in that the described method includes:
The wafer for being formed with semiconductor devices is attached into substrate supports on piece；
Patterned mask layer is formed far from a surface of the substrate supports piece in the wafer, exposes the wafer
Piece needs a part etched；And
A part of the wafer exposed is performed etching, is formed through the through-hole of the wafer and including width
The dicing lane of different first part and second part, wherein the width of the first part is greater than the second part, it is described
Second part is connected to the opposite end of the first part.
7. the manufacturing method of semiconductor crystal wafer as claimed in claim 6, which is characterized in that attached in the wafer described
After substrate supports on piece, the method also includes:
The wafer is carried out thinned, wherein the wafer is thinned between 50 to 200 microns.
8. the manufacturing method of semiconductor crystal wafer as claimed in claim 7, which is characterized in that it is described in the wafer far from institute
It states the step of a surface of substrate supports piece forms patterned mask layer and includes:
A mask layer is deposited far from a surface of the substrate supports piece in the wafer；
A layer photoresist is formed above the mask layer, and visualization processing procedure, shape are carried out to photoresist using a reticle
At patterned protective layer；And
It removes the mask layer and the patterned mask layer is not formed by the part that the protective layer is blocked；
Wherein, the reticle includes and the through-hole corresponding first light passing portion and corresponding with the dicing lane second logical
Light portion, second light passing portion include the first light passing region corresponding with the first part of the dicing lane and with the scribing
The second part in road corresponding second light passing region, the width in first light passing region are greater than the width in second light passing region
Degree.
9. the manufacturing method of semiconductor crystal wafer as claimed in claim 6, which is characterized in that the method also includes:
Patterned back metal is formed far from the side of the substrate slice in the wafer, passes through the back metal described
Through-hole is connect with the semiconductor device electrical property；And
The substrate supports piece is removed from the wafer, isolates the semiconductor crystal wafer.
10. the manufacturing method of semiconductor crystal wafer as claimed in claim 6, which is characterized in that the method uses reactive ion
Etching, inductive coupling plasma etch or ion beam etching method perform etching a part of the wafer.
11. the manufacturing method of semiconductor crystal wafer as claimed in claim 6, which is characterized in that the patterned mask layer by
Nickel, aluminium, silica, silicon nitride, wherein one or more in photoresist composition formed.
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| CN107068611A (en) * | 2016-12-23 | 2017-08-18 | 苏州能讯高能半导体有限公司 | The manufacture method of semiconductor chip, semiconductor crystal wafer and semiconductor crystal wafer |
| CN107369611B (en) * | 2017-07-11 | 2020-03-17 | 上海朕芯微电子科技有限公司 | Novel wafer thinning back metallization process |
| CN108328570A (en) * | 2018-01-31 | 2018-07-27 | 北京航天控制仪器研究所 | A kind of MEMS chip splinter method and supporting tool with film back cavity structure |
| CN109052307B (en) * | 2018-07-09 | 2020-11-17 | 武汉耐普登科技有限公司 | Wafer structure and wafer processing method |
| CN109686700B (en) * | 2018-12-20 | 2020-07-07 | 吉林华微电子股份有限公司 | Chip to be filmed and processing technology thereof |
| CN110098131A (en) * | 2019-04-18 | 2019-08-06 | 电子科技大学 | A kind of power MOS type device and IC wafers grade reconstruct packaging method |
| US11942522B2 (en) | 2021-03-31 | 2024-03-26 | Changxin Memory Technologies, Inc. | Method for manufacturing semiconductor structure and semiconductor structure |
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| KR101446288B1 (en) * | 2008-03-25 | 2014-10-01 | 삼성전자주식회사 | Method Of Fabricating Semiconductor Device |
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| FR2549292A1 (en) * | 1983-07-12 | 1985-01-18 | Silicium Semiconducteur Ssc | Diode mounting method. |
| JPH04335552A (en) * | 1991-05-13 | 1992-11-24 | Sumitomo Electric Ind Ltd | Manufacture of semiconductor device |
| JP2003289076A (en) * | 2002-01-24 | 2003-10-10 | Matsushita Electric Ind Co Ltd | Soi semiconductor device and its manufacturing method |
| KR20090098175A (en) * | 2008-03-13 | 2009-09-17 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
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