KR20090098175A - Method for manufacturing semiconductor device - Google Patents

Abstract

A manufacturing method of a semiconductor device is provided to prevent generation of an abnormal layer due to reaction between copper and PiQ material by isolating a bonding pad and a PiQ(Polymide Isoindro Quirazorindione) layer formed by copper through an insulation material. An interlayer insulation film(23) is formed on a top part of a semiconductor substrate in which a fuse(22) is formed. A bonding pad(24) is formed on a top part of the interlayer insulation film. A passivation film(25) is formed on a top part of the interlayer insulation film including the bonding pad. The fuse and the bonding pad are exposed by etching the passivation film and the interlayer insulation film through a repair mask. A buffer nitride film(30) is formed on a top part of the passivation film, the fuse, and the bonding pad. A PiQ layer is formed on a top part of the buffer nitride film.

Description

Method for manufacturing semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, an abnormal layer caused by a reaction between copper (Cu) and a PiQ material by isolating a bonding pad and a PiQ layer made of copper (Cu) with an insulating material. It relates to a method of forming a semiconductor device capable of preventing the formation of the bonding process can be performed normally.

In general, the semiconductor device inspects the electrical characteristics of each memory device present on the wafer after completion of the manufacturing process to screen the good and bad. Here, if a defective cell in bits in the memory area within the device exists within the limit of repair, the defective cell is replaced with a spare cell already made in the device, and the good product is tested again.

This conventional semiconductor device wafer test method uses various pattern techniques of the VLSI memory test system to test the operating characteristics of the memory device and various defects in the memory region.

In addition, after dividing the semiconductor device into good, repairable, or defective products through testing, the repairable device that satisfies the repair algorithm is assigned an address to be repaired using a fail bit search utility in the test system. Save to a data file on the host computer.

Then, using a laser repair system for the repairable device, replace it with a spare cell by blowing a fuse based on the repair algorithm for each device, and then make a second electrical decision whether the replaced cell is operating normally. Judging by the characteristic test. Thereafter, the completed chip is packaged and completed.

Despite the increase in the integration of semiconductor devices, high-speed products are desired. To solve this problem, the metal line is shifting from aluminum (Al) to low resistivity copper (Cu).

However, when copper is used as a metal line, a bake process is performed when the PiX process is performed while copper is exposed in a general manufacturing process, and thus an abnormal layer is formed on the copper, and thus the bonding process cannot be performed.

1A to 1C are cross-sectional views illustrating a bonding pad opening method of a general semiconductor device. Here, (i) is sectional drawing of a main chip area | region, and (ii) is sectional drawing of a scribe lane area | region.

Referring to FIG. 1A, an interlayer insulating layer 13 is formed on a semiconductor substrate on which a process of forming a transistor, a metal wiring, a fuse 12, and the like is completed, and a bonding pad 14 is formed on the interlayer insulating layer 13. . Here, the fuse 12 is made of aluminum (Al), the bonding pad 14 is made of copper (Cu).

A passivation oxide 15 and a passivation nitride 16 are sequentially deposited on the interlayer insulating layer 13 including the bonding pads 14.

Subsequently, after the photoresist is applied over the protective nitride layer 16, the photoresist pattern 17 is exposed and developed to the photoresist using a repair mask in which a pad region, a fuse region, and a pad region of the scribe lane are defined. To form.

Referring to FIG. 1B, the protective oxide layer 15 and the protective nitride layer 16 of the pad region of the main chip and the pad region of the scribe lane are etched using the photoresist pattern 17 as an etching mask to expose the bonding pads 14. The protective oxide film 15, the protective nitride film 16, and the interlayer insulating film 13 in the fuse region of the main chip are etched to expose the fuse 12.

Referring to FIG. 1C, the photoresist pattern 17 is removed, and a polyisode quizorindione (PiQ) 18 is coated and baked on the protective nitride film 16 including the exposed bonding pads 14 and the fuse 11. Proceed with the bake process. At this time, since the copper (Cu) constituting the bonding pad 14 and the PiQ 18 react with each other to form an abnormal layer 19, a subsequent pad bonding process may not be normally performed.

Referring to FIG. 1D, the PiQ 18 is etched using a PiX mask in which a pad region, a fuse region, and a scribe lane of a main chip are defined to form a PiQ pattern 18a.

As described above, in order to prevent a problem in the pad bonding process due to the reaction between the copper (Cu) constituting the pad and the PiQ during PiQ coating after the pad etching, the copper constituting the bonding pad 14 is not exposed. Although it may be etched, it may be difficult to etch so as not to expose the bonding pad 14 due to an etch selectivity problem due to the step between the bonding pad 14 and the fuse 12. That is, an additional mask step is required to simultaneously etch the bonding pad 14 and the fuse 12.

In the present invention, when the bonding pad is formed of copper (Cu), a semiconductor device may be formed to prevent the formation of an abnormal layer due to contact between the copper (Cu) and the PiQ layer in the baking process, thereby performing the normal bonding process. It is an object to provide a method.

The method of forming a semiconductor device according to the present invention

Forming an interlayer insulating film on the semiconductor substrate on which the fuse is formed;

Forming a bonding pad on the interlayer insulating film;

Forming a protective film on the interlayer insulating film including the bonding pads;

Etching the passivation layer and the interlayer insulating layer by using a repair mask defining a bonding pad region, a fuse region, and a bonding pad region of a scribe lane of the main chip to expose the fuse and the bonding pad;

Forming a buffer nitride layer on the bonding pad, the fuse, and the passivation layer;

Forming a PiQ layer on the buffer insulating layer; And

Etching the PiQ layer and the buffer nitride layer using a PiX mask in which a fuse region, a bonding pad region, and the scribe lane region of the main chip are defined.

In addition, the forming of the PiQ layer further includes performing a baking process,

The passivation layer is formed by sequentially depositing a passivation oxide and a passivation nitride,

The protective oxide film is implemented as an HDP (High Density Plasma) oxide film,

The bonding pad is made of copper (Cu),

The etching of the protective film and the insulating film is

Applying a photoresist film on the protective film;

Forming a photoresist pattern on the photoresist using the repair mask through an exposure and development process; And

Etching the passivation layer and the insulating layer of the fuse area of the main chip using the photoresist pattern as an etching mask;

The fuse is made of aluminum (Al),

The PiQ layer is embodied in poly amide or poly benjo oxazol,

The bonding pads are formed by a damascene process.

The present invention isolates the bonding pad and the PiQ layer made of copper (Cu) with an insulating material to prevent the formation of an abnormal layer due to contact of the copper (Cu) and the PiQ layer in the baking process, thereby normal bonding process There is an effect that can be performed.

In addition, the present invention has an effect of preventing wafer sawing defects by completely removing the PiQ layer in the scribe lane after the PiQ patterning process using the PiX mask.

In addition, since the present invention blocks the bonding pads made of copper (Cu) with an insulating material, it is possible to prevent contamination by copper (Cu) even when the wafer is exposed in the manufacturing equipment during the PiQ patterning process using the PiX mask. have.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the spirit of the present invention is thoroughly and completely disclosed, and the spirit of the present invention to those skilled in the art will be fully delivered. Also, like reference numerals denote like elements throughout the specification.

2A to 2F are cross-sectional views illustrating a bonding pad opening method of a general semiconductor device. Here, (i) is sectional drawing of a main chip area | region, and (ii) is sectional drawing of a scribe lane area | region.

Referring to FIG. 2A, an interlayer insulating film 23 is formed on a semiconductor substrate on which a process of forming transistors, metal wirings, fuses 22, and the like is completed, and a bonding pad 24 is formed on the interlayer insulating film 23. do. Here, the fuse 22 is described as an example of implementing aluminum (Al), but may be a metal material such as poly, copper (Cu), tungsten (W), if necessary. In addition, the bonding pad 24 is made of copper (Cu). The bonding pad 24 may be formed through a damascene process.

A passivation oxide 25 and a passivation nitride 26 are sequentially deposited on the interlayer insulating layer 23 including the bonding pads 24.

Subsequently, after the photoresist is applied over the protective nitride layer 26, the photoresist pattern 27 is exposed and developed to the photoresist using a repair mask in which a pad region, a fuse region, and a pad region of the scribe lane are defined. To form.

Referring to FIG. 2B, the protective oxide layer 25 and the protective nitride layer 26 of the pad region of the main chip and the pad region of the scribe lane are etched using the photoresist pattern 27 as an etching mask to expose the bonding pad 24. The protective oxide film 25, the protective nitride film 26, and the interlayer insulating film 23 in the fuse region of the main chip are etched to expose the fuse 22.

2C and 2D, the photoresist layer pattern 27 is removed, and a buffer nitride layer 30 is formed on the protective nitride layer 26 including the exposed bonding pads 24 and the fuses 22. Polymide Isoindro Quirazorindione (PiQ) 28 is sequentially deposited and a bake process is performed. Here, the PiQ material uses poly amide, poly benzoxazole, and the like.

Meanwhile, the buffer nitride film 30 may prevent the bonding pad 24 from reacting with the PiQ 28. That is, the buffer nitride film 30 acts as a reaction prevention film to prevent the reaction of copper (Cu) and PiQ. In addition, the buffer nitride film 30 may use an insulating film such as an oxide film as necessary.

Referring to FIG. 2E, the PiQ 28 is etched using a PiX mask in which a pad region, a fuse region, and a scribe lane of a main chip are defined to form a PiQ pattern 28a.

Referring to FIG. 2F, the fuse 22, the bonding pad 24, and the buffer nitride film 30 on the protective nitride film 26 of the scribe lane are removed.

As described above, the present invention isolates the bonding pad and the PiQ layer made of copper (Cu) with an insulating material, thereby preventing the formation of an abnormal layer due to the reaction between the copper (Cu) and the PiQ material. Disclosed are techniques that can be performed normally.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such modifications, changes, etc. are the following patents It should be regarded as belonging to the claims.

1A to 1D are cross-sectional views illustrating a bonding pad opening method of a general semiconductor device.

2A through 2E are cross-sectional views illustrating a bonding pad opening method of a general semiconductor device.

<Description of Signs for Main Parts of Drawings>

22: fuse 23: interlayer insulating film

24: bonding pad 25: protective oxide film

26: protective nitride film 27: photosensitive film pattern

28: PiQ 28a: PiQ Pattern

30: buffer nitride film

Claims (9)

Forming an interlayer insulating film on the semiconductor substrate on which the fuse is formed; Forming a bonding pad on the interlayer insulating film; Forming a protective film on the interlayer insulating film including the bonding pads; Etching the passivation layer and the interlayer insulating layer by using a repair mask defining a bonding pad region, a fuse region, and a bonding pad region of a scribe lane of the main chip to expose the fuse and the bonding pad; Forming a buffer nitride layer on the bonding pad, the fuse, and the passivation layer; Forming a PiQ layer on the buffer insulating layer; And Etching the PiQ layer and the buffer nitride layer using a PiX mask in which a fuse region, a bonding pad region, and the scribe lane region of the main chip are defined. The method of claim 1, The forming of the PiQ layer further comprises performing a baking process. The method of claim 1, And the passivation layer is formed by sequentially depositing a passivation oxide and a passivation nitride. The method of claim 3, wherein The protective oxide film is a semiconductor device formation method, characterized in that implemented by HDP (High Density Plasma) oxide film. The method of claim 1, The bonding pad may be formed of copper (Cu). The method of claim 1, The etching of the protective film and the insulating film is Applying a photoresist film on the protective film; Forming a photoresist pattern on the photoresist using the repair mask through an exposure and development process; And And etching the passivation layer and the insulating layer in the fuse area of the main chip using the photoresist pattern as an etching mask. The method of claim 1, The fuse is a semiconductor device forming method, characterized in that implemented by aluminum (Al). The method of claim 1, The method of forming a semiconductor device, characterized in that the PiQ layer is implemented with polyamide or poly benjo oxazol. The method of claim 1, The bonding pads are formed by a damascene process.

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