CN106206395A - The method improving IGBT back side stress - Google Patents
The method improving IGBT back side stress Download PDFInfo
- Publication number
- CN106206395A CN106206395A CN201610620546.6A CN201610620546A CN106206395A CN 106206395 A CN106206395 A CN 106206395A CN 201610620546 A CN201610620546 A CN 201610620546A CN 106206395 A CN106206395 A CN 106206395A
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- back side
- stress
- method improving
- glass slide
- organic bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a kind of method improving IGBT back side stress, on front side of silicon wafer passivation layer cover polyimides, photoetching and etch patterning after, at whole silicon chip surface application of adhesive, be then stained with glass slide.Described binding agent is substantially filled in the depression after polyimides etching and gap, and glass slide forms stress-buffer layer together with binding agent.
Description
Technical field
The present invention relates to IC design and manufacture field, particularly relate to a kind of method improving IGBT back side stress.
Background technology
IGBT (Insulated Gate Bipolar Transistor) insulated gate bipolar transistor, is (double by BJT
Polar form audion) and the compound full-control type voltage driven type power semiconductor that forms of MOS (insulating gate type field effect tube), hold concurrently
There is advantage of both the high input impedance of MOSFET and the low conduction voltage drop of GTR.Being highly suitable to be applied for DC voltage is
The fields such as 600V and above converter system such as alternating current generator, converter, Switching Power Supply, lighting circuit, Traction Drive.
Common IGBT structure is as it is shown in figure 1, substrate 1 front, i.e. Fig. 1 first half is the grid 2 in IGBT front, gate oxidation
Layer 3, p-well 4, front metal line 7 etc..The back side, i.e. Fig. 1 lower half is IGBT back structure, and including cushion 9, the back side is injected
Layer 10, and metal layer on back 11.Metal layer on back is the composite bed of Al-Ti-Ni-Ag.
From the point of view of IGBT technique, thickness is the thinnest, and corresponding conduction voltage drop and dynamic loss all can reduce.But it is the thinnest
Silicon chip particularity due to front description in milled processed can cause stress problem, causes sliver time serious.For highly reliable
Property IGBT, need on the passivation layer of front cover polyimides (Polyimide), as shown in Figure 2.Due to polyimide thickness
Relatively big, in grinding overleaf, unbalance stress causes the biggest stress, and back side time serious is it can be seen that obvious front description pattern.
The stress of silicon chip back side is concentrated mainly on street area, because step is maximum herein, in subsequent technique, particularly laser moves back
Fire, owing to laser annealing quickly (Microsecond grade) can produce liter gentleness cooling in local, STRESS VARIATION is big especially, and silicon chip is easily being drawn
Split in film channel district.
Summary of the invention
The technical problem to be solved is to provide a kind of method improving IGBT stress, solves silicon chip and easily exists
The splintery problem in scribe area.
For solving the problems referred to above, the method improving IGBT stress of the present invention, for front side of silicon wafer passivation layer overlying
Lid polyimides, photoetching and etch patterning after, at whole silicon chip surface application of adhesive, be then stained with glass slide.
The method improving IGBT back side stress of the present invention, described binding agent is substantially filled to polyimides and etches it
After depression and gap in, glass slide forms stress-buffer layer together with binding agent.
The method improving IGBT back side stress of the present invention, the step comprised is:
1st step, spin coating organic bond on glass slide；
2nd step, is coated with organic bond at front side of silicon wafer；
3rd step, front side of silicon wafer alignment scribbles the glass slide of organic bond, both is bonded；
4th step, carries out ultraviolet baking；
5th step, carries out thinning back side by the silicon chip with glass slide；
6th step, heats the silicon chip with glass slide；
7th step, separation of glasses slide glass and silicon chip, remove the binding agent of front side of silicon wafer；
8th step, nitrogen dries up silicon chip, the wet etching scale back side, carries out back side injection, laser annealing and smithcraft.
Described 1st step, organic bond coating thickness is 10～15 μm.
Described 2nd step, organic bond coating thickness is 10～15 μm.
Described 4th step, ultraviolet irradiation temperature 300～350 DEG C.
Described 5th step, depending on thinning thickness is according to specific product.
Described 6th step, heating-up temperature is 300～350 DEG C.
The method improving IGBT stress of the present invention, by glass slide by binding agent and Wafer bonding, binding agent
Form stress-buffer layer with glass slide, to improve the stress of silicon chip, reduce the stress of high stepped area in process of lapping, have
Effect improves the sliver problem that back side stress causes.
Accompanying drawing explanation
Fig. 1 is existing IGBT structure schematic diagram.
Fig. 2 is that polyimides is at scribe line district pattern.
Fig. 3 is the silicon chip that the present invention bonds glass slide.
Description of reference numerals
1 is silicon substrate, and 2 is grid, and 3 is gate oxide, and 4 is p-well, and 5 is p-type heavily doped region, and 6 is N-type heavily doped region, 7
Being metal connecting line, 8 is inter-level dielectric, and 9 is N-type field stop layer, and 10 is back side p-type implanted layer, and 11 is back metal, and 12 is polyamides
Imines, 13 is binding agent, and 14 is glass slide.
Detailed description of the invention
The method improving IGBT stress of the present invention, as it is shown on figure 3, gather for covering on front side of silicon wafer passivation layer
Acid imide 12, photoetching and etch patterning after, whole silicon chip surface coat organic bond 13, be then stained with glass slide
14.Described organic bond 13 is substantially filled in the depression after polyimides etching, patterning and gap, glass slide 14
Stress-buffer layer is formed together with organic bond 13.
The method improving IGBT back side stress of the present invention, the step comprised is:
1st step, on glass slide, spin coating thickness is the organic bond of 10～15 μm.
2nd step, at the organic bond that front side of silicon wafer also coating thickness is 10～15 μm.
3rd step, front side of silicon wafer alignment scribbles the glass slide of organic bond, both is bonded.
4th step, carries out the ultraviolet baking that temperature is 300～350 DEG C.
5th step, carries out thinning back side by the silicon chip with glass slide, depending on thinning thickness is according to specific product.
6th step, heats the silicon chip with glass slide, and using temperature is 300～350 DEG C.
7th step, separation of glasses slide glass and silicon chip, remove the binding agent of front side of silicon wafer；
8th step, nitrogen dries up silicon chip, the wet etching scale back side, carries out back side injection, laser annealing and smithcraft.
The method improving IGBT stress of the present invention, by glass slide by binding agent and Wafer bonding, binding agent
Form stress-buffer layer with glass slide, to improve the stress of silicon chip, reduce the stress of high stepped area in process of lapping, have
Effect improves the sliver problem that back side stress causes.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.Those skilled in the art is come
Saying, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, any amendment of being made, equivalent
Replacement, improvement etc., should be included within the scope of the present invention.
Claims (8)
1. the method improving IGBT back side stress, it is characterised in that: the polyamides for covering on front side of silicon wafer passivation layer is sub-
Amine, photoetching and etch patterning after, whole silicon chip surface coat organic bond, be then stained with glass slide.
The method improving IGBT back side stress the most as claimed in claim 1, it is characterised in that: described organic bond is fully filled out
Being charged in the depression after polyimides etching and gap, glass slide forms stress-buffer layer together with organic bond.
The method improving IGBT back side stress the most as claimed in claim 1, it is characterised in that: the step comprised is:
1st step, spin coating organic bond on glass slide；
2nd step, is coated with organic bond at front side of silicon wafer；
3rd step, front side of silicon wafer alignment scribbles the glass slide of organic bond, both is bonded；
4th step, carries out ultraviolet baking；
5th step, carries out thinning back side by the silicon chip with glass slide；
6th step, heats the silicon chip with glass slide；
7th step, separation of glasses slide glass and silicon chip, remove the binding agent of front side of silicon wafer；
8th step, nitrogen dries up silicon chip, the wet etching scale back side, carries out back side injection, laser annealing and smithcraft.
The method improving IGBT back side stress the most as claimed in claim 3, it is characterised in that: described 1st step, organic bond
Coating thickness is 10～15 μm.
The method improving IGBT back side stress the most as claimed in claim 3, it is characterised in that: described 2nd step, organic bond
Coating thickness is 10～15 μm.
The method improving IGBT back side stress the most as claimed in claim 3, it is characterised in that: described 4th step, ultraviolet irradiates
Temperature 300～350 DEG C.
The method improving IGBT back side stress the most as claimed in claim 3, it is characterised in that: described 5th step, thinning thickness
Depending on specific product.
The method improving IGBT back side stress the most as claimed in claim 3, it is characterised in that: described 6th step, heating-up temperature is
300～350 DEG C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610620546.6A CN106206395A (en) | 2016-08-01 | 2016-08-01 | The method improving IGBT back side stress |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610620546.6A CN106206395A (en) | 2016-08-01 | 2016-08-01 | The method improving IGBT back side stress |
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| Publication Number | Publication Date |
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| CN106206395A true CN106206395A (en) | 2016-12-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610620546.6A Pending CN106206395A (en) | 2016-08-01 | 2016-08-01 | The method improving IGBT back side stress |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113013061A (en) * | 2021-02-23 | 2021-06-22 | 绍兴同芯成集成电路有限公司 | Method for processing compound semiconductor by using organic film |
| CN114420621A (en) * | 2021-11-17 | 2022-04-29 | 武汉新芯集成电路制造有限公司 | Bonding method and semiconductor structure |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120292662A1 (en) * | 2011-05-16 | 2012-11-22 | Renesas Electronics Corporation | Ie-type trench gate igbt |
| CN103035694A (en) * | 2012-12-04 | 2013-04-10 | 国网智能电网研究院 | Insulated gate bipolar translator (IGCB) chip with terminal protection structure and manufacturing method of IGCB chip with terminal protection structure |
| CN103050480A (en) * | 2012-08-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Technical method for imaging rear side of silicon wafer |
| CN103274350A (en) * | 2013-05-16 | 2013-09-04 | 北京大学 | Heat insulation structure based on Parylene filling and preparation method thereof |
| CN103765598A (en) * | 2011-09-11 | 2014-04-30 | 科锐 | Edge termination structure employing recesses for edge termination elements |
| CN104332455A (en) * | 2014-09-25 | 2015-02-04 | 武汉新芯集成电路制造有限公司 | Structure of silicon through hole based semiconductor device on chip, and preparation method of the semiconductor device |
-
2016
- 2016-08-01 CN CN201610620546.6A patent/CN106206395A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120292662A1 (en) * | 2011-05-16 | 2012-11-22 | Renesas Electronics Corporation | Ie-type trench gate igbt |
| CN103765598A (en) * | 2011-09-11 | 2014-04-30 | 科锐 | Edge termination structure employing recesses for edge termination elements |
| CN103050480A (en) * | 2012-08-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Technical method for imaging rear side of silicon wafer |
| CN103035694A (en) * | 2012-12-04 | 2013-04-10 | 国网智能电网研究院 | Insulated gate bipolar translator (IGCB) chip with terminal protection structure and manufacturing method of IGCB chip with terminal protection structure |
| CN103274350A (en) * | 2013-05-16 | 2013-09-04 | 北京大学 | Heat insulation structure based on Parylene filling and preparation method thereof |
| CN104332455A (en) * | 2014-09-25 | 2015-02-04 | 武汉新芯集成电路制造有限公司 | Structure of silicon through hole based semiconductor device on chip, and preparation method of the semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113013061A (en) * | 2021-02-23 | 2021-06-22 | 绍兴同芯成集成电路有限公司 | Method for processing compound semiconductor by using organic film |
| CN113013061B (en) * | 2021-02-23 | 2023-06-02 | 绍兴同芯成集成电路有限公司 | Method for processing compound semiconductor by using organic film |
| CN114420621A (en) * | 2021-11-17 | 2022-04-29 | 武汉新芯集成电路制造有限公司 | Bonding method and semiconductor structure |
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Application publication date: 20161207 |