CN104576367B - The ameliorative way of IGBT negative resistance problem - Google Patents
The ameliorative way of IGBT negative resistance problem Download PDFInfo
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- CN104576367B CN104576367B CN201410307058.0A CN201410307058A CN104576367B CN 104576367 B CN104576367 B CN 104576367B CN 201410307058 A CN201410307058 A CN 201410307058A CN 104576367 B CN104576367 B CN 104576367B
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Abstract
The invention discloses a kind of ameliorative ways of IGBT negative resistance problem, comprising steps of selecting substrate material and carrying out back thinning.Back side first time N-type heavy doping ion is carried out to inject to form the second N-type field stop layer.Carry out thermal annealing.Complete the front description technique of IGBT.Wet etching is carried out to substrate back.Second of back side N-type heavy doping ion is carried out to inject to form the second N-type field stop layer.Back side p-type heavy doping ion is carried out to inject to form p-type implanted layer.Carry out laser annealing activation.Form metal layer on back.The present invention can form thicker back surface field stop layer and can eliminate the negative resistance effect of IGBT, improve the reliability of product, can existing semiconductor technology compatibility, process costs it is low.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture methods, more particularly to a kind of improvement of IGBT negative resistance problem
Method.
Background technique
Insulated gate bipolar transistor (IGBT, Insulated Gate Bipolar Transistor), is by ambipolar
The compound full-control type voltage driven type power semiconductor device of triode (BJT) and insulating gate type field effect tube (MOSFET) composition
Part has the high input impedance and power transistor (GTR) i.e. high voltage withstanding, high current bipolar junction transistor of MOSFET concurrently
Advantage of both low conduction voltage drop.It is highly suitable to be applied for the converter system such as alternating current that DC voltage is 600V or more
The fields such as machine, frequency converter, Switching Power Supply, lighting circuit, Traction Drive.
For high pressure IGBT technique, being capable of forming thicker back side N+ buffer layer has the performance boost of IGBT product
Great meaning.Industry has the forming method of more thick N+ buffer layer at present, but manufactures with general semiconductor integrated circuit
The technique of factory (FAB) is usually incompatible, needs in addition to create FAB to produce.
As shown in Figure 1, the structural schematic diagram for the IGBT that existing method is formed；Pass through the lining in n-type doping in existing method
The front of bottom material such as silicon substrate 101 is formed before front description, is carried out back thinning to substrate 101, and injected, annealed
The method for pushing away trap forms the buffer layer i.e. N-type field stop layer 110 with a thickness of 10 microns~20 microns.Form N-type field stop layer 110
Front description technique is just carried out later, and the front description technique includes cellular region and pressure-resistant protection zone, and pressure-resistant protection zone surrounds
In the side of cellular region.The cellular region is formed with the cellular construction of IGBT, and the cellular construction of the IGBT includes:
P-well 104, p-well 104 are formed in the front of substrate 101.
Polysilicon gate 102, isolation has gate oxide 103 between the polysilicon gate 102 and the p-well 104.
Emitter region 105, the N-type heavily doped region by being formed in 104 surface of p-well are formed, are covered by the polysilicon gate 102
104 surface of the p-well of lid is used to form the channel for connecting the emitter region 105 and the N-type drift region.Emitter region 105
That is the source region of the MOS device in IGBT.
P-well draw-out area 105, is made of p-type heavily doped region；The p-well draw-out area 105 enters across the emitter region 105
Into the p-well 104, the p-well draw-out area 105 is contacted with the emitter region 105 and the p-well 104 simultaneously.
Front metal layer 109, grid and emitter are made of front metal layer 109 respectively, and grid is by passing through interlayer film
107 contact hole 108 and the polysilicon gate 102 contact, emitter are connect by contact hole 108 and the p-well draw-out area 105
Touching.
After front description technique is completed, it carries out back side p-type heavy doping ion to inject to form p-type implanted layer 111, by described
The collecting zone of the composition of p-type implanted layer 111 IGBT；Laser annealing activation is carried out to the p-type implanted layer 111；And in the substrate
101 back side forms metal layer on back 112, and metal layer on back 112 is used as collector.
The shortcoming that existing method is after forming N-type field stop layer 110 in front of the graphic process, the back side is non-
It often is readily incorporated impurity, causes p-type injection in the back side uneven, is i.e. the doping of p-type implanted layer 111 can be uneven, this meeting is so that produce
There is the problem of Vcesat negative resistance in product, and Vcesat is collector and emitter saturation voltage.Fig. 2 is IGBT shown in Fig. 1
Vcesat curve 201；Abscissa is Vcesat, and ordinate is Ic, and Ic is collector current；It can be seen that the dotted line of curve 201
There are electric currents to increase and negative resistance phenomenon that voltage can reduce in region corresponding to 202, the reason is that the doping meeting of p-type implanted layer 111
When uneven, after IGBT is opened, when Vce namely the collector and emitter voltage is small, 111 note of p-type implanted layer of position
Entering hole efficiency into drift region can be uneven, with Vce increase when the p-type implanted layer 111 of position all start into
Row hole can carry out conductance modulation to drift region and reduce the conducting resistance of drift region when injecting and being connected, collector current increases
Add to export negative resistance effect.
The appearance of negative resistance effect can eventually lead to dynamic test shutdown failure, as shown in figure 3, being the dynamic of IGBT shown in Fig. 1
State curve；Curve 203 is grid voltage, that is, Vg curve, curve 204 is Ic curve, curve 205 is Vce curve, shown in dotted line 206
Region corresponds to process when shutdown, it can be seen that and after Vg is reduced to low level, there is no reduction, Vce also not to rise by Ic,
So shutdown failure.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of ameliorative ways of IGBT negative resistance problem, can be formed thicker
Back surface field stop layer simultaneously can eliminate the negative resistance effect of IGBT, improve the reliability of product, being capable of existing semiconductor technology compatibility, work
Skill is at low cost.
In order to solve the above technical problems, the ameliorative way of IGBT negative resistance problem provided by the invention includes the following steps:
Step 1: the substrate material of selection n-type doping；The substrate is carried out back thinning.
It injects to form the termination of the first N-type field Step 2: carrying out first time N-type heavy doping ion to the back side of the substrate
Layer.
Step 3: carrying out thermal annealing to the first N-type field stop layer.
Step 4: completing the front description technique of IGBT, the p-well of the front description technique and institute in the substrate face
The substrate is stated between the first N-type field stop layer as N-type drift region.
Step 5: carrying out wet etching to the substrate back for completing the front description technique, which will
The back side of the first N-type field stop layer removes certain thickness.
It injects to form the termination of the second N-type field Step 6: carrying out second of N-type heavy doping ion to the back side of the substrate
Layer, the junction depth of the second N-type field stop layer are shallower than the junction depth of the first N-type field stop layer, are terminated by first N-type field
The field stop layer of layer and the second N-type field stop layer composition IGBT, improves the field by the first N-type field stop layer
The thickness of stop layer is eliminated by the second N-type field stop layer and described is introduced into the lining in front of the graphic process
Influence of the impurity of bottom back side to the p-type implanted layer being subsequently formed.
It injects to form the p-type implanted layer, the p-type Step 7: carrying out p-type heavy doping ion to the back side of the substrate
Implanted layer is located on the back of the second N-type field stop and is made of the p-type implanted layer the collecting zone of IGBT.
Step 8: carrying out laser annealing activation to the second N-type field stop layer and the p-type implanted layer.
Step 9: forming metal layer on back at the back side of the substrate.
A further improvement is that the implantation dosage of the injection of first time N-type heavy doping ion described in step 2 is 2E13cm-2~
3E13cm-2, Implantation Energy 1.5MeV.
A further improvement is that be 1200 DEG C to the temperature of the thermal annealing of the first N-type field stop layer in step 3, when
Between be 1200 minutes.
A further improvement is that wet etching described in step 5 removed the back side of the first N-type field stop layer
With a thickness of 3 microns~5 microns.
A further improvement is that the implantation dosage of the injection of second of N-type heavy doping ion described in step 6 is 1E12cm-2~
3E12cm-2, Implantation Energy 450KeV.
A further improvement is that the implantation dosage that the p-type heavy doping ion of p-type implanted layer described in step 7 is injected
For 1E13cm-2~2E13cm-2, Implantation Energy 40KeV.
A further improvement is that the laser irradiation amount of laser annealing described in step 8 is 2.5J/cm2。
A further improvement is that the doping concentration of N-type drift region substrate as selected in step 1 is mixed
Miscellaneous concentration determines that the N-type drift region thickness is determined by the technique for thinning back side in step 1, and the operating voltage of IGBT is higher,
The thickness of the N-type drift region is bigger, doping concentration is smaller.
A further improvement is that the front description technique includes cellular region and pressure-resistant protection zone.
A further improvement is that the cellular region is formed with the cellular construction of IGBT, the cellular construction of the IGBT includes:
Polysilicon gate, isolation has gate oxide between the polysilicon gate and the p-well.
Emitter region, the N-type heavily doped region by being formed in the p-well surface form, the P covered by the polysilicon gate
Trap surface is used to form the channel for connecting the emitter region and the N-type drift region.
P-well draw-out area, is made of p-type heavily doped region；The p-well draw-out area passes through the emitter region and enters the p-well
In, the p-well draw-out area is contacted with the emitter region and the p-well simultaneously.
Front metal layer, grid and emitter are made of front metal layer respectively, and grid passes through contact hole and the polycrystalline
Si-gate contact, emitter are contacted by contact hole and the p-well draw-out area.
The method of the present invention by carrying out carrying out back thinning substrate before front description technique, injecting, annealing pushes away trap
Method can form the first thicker N-type field stop layer, so as to field stop layer thickness need, guarantee product performance；Pass through
After the positive graphic process, certain thickness wet etching is carried out to the first N-type field stop layer and carries out the back side and inject to be formed
The second relatively thin N-type field stop layer, can eliminate be introduced into front of the graphic process the first N-type field stop layer the back side it is miscellaneous
Matter eliminates negative resistance effect, and improve the reliability of product so as to make subsequent p-type injection uniformly.
In addition, the technique of the method for the present invention can existing semiconductor technology compatibility, so can be given birth in existing FAB
It produces, does not need in addition to create FAB to produce, process costs are low.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the structural schematic diagram for the IGBT that existing method is formed；
Fig. 2 is the Vcesat curve of IGBT shown in Fig. 1；
Fig. 3 is the performance graph of IGBT shown in Fig. 1；
Fig. 4 is flow chart of the embodiment of the present invention；
Fig. 5 is the structural schematic diagram for the IGBT that present invention method is formed；
Fig. 6 is the Vcesat curve of IGBT shown in Fig. 5；
Fig. 7 is the performance graph of IGBT shown in Fig. 6.
Specific embodiment
As shown in figure 4, being flow chart of the embodiment of the present invention；As shown in figure 5, being that present invention method is formed
The structural schematic diagram of IGBT；The ameliorative way of IGBT negative resistance problem of the embodiment of the present invention includes the following steps:
Step 1: the substrate 1 such as silicon substrate material of selection n-type doping；The substrate 1 is carried out back thinning.
The doping concentration of N-type drift region doping concentration of the substrate 1 as selected in step 1 determines, described
N-type drift region thickness is determined by the technique for thinning back side in step 1, and the operating voltage of IGBT is higher, the N-type drift region
Thickness is bigger, doping concentration is smaller.
In preferred embodiment one, the operating voltage for being formed by device is 3300V, and the resistivity of the substrate 1 is 220
Ohmcm~280 ohmcms, the substrate 1 be thinned after with a thickness of 530 microns~570 microns.
In preferred embodiment two, the operating voltage for being formed by device is 4500V, and the resistivity of the substrate 1 is 380
Ohmcm~480 ohmcms, the substrate 1 be thinned after with a thickness of 530 microns~570 microns.
In preferred embodiment three, the operating voltage for being formed by device is 4500V, and the resistivity of the substrate 1 is 600
Ohmcm~700 ohmcms；The substrate 1 be thinned after with a thickness of 670 microns~750 microns, the substrate 1
It can not be thinned.
It injects to form the termination of the first N-type field Step 2: carrying out first time N-type heavy doping ion to the back side of the substrate 1
Layer 10.The implantation dosage of the first time N-type heavy doping ion injection is 2E13cm-2~3E13cm-2, Implantation Energy is
1.5MeV。
Step 3: carrying out thermal annealing to the first N-type field stop layer 10.To the heat of the first N-type field stop layer 10
The temperature of annealing is 1200 DEG C, and the time is 1200 minutes.
Step 4: completing the front description technique of IGBT, 4 He of p-well of the front description technique in the front of substrate 1
The substrate 1 is used as N-type drift region between the first N-type field stop layer 10.
The front description technique includes cellular region and pressure-resistant protection zone, and the pressure resistance protection zone is centered around the cellular region
Side.The cellular region is formed with the cellular construction of IGBT, and the cellular construction of the IGBT includes:
Polysilicon gate 2, isolation has gate oxide 3 between the polysilicon gate 2 and the p-well 4.
Emitter region 5, the N-type heavily doped region by being formed in 4 surface of p-well form, the institute covered by the polysilicon gate 2
It states 4 surface of p-well and is used to form the channel for connecting the emitter region 5 and the N-type drift region.
P-well draw-out area 6, is made of p-type heavily doped region；The p-well draw-out area 6 passes through the emitter region 5 and enters the P
In trap 4, the p-well draw-out area 6 is contacted with the emitter region 5 and the p-well 4 simultaneously；
Front metal layer 9, grid and emitter are made of front metal layer 9 respectively, and grid is by passing through connecing for interlayer film 7
Contact hole 8 and the polysilicon gate 2 contact, and emitter is contacted by contact hole 8 and the p-well draw-out area 6.
Step 5: carrying out wet etching to 1 back side of the substrate for completing the front description technique, which will
The back side of the first N-type field stop layer 10 removes certain thickness.The wet etching is by the first N-type field stop layer 10
The back side removal with a thickness of 3 microns~5 microns.
It injects to form the termination of the second N-type field Step 6: carrying out second of N-type heavy doping ion to the back side of the substrate 1
Layer 13, the junction depth of the second N-type field stop layer 13 is shallower than the junction depth of the first N-type field stop layer 10, by first N-type
The field stop layer of field stop layer 10 and the second N-type field stop layer 13 composition IGBT, passes through the first N-type field stop layer 10
The thickness of the field stop layer is improved, the front description technical process eliminated by the second N-type field stop layer 13
In be introduced into influence of the impurity at 1 back side of substrate to the p-type implanted layer 11 being subsequently formed.Second of N-type heavy doping
The implantation dosage of ion implanting is 1E12cm-2~3E12cm-2, Implantation Energy 450KeV.
It injects to form the p-type implanted layer 11 Step 7: carrying out p-type heavy doping ion to the back side of the substrate 1, it is described
P-type implanted layer 11 is located at 13 back side of the second N-type field stop layer and is made of the collecting zone of IGBT the p-type implanted layer 11.
The implantation dosage of the p-type heavy doping ion injection of the p-type implanted layer 11 is 1E13cm-2~2E13cm-2, Implantation Energy
For 40KeV.
Step 8: carrying out laser annealing activation to the second N-type field stop layer 13 and the p-type implanted layer 11；
Step 9: forming metal layer on back 12 at the back side of the substrate 1.
As shown in fig. 6, being the Vcesat curve 301 of IGBT shown in Fig. 5；Abscissa is Vcesat, and ordinate is Ic, and bent
Line 201 compares it is found that there is no negative resistance effects in the curve 301 of the embodiment of the present invention.
Fig. 7 is the performance graph of IGBT shown in Fig. 6, curve 302 is grid voltage, that is, Vg curve, curve 303 be Ic curve,
Curve 304 is Vce curve, it can be seen that after high level is reduced to low level during shut-off, Ic is reduced Vg, Vce rises, shutdown when shutdown
Correctly.It is known from comparing Figure 7 with Figure 3 that the embodiment of the present invention eliminates the dynamic test shutdown failure of the IGBT of existing method formation
Defect.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (10)
1. a kind of ameliorative way of IGBT negative resistance problem, which comprises the steps of:
Step 1: the substrate material of selection n-type doping；The substrate is carried out back thinning；
It injects to form the first N-type field stop layer Step 2: carrying out first time N-type heavy doping ion to the back side of the substrate；
Step 3: carrying out thermal annealing to the first N-type field stop layer；
Step 4: completing the front description technique of IGBT, the p-well of the front description technique and described the in the substrate face
The substrate is as N-type drift region between one N-type field stop layer；
Step 5: carrying out wet etching to the substrate back for completing the front description technique, which will be described
The back side of first N-type field stop layer removes certain thickness；
It injects to form the second N-type field stop layer, institute Step 6: carrying out second of N-type heavy doping ion to the back side of the substrate
The junction depth for stating the second N-type field stop layer is shallower than the junction depth of the first N-type field stop layer, by the first N-type field stop layer and
The field stop layer of the second N-type field stop layer composition IGBT, the field is improved by the first N-type field stop layer and is terminated
The thickness of layer is eliminated by the second N-type field stop layer and described is introduced into the substrate back in front of the graphic process
Influence of the impurity in face to the p-type implanted layer being subsequently formed；
It injects to form the p-type implanted layer Step 7: carrying out p-type heavy doping ion to the back side of the substrate, the p-type injection
Layer is located on the back of the second N-type field stop and is made of the p-type implanted layer the collecting zone of IGBT；
Step 8: carrying out laser annealing activation to the second N-type field stop layer and the p-type implanted layer；
Step 9: forming metal layer on back at the back side of the substrate.
2. the method as described in claim 1, it is characterised in that: the note of the injection of first time N-type heavy doping ion described in step 2
Entering dosage is 2E13cm-2~3E13cm-2, Implantation Energy 1.5MeV.
3. method according to claim 1 or 2, it is characterised in that: moved back in step 3 to the heat of the first N-type field stop layer
The temperature of fire is 1200 DEG C, and the time is 1200 minutes.
4. the method as described in claim 1, it is characterised in that: wet etching described in step 5 is whole by first N-type field
Only layer the back side removal with a thickness of 3 microns~5 microns.
5. the method as described in claim 1, it is characterised in that: the note of the injection of second of N-type heavy doping ion described in step 6
Entering dosage is 1E12cm-2~3E12cm-2, Implantation Energy 450KeV.
6. the method as described in claim 1, it is characterised in that: the p-type heavy doping of p-type implanted layer described in step 7 from
The implantation dosage of son injection is 1E13cm-2~2E13cm-2, Implantation Energy 40KeV.
7. the method as described in claim 1, it is characterised in that: the laser irradiation amount of laser annealing described in step 8 is 2.5J/
cm2。
8. the method as described in claim 1, it is characterised in that: the N-type drift region thickness is by the thinning back side in step 1
Technique determines that the operating voltage of IGBT is higher, and the thickness of the N-type drift region is bigger, doping concentration is smaller.
9. the method as described in claim 1, it is characterised in that: the front description technique includes cellular region and pressure resistance protection
Area.
10. method as claimed in claim 9, it is characterised in that: the cellular region is formed with the cellular construction of IGBT, described
The cellular construction of IGBT includes:
Polysilicon gate, isolation has gate oxide between the polysilicon gate and the p-well；
Emitter region, the N-type heavily doped region by being formed in the p-well surface form, the p-well table covered by the polysilicon gate
Face is used to form the channel for connecting the emitter region and the N-type drift region；
P-well draw-out area, is made of p-type heavily doped region；The p-well draw-out area passes through the emitter region and enters in the p-well, institute
P-well draw-out area is stated to contact with the emitter region and the p-well simultaneously；
Front metal layer, grid and emitter are made of front metal layer respectively, and grid passes through contact hole and the polysilicon gate
Contact, emitter are contacted by contact hole and the p-well draw-out area.
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| CN109994544B (en) * | 2018-01-03 | 2022-05-27 | 宁波达新半导体有限公司 | Method for manufacturing field stop type power device |
| CN117012641A (en) * | 2023-07-21 | 2023-11-07 | 上海华虹挚芯电子科技有限公司 | IGBT device manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102800591A (en) * | 2012-08-31 | 2012-11-28 | 电子科技大学 | Preparation method for FS-IGBT device |
| CN103578959A (en) * | 2013-11-19 | 2014-02-12 | 电子科技大学 | Manufacturing method of anode of FS-IGBT device |
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| US7538412B2 (en) * | 2006-06-30 | 2009-05-26 | Infineon Technologies Austria Ag | Semiconductor device with a field stop zone |
| US7989888B2 (en) * | 2006-08-31 | 2011-08-02 | Infineon Technologies Autria AG | Semiconductor device with a field stop zone and process of producing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102800591A (en) * | 2012-08-31 | 2012-11-28 | 电子科技大学 | Preparation method for FS-IGBT device |
| CN103578959A (en) * | 2013-11-19 | 2014-02-12 | 电子科技大学 | Manufacturing method of anode of FS-IGBT device |
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