CN117012641A - IGBT device manufacturing method - Google Patents
IGBT device manufacturing method Download PDFInfo
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- CN117012641A CN117012641A CN202310904466.3A CN202310904466A CN117012641A CN 117012641 A CN117012641 A CN 117012641A CN 202310904466 A CN202310904466 A CN 202310904466A CN 117012641 A CN117012641 A CN 117012641A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 239000010410 layer Substances 0.000 claims abstract description 116
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 49
- 239000011574 phosphorus Substances 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 43
- -1 phosphorus ions Chemical class 0.000 claims abstract description 42
- 238000002513 implantation Methods 0.000 claims abstract description 41
- 238000005468 ion implantation Methods 0.000 claims abstract description 39
- 230000008569 process Effects 0.000 claims abstract description 37
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 31
- 239000001257 hydrogen Substances 0.000 claims abstract description 31
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052796 boron Inorganic materials 0.000 claims abstract description 22
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000000137 annealing Methods 0.000 claims abstract description 11
- 238000005224 laser annealing Methods 0.000 claims abstract description 11
- 239000002344 surface layer Substances 0.000 claims abstract description 6
- 238000002347 injection Methods 0.000 claims description 28
- 239000007924 injection Substances 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 8
- 238000001465 metallisation Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 3
- 210000000746 body region Anatomy 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 20
- 239000007943 implant Substances 0.000 description 10
- 230000005684 electric field Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 230000004913 activation Effects 0.000 description 3
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- 239000000243 solution Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3245—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering of AIIIBV compounds
Abstract
The application discloses a manufacturing method of an IGBT device, which comprises the following steps: providing a semiconductor substrate, and manufacturing a DMOS structure on the front surface of the semiconductor substrate; carrying out a back thinning process on the back of the semiconductor substrate, and then carrying out a phosphorus ion implantation process on the back twice; carrying out a first boron ion implantation process on the back surface of the semiconductor substrate; performing an annealing process on the back surface after the implantation is completed; carrying out hydrogen ion implantation process on the back surface twice more; a back metal layer is formed. The application optimizes the back surface field termination layer, wherein the field termination layer of the back surface layer formed by phosphorus ions is formed in advance after phosphorus ion implantation and laser annealing. The field termination layer of the back lining layer formed by the hydrogen ions can adjust the emission efficiency of the back emission junction by adjusting the implantation energy of the hydrogen ions, wherein the maximum peak concentration of the field termination layer is smaller than or equal to the maximum peak depth of the field termination layer of the phosphorus ions, and meanwhile, the single-chip implantation time is shorter.
Description
Technical Field
The application relates to the technical field of semiconductor device manufacturing, in particular to a manufacturing method of an IGBT device, which forms a back surface field stop layer by adopting two different kinds of ions, namely hydrogen ions and phosphorus ions.
Background
In the technical field of semiconductor device manufacturing, a back surface field termination layer of an IGBT device is one of key structural layers affecting product performance. The concentration profile and thickness thereof influence the design of the compromise of saturation voltage drop Vcesat, turn-off energy consumption Eoff and collector emitter breakdown voltage BVCES of the IGBT product. Therefore, optimizing the concentration profile and thickness of the back surface field stop layer is one of the key factors for optimizing product performance and reducing manufacturing costs.
The back surface field stop layer technology mainly comprises a phosphorus ion doping technology, a phosphorus ion implantation doping technology, a hydrogen ion implantation doping technology and the like by adopting an epitaxial layer. The IGBT with the field stop layer by the epitaxial layer doping phosphorus ion technology is manufactured by processing an epitaxial wafer. The IGBT using phosphorus ion and hydrogen ion implantation doping technology as the field stop layer generally adopts a single wafer substrate.
The epitaxial layer doped with phosphorus ions is used as a back surface field stop layer, and the cost is high, in particular to a high-voltage IGBT with the voltage of more than 1200V. The epitaxial price is higher due to the thick epitaxial thickness. As shown in fig. 1, in which the region 15 is an epitaxially formed high-resistance drift region, the region 16 is a field stop layer formed by epitaxy, and the DMOS structure composed of the regions 1 to 7 of the front surface is formed on the epitaxial layer.
The back surface field stop layer formed by the phosphorus ion back surface injection technology is relatively thin due to the relatively large mass of phosphorus ions, the thickness of the stop layer is generally 1-3 um, and the field stop effect is not ideal, as shown in fig. 2. Where region 2 is the high resistance drift region and region 9 is the field stop layer formed by phosphorus implantation.
The implantation depth of hydrogen ions in silicon can be made deeper due to the lighter weight, and a good back surface field stop layer can be formed. But high energy hydrogen ion implantation is due to the use of specialized hydrogen ion implantation equipment. To form a good back surface field stop layer, multiple high energy hydrogen ion implants are generally required, with higher implant dose requirements closer to the back surface, and relatively low efficiency of hydrogen ion activation as a donor. The high energy hydrogen implant costs are also relatively high, as shown in fig. 3, where region 2 is the high resistance drift region and region 8 is the field stop layer formed by the hydrogen implant.
In the prior art, a process method for forming a back buffer layer by hydrogen injection is adopted, wherein the energy of the hydrogen injection is 100-500 keV, and the dosage is 1E12cm -2 ～1E16cm -2 . The hydrogen injection dosage is up to 1E16cm -2 . The productivity utilization rate of the injection equipment is low and the cost is high. Or the back surface phosphorus implantation and the hydrogen implantation are adopted, but the energy range adopted by the hydrogen implantation is 400 keV-1.5 MeV, and the dosage range is 5E11cm -2 ～5E14cm -2 . The hydrogen injection energy is relatively high, the injection depth is relatively deep, and high-energy hydrogen injection equipment is needed.
Disclosure of Invention
The application mainly solves the technical problems of poor effect of back surface field termination or high manufacturing cost of a semiconductor device in the prior art.
In order to solve the technical problems, the application simplifies the manufacturing process of the semiconductor device and reduces the manufacturing cost while ensuring the termination effect of the field termination layer on the electric field, and provides a manufacturing method of the IGBT device, which comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a front surface and a back surface opposite to the front surface;
manufacturing a DMOS structure on the front surface of the semiconductor substrate;
carrying out a back thinning process on the back of the semiconductor substrate, and then carrying out a first and a second phosphorus ion implantation processes on the back;
carrying out a first boron ion implantation process on the back surface of the semiconductor substrate;
performing an annealing process on the back surface after the implantation is completed;
carrying out a first and a second hydrogen ion implantation processes on the back surface;
performing a heat treatment process on the semiconductor substrate;
a back metal layer is formed.
Further, the semiconductor substrate comprises a silicon substrate, a germanium-silicon substrate, a gallium arsenide substrate, a gallium nitride substrate and a silicon carbide substrate.
Further, the manufacturing process of the front-side DMOS structure includes:
firstly, growing a first oxide layer on the surface of a semiconductor substrate, and forming P-Ring on a chip terminal area on the semiconductor substrate after one-time photoetching, selective etching, boron injection and high-temperature junction pushing;
etching the source region of the chip through the second photoetching, so that the source region except the P-Ring region is free of the oxide layer; depositing a second oxide layer on the semiconductor substrate as a hard mask layer for the subsequent trench etching;
selectively exposing and etching the hard mask layer on the hard mask layer, then etching the semiconductor substrate to form a deep trench, and then removing the second oxide layer;
growing a gate oxide layer, wherein the gate oxide layer is attached to the inner wall of the deep trench, and then performing polysilicon deposition and polysilicon annealing to enable the deep trench to be filled with polysilicon to form a trench gate;
after the trench gate is formed, performing boron ion implantation and boron ion junction pushing to form a P-type body region, forming a source region through selective photoetching and arsenic ion implantation, and then performing TEOS+BPSG deposition; and finally, forming a front metal layer after front metal deposition and metal photoetching, and completing the front DMOS structure.
Further, the backside thinning process, wherein the thinned thickness is related to the required operating voltage level thereof; the higher the operating voltage, the thicker the thickness of the semiconductor substrate remaining after the backside thinning process.
Further, the first and second phosphorus ion implantation processes have the implantation energy of 300-600 keV and the implantation dosage of 5E11cm -2 ～3E12cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The implantation energy of the second phosphorus ion implantation is 100-220 keV, and the implantation dosage is 3E12cm -2 ～1E13cm -2 。
Further, the implantation energy of the first boron ion implantation process is 10-50 keV, and the boron implantation dosage is 5E12cm -2 ～1E14cm -2 。
Further, the annealing process is laser annealing, and the laser energy is 1.0-3.0 mJ/cm 2 After the annealing is completed, a field stop layer formed by phosphorus ions and a back collector region formed by boron ions are formed on the shallow back surface layer.
Further, the first and second hydrogen ion implantation processes have the implantation energy of 300-400 keV and the implantation dosage of 1E12cm -2 ～1E13cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The implantation energy of the second hydrogen ion implantation is 250-350keV, and the implantation dosage is 2E13cm -2 ～5E13cm -2 。
Further, the heat treatment process is to perform heat treatment for 30-60 min under the nitrogen atmosphere condition of 300-450 ℃ to form a field termination layer of the back lining layer formed by hydrogen ions after the completion of the heat treatment.
Further, the back metal layer is subjected to back metallization by a sputtering method; sequentially forming Al-Ti-Ni-Ag on the back surface; wherein the thickness of Al isTi thickness of +.>Ni layer thickness +.>The thickness of the Ag layer is
The application optimizes the back surface electric field termination layer formed by two N-type impurities of hydrogen and phosphorus, and adjusts the injection parameters of the back surface electric field termination layer, wherein the field termination layer formed by phosphorus ions is formed in advance after phosphorus ion injection and laser annealing. The field stop layer of the back lining layer formed by hydrogen ions is positioned at the position of 2-4 um on the inner side of the field stop layer formed by the phosphorus ions by adjusting the implantation energy of the hydrogen ions, and the maximum peak value concentration of the field stop layer is smaller than or equal to the maximum peak value depth of the field stop layer formed by the phosphorus ions. The electric field termination layer of the back surface layer is formed by phosphorus injection, and the injected phosphorus ions are activated by laser annealing, so that the activation rate of the injected phosphorus ions can be more than 80% by adjusting the laser power during the laser annealing, the concentration of the N-type termination layer is high enough, and the effect of adjusting the emission efficiency of the back emission junction can be well achieved. The dose of phosphorus implant is an order of magnitude smaller than with hydrogen implant, so the monolithic implant time is much shorter.
Drawings
Fig. 1 is a schematic cross-sectional view of a prior art epitaxial layer using phosphorus doping as a back surface field stop layer, wherein the epitaxial layer has a larger thickness.
Fig. 2 is a schematic cross-sectional view of a prior art process for forming a back surface field stop layer by a phosphorus ion back side implantation process, wherein the back surface field stop layer is formed thinner.
Fig. 3 is a schematic cross-sectional view of a prior art hydrogen ion implantation to form a back surface field stop layer.
Fig. 4 is a cross-sectional configuration diagram of an IGBT according to the present application.
Fig. 5 is a process step flow diagram of a method of fabricating an IGBT device of the application.
Description of the reference numerals
1 is front metal, 2 is drift region, 3 is body region, 4 is polysilicon gate, 5 is gate dielectric layer, 6 is TEOS+BPSG,7 is source region, 8 is inner field stop layer (hydrogen ion implantation), 9 is shallow surface field stop layer (phosphorus ion implantation), 10 is collector region, 11-14 is Al-Ti-Ni-Ag metal layer.
Detailed Description
The following description of the embodiments of the present application will be given with reference to the accompanying drawings, in which the technical solutions of the present application are clearly and completely described, but the present application is not limited to the following embodiments. It will be apparent that the described embodiments are some, but not all, embodiments of the application. Advantages and features of the application will become more apparent from the following description and from the claims. It is noted that the drawings are in a very simplified form and use non-precise ratios for convenience and clarity in assisting in illustrating embodiments of the application. All other embodiments obtained by those skilled in the art without making any inventive effort are within the scope of the present application.
This application may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for the same elements throughout. In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Referring to fig. 4, the IGBT structure diagram of the present application is that the dimensions do not form a proportional relationship, and there is no correspondence with the actual product dimensions. In the figures, region 2, region 3, region 7, region 8, region 9, region 10 are N-type silicon or P-type silicon (corresponding to different types of IGBT), region 1 is a front metal layer, region 4 is a trench type polysilicon gate, and region 5 is a gate dielectric layer (SiO) 2 ) Region 6 is a gate-source isolation layer (SiO 2 +bpsg), regions 11, 12, 13, 14 are back side metal layers comprising different metals. Wherein regions 1 to 7 constitute the aforementioned front-side DMOS structure, regions 8, 9, 10 are back-side field stop layers and back-side collector regions. These regions are described belowDomain formation process and method.
The application is realized by forming a DMOS structure on the front surface of a monocrystalline silicon wafer, wherein the DMOS structure can be a planar DMOS or a trench DMOS, and the manufacturing methods of the two DMOS structures are well known to the related technical personnel. After the front-side DMOS structure is formed, a desired silicon wafer thickness is obtained by thinning the back side, and then a back side process is performed.
Taking a certain product as an example, the following is introduced briefly:
firstly, performing thermal oxidation at 1100 ℃ to grow an oxide layer with the thickness of 1.3um, and forming a P-Ring field stop Ring in a chip terminal area after one-time photoetching and selective etching, boron injection and high-temperature junction pushing. The source region of the chip is etched by the second photoetching to make the source region except the P-Ring region have no SiO 2 . By depositing SiO of 0.5um thickness on the wafer 2 As a hard mask layer for the subsequent gate trench etch. Selective exposure and etching of SiO on the hard mask layer 2 Etching substrate silicon, forming a trench with a depth of 5um in the substrate, removing a sacrificial oxide layer, growing a gate oxide layer, forming a region 5 in fig. 4, depositing polysilicon and annealing the polysilicon, and forming a region 4 in fig. 4 after the polysilicon etching. Region 3 in fig. 4 is formed after the formation of the polysilicon gate by boron ion implantation and boron ion push junction, region 7 (n+ source region of IGBT) is formed after selective lithography and arsenic ion implantation, and region layer 6 is formed by post-teos+bpsg deposition followed by lead hole lithography. Finally, front metal deposition and metal lithography are carried out to form a front metal layer (region 1 in the figure). The fabrication of the front-side DMOS structure is thus completed.
The back surface field stop layer and the back surface collector region are obtained by the method that firstly, after the front surface DMOS structure is manufactured, a back surface thinning process of a wafer is carried out, and the wafer is thinned to a required thickness. The wafer thickness targets for different voltage levels are different, e.g., the thickness target for a silicon substrate after IGBT thinning of 1200V is 115um, while for an IGBT thinning of 750V the silicon substrateThe thickness of (2) is 75um, that is, the thickness of the thinned silicon substrate is thicker as the operating voltage is higher. After the thinning is finished, phosphorus injection with different energy and dosages is sequentially carried out on the back surface, the injection energy of the first time and the second time is 450keV and 200keV in sequence, and the corresponding injection dosages are 1E12cm in sequence -2 、3E12cm -2 . After the phosphorus implantation is completed, the back surface boron implantation is carried out, the energy of the boron implantation is 40keV, and the dosage of the boron implantation is 5E13cm -2 . After the implantation is completed, the laser annealing is carried out, and the laser energy is 1.8mJ/cm 2 A field stop layer (region 9 in fig. 4) formed of phosphorus ions and a back surface collector region (region 10 in fig. 4) formed of boron ions are formed on the back surface shallow layer.
After the laser annealing, carrying out two more hydrogen injections on the back of the wafer, wherein the injection energy of the first hydrogen injection and the second hydrogen injection is 400keV and 300keV in sequence, and the injection dosage is 0.5E13cm in sequence -2 、2.5E13cm -2 . Then, the heat treatment was performed under nitrogen atmosphere at 410℃for 30 minutes. This completes the fabrication of the field stop layer (region 8 in fig. 4) of the backside lining formed of hydrogen ions. Finally, forming back metal, carrying out back metallization by a sputtering method, and sequentially forming Al-Ti-Ni-Ag on the back, wherein the Al-Ti-Ni-Ag sequentially corresponds to reference numerals 11-14 in fig. 4. Wherein the thickness of the Al layer 11 isThe thickness of the Ti layer 12 is +.>The thickness of the Ni layer 13 is +.>The thickness of the Ag layer 14 is +.>
The method of the application has the main advantages that:
1. the application optimizes the back surface electric field termination layer formed by two N-type impurities of hydrogen and phosphorus, wherein the field termination layer 9 of the back surface layer formed by phosphorus ions is formed in advance after phosphorus ion implantation and laser annealing. The field stop layer 8 of the back inner layer formed by hydrogen ions is positioned at the position of 2-4 um on the inner side of the field stop layer formed by the phosphorus ions by designing the implantation energy of the hydrogen ions, and the maximum peak value concentration is smaller than or equal to the maximum peak value depth of the field stop layer formed by the phosphorus ions.
2. The electric field stop layer 9 of the back surface layer of the present application is formed by phosphorus implantation. The implanted phosphorus ions are activated by laser annealing, and the activation rate of the implanted phosphorus ions can be 80% or more by adjusting the laser power during the laser annealing. Thus the dosage of the phosphorus ion implantation is 1E11cm -2 ～5E12cm -2 The concentration of the N-type termination layer is high enough, and the effect of adjusting the emission efficiency of the back emission junction can be well achieved. The dose of phosphorus implant is an order of magnitude smaller than with hydrogen implant, so the monolithic implant time is much shorter.
3. The electric field termination layer of the back lining layer is an N-type buffer layer with the depth of 4-6 um, and is formed by hydrogen ion implantation and furnace tube or oven annealing, wherein the hydrogen ion implantation adopts relatively low energy, the energy range is 200-400 keV, and the implantation dosage is 5E13cm -2 ～1E11cm -2 Between, 1 or two hydrogen injections may be performed, with the injection energy increasing in sequence and the dose decreasing in sequence if the two injections are performed. After hydrogen implantation, an anneal is performed to obtain an optimized N-type concentration profile field stop layer. The annealing temperature and time are 300-450 ℃ and 30-60 minutes. The electric field termination layer can well compromise the BVCES parameters and switching characteristics on the inner side formed by the phosphorus ions. Meanwhile, as the maximum injection dosage of hydrogen is smaller, a large amount of injection time can be saved, the productivity of hydrogen injection equipment in unit time is increased, and the production period and the production cost are shortened.
The above are only preferred embodiments of the present application, and are not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. The IGBT device manufacturing method is characterized in that:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a front surface and a back surface opposite to the front surface;
manufacturing a DMOS structure on the front surface of the semiconductor substrate;
carrying out a back thinning process on the back of the semiconductor substrate;
performing a first and a second phosphorus ion implantation process on the back surface;
carrying out a first boron ion implantation process on the back surface of the semiconductor substrate;
performing an annealing process on the back surface after the implantation is completed;
carrying out a first and a second hydrogen ion implantation processes on the back surface;
performing a heat treatment process on the semiconductor substrate;
a back metal layer is formed.
2. The IGBT device manufacturing method of claim 1, wherein: the semiconductor substrate comprises a silicon substrate, a germanium-silicon substrate, a gallium arsenide substrate, a gallium nitride substrate and a silicon carbide substrate.
3. The IGBT device manufacturing method of claim 1, wherein: the front-side DMOS structure is a planar DMOS or a trench DMOS, and the manufacturing process comprises the following steps:
firstly, growing a first oxide layer on the surface of a semiconductor substrate, and forming P-Ring on a chip terminal area on the semiconductor substrate after one-time photoetching, selective etching, boron injection and high-temperature junction pushing;
etching the source region of the chip through the second photoetching, so that the source region except the P-Ring region is free of the oxide layer; depositing a second oxide layer on the semiconductor substrate as a hard mask layer for the subsequent trench etching;
selectively exposing and etching the hard mask layer on the hard mask layer, then etching the semiconductor substrate to form a deep trench, and then removing the second oxide layer;
growing a gate oxide layer, wherein the gate oxide layer is attached to the inner wall of the deep trench, and then performing polysilicon deposition and polysilicon annealing to enable the deep trench to be filled with polysilicon to form a trench gate;
after the trench gate is formed, performing boron ion implantation and boron ion junction pushing to form a P-type body region, forming a source region through selective photoetching and arsenic ion implantation, and then performing TEOS+BPSG deposition; and finally, forming a front metal layer after front metal deposition and metal photoetching, and completing the front DMOS structure.
4. The IGBT device manufacturing method of claim 1, wherein: the back thinning process, wherein the thickness after thinning is related to the required working voltage level; the higher the operating voltage, the thicker the thickness of the semiconductor substrate remaining after the backside thinning process.
5. The IGBT device manufacturing method of claim 1, wherein: the first and second phosphorus ion implantation processes, the implantation energy of the first phosphorus ion implantation is 300-660 keV, and the implantation dosage is 5E11cm -2 ～3E12cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The implantation energy of the second phosphorus ion implantation is 100-220 keV, and the implantation dosage is 3E12cm -2 ～1E13cm -2 。
6. The IGBT device manufacturing method of claim 1, wherein: the implantation energy of the first boron ion implantation process is 10-50 keV, and the boron implantation dosage is 5E12cm -2 ～1E14cm -2 。
7. The IGBT device manufacturing method of claim 1, wherein: the annealing process is laser annealing, and the laser energy is 1.0-3.0 mJ/cm 2 Formed into a back shallow surface layer by phosphorus ion after annealingA field stop layer and a back surface collector region formed of boron ions.
8. The IGBT device manufacturing method of claim 1, wherein: the first and second hydrogen ion implantation processes have the implantation energy of 300-400 keV and the implantation dosage of 1E12cm -2 ～1E13cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The implantation energy of the second hydrogen ion implantation is 250-350keV, and the implantation dosage is 2E13cm -2 ～5E13cm -2 。
9. The IGBT device manufacturing method of claim 1, wherein: the heat treatment process is that the heat treatment is carried out for 30-60 min under the nitrogen atmosphere condition of 300-450 ℃ and then the field termination layer of the back lining layer formed by hydrogen ions is formed.
10. The IGBT device manufacturing method of claim 1, wherein: the back metal layer is subjected to back metallization by a sputtering method; sequentially forming Al-Ti-Ni-Ag on the back surface; wherein the Al has a thickness of 1000A, the Ti has a thickness of 1000A, the Ni layer has a thickness of 2000A, and the Ag layer has a thickness of 8000A.
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| CN104576367A (en) * | 2014-06-30 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Method for improving negative resistance problem of IGBT (Insulated Gate Bipolar Transistor) |
| CN104637994A (en) * | 2013-11-13 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and manufacturing method |
| CN113206013A (en) * | 2021-04-27 | 2021-08-03 | 上海积塔半导体有限公司 | IGBT device with back buffer layer structure and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104637994A (en) * | 2013-11-13 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and manufacturing method |
| CN104576367A (en) * | 2014-06-30 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Method for improving negative resistance problem of IGBT (Insulated Gate Bipolar Transistor) |
| CN113206013A (en) * | 2021-04-27 | 2021-08-03 | 上海积塔半导体有限公司 | IGBT device with back buffer layer structure and preparation method thereof |
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