CN106200167A - Array base palte and liquid crystal display - Google Patents
Array base palte and liquid crystal display Download PDFInfo
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- CN106200167A CN106200167A CN201610729146.9A CN201610729146A CN106200167A CN 106200167 A CN106200167 A CN 106200167A CN 201610729146 A CN201610729146 A CN 201610729146A CN 106200167 A CN106200167 A CN 106200167A
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Abstract
The open a kind of array base palte of the present invention and liquid crystal display.It is formed with gate driver circuit on this array base palte, gate driver circuit includes grid layer, source/drain layer and the first insulating barrier between grid layer and source/drain layer, and grid layer is least partially overlapped with source/drain layer to form the first electric capacity needed for gate driver circuit.The present invention can increase the electric capacity of GOA on the whole, reduces the area shared by electric capacity, the narrow frame of beneficially LCD and high PPI design.
Description
Technical field
The present invention relates to technical field of liquid crystal display, in particular to a kind of array base palte and include this array base palte
Liquid crystal display.
Background technology
LCD (Liquid Crystal Display, liquid crystal display), due to advantages such as its lightening and low-power consumption, is mesh
Main flow display device in front market.Raising along with the PPI (Pixels Per Inch, number of pixels or picture element density) of LCD
And the industry demand of narrow frame, the progression of GOA (Gate Driver On Array, array base palte row cutting) is gradually increased,
The width causing GOA becomes narrow gradually, and this can make the TFT (Thin Film Transistor, thin film transistor (TFT)) in GOA undoubtedly
And the arrangement of electric capacity is more difficult.Further, along with the width of GOA diminishes, the area shared by its electric capacity is less, so that electric
Container has bigger capacity (Holding) with more stable work, and the capacitance of GOA is accomplished by promoting.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of array base palte and liquid crystal display, it is possible to increase the electric capacity of GOA,
Reduce the area shared by electric capacity, the narrow frame of beneficially LCD and high PPI design.
A kind of array base palte that the embodiment of the present invention provides, it is formed gate driver circuit, gate driver circuit bag
Include grid layer, source/drain layer and the first insulating barrier between grid layer and source/drain layer, wherein grid layer with
Source/drain layer is least partially overlapped, and then is formed the first electricity needed for gate driver circuit by grid layer and source/drain layer
Hold.
Wherein, gate driver circuit farther include to be positioned at grid layer away from source/drain layer side channel layer with
And the second insulating barrier between grid layer and channel layer, wherein channel layer is least partially overlapped with grid layer, and with source electrode/
Drain electrode layer electrically connects, and then is formed the second electric capacity with the first capacitances in series by grid layer and channel layer.
Wherein, the first insulating barrier and the second insulating barrier are provided with through hole spaced with grid layer, source/drain layer
Electrically connect with channel layer via through hole.
Wherein, gate driver circuit farther include to be positioned at the light shield layer away from grid layer side of channel layer and between
The 3rd insulating barrier between channel layer and light shield layer, wherein light shield layer and the least partially overlapped setting of channel layer, and and grid layer
Electrical connection, and then formed and the first electric capacity and the 3rd electric capacity of the second capacitances in series by channel layer and light shield layer.
Wherein, the second insulating barrier and the 3rd insulating barrier are provided with through hole spaced with channel layer, grid layer via
Through hole electrically connects with light shield layer.
Wherein, gate driver circuit farther includes to be positioned at the touch-control cabling away from grid layer side of source/drain layer
Layer and the 4th insulating barrier between source/drain layer and touch-control routing layer, wherein touch-control routing layer and source/drain layer
Least partially overlapped setting, and electrically connect with grid layer, and then formed and the first electricity by source/drain layer and touch-control routing layer
Appearance, the second electric capacity, the 4th electric capacity of the 3rd capacitances in series.
Wherein, the first insulating barrier and the 4th insulating barrier are provided with through hole spaced with source/drain layer, grid layer
Electrically connect with touch-control routing layer via through hole.
Wherein, grid layer, source/drain layer, light shield layer and touch-control routing layer are metal level, and channel layer is polysilicon
Layer.
A kind of liquid crystal display that the embodiment of the present invention provides, including above-mentioned array base palte.
The another kind of array base palte that the embodiment of the present invention provides, it is formed gate driver circuit, gate driver circuit
The multiple conductive layers arranged including stacking and the insulating barrier between adjacent conductive layer, plurality of conductive layer is for choosing freely
At least three in the group that grid layer, source/drain layer, light shield layer, channel layer and touch-control routing layer are formed, multiple leads
Electric layer is electrically connected and is connected at least two electric capacity being one another in series.
Beneficial effect: the embodiment of the present invention is driven by the least partially overlapped formation grid of grid layer with source/drain layer
An electric capacity needed for galvanic electricity road, the electric capacity liquid crystal provided along that this electric capacity overlaps to form with public electrode and pixel electrode insulation rings
Electricity needed for should such that it is able to increase the electric capacity of GOA, reduces the area shared by electric capacity, the narrow frame of beneficially LCD and height
PPI designs.
Accompanying drawing explanation
Fig. 1 is the structure sectional view of the display panels of one embodiment of the invention；
Fig. 2 is the dot structure schematic diagram of the embodiment of display panels one shown in Fig. 1；
Fig. 3 is the equivalent circuit diagram of the dot structure shown in Fig. 2；
Fig. 4 is the structure sectional view of the array base palte of first embodiment of the invention；
Fig. 5 is the structure sectional view of the array base palte of second embodiment of the invention；
Fig. 6 is the structure sectional view of the array base palte of third embodiment of the invention；
Fig. 7 is the structure sectional view of the array base palte of fourth embodiment of the invention；
Fig. 8 is the structure sectional view of the liquid crystal display of one embodiment of the invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the skill to each exemplary embodiment provided by the present invention
Art scheme is clearly and completely described.In the case of not conflicting, the feature in each embodiment following and embodiment can
To be mutually combined.
Fig. 1 is the structure sectional view of the display panels of one embodiment of the invention.As it is shown in figure 1, the liquid of the present embodiment
LCD panel 10 include color membrane substrates that relative spacing arranges (Color Filter Substrate, is called for short CF substrate, also known as
Colored filter substrate) 11 and array base palte (Thin Film Transistor Substrate, be called for short TFT substrate, also known as thin
Film transistor substrate or Array substrate) 12 and the liquid crystal (liquid crystal molecule) 13 that is filled between two substrates, this liquid crystal 13 is positioned at
In the liquid crystal cell that array base palte 12 and color membrane substrates 11 superposition are formed.
In conjunction with the dot structure schematic diagram of display panels 10 shown in Fig. 2, array base palte 12 includes arranging along column direction
A plurality of data lines D, the multi-strip scanning line G arranged in the row direction and the multiple pixel regions defined by scan line G and data wire D
Territory P.Wherein, each pixel region P connects a corresponding data line D and scan line G, and each bar scan line G is connected to grid
Pole drive circuit 21 is to provide scanning voltage to each pixel region P, and pieces of data line D is connected to source electrode drive circuit 22 with to respectively
Pixel region P provides gray scale voltage.Further combined with the equivalent circuit diagram of the dot structure shown in Fig. 3, gate driver circuit 21
Including TFT 14, storage electric capacity CstAnd liquid crystal capacitance Clc, liquid crystal capacitance ClcBy being positioned at the pixel electrode of pixel region P, color film
The public electrode of substrate 11 side and be positioned at liquid crystal 13 between the two and formed.
According to the displaying principle of display panels 10, by inputting scanning voltage for scan line G, it is positioned at same a line
TFT 14 is simultaneously open, and the TFT 14 being positioned at next line after a certain time is simultaneously open, the like.Due to each
The time that row TFT 14 opens is comparatively short, liquid crystal capacitance ClcThe time that charging controls liquid crystal 13 deflection is shorter, is extremely difficult to liquid crystal
The response time of 13, stores electric capacity CstJust can maintain the voltage of each pixel region P after TFT 14 closes, thus be liquid crystal
13 response offer times.
In the prior art, storage electric capacity CstPublic electrode and pixel electrode for array base palte 12 side are by being held on
The storage electric capacity that passivation layer between the two is formed.Being different from prior art, the embodiment of the present invention is at this storage electric capacity CstBase
Electric capacity is increased on plinth.
Refering to Fig. 4, for the structure sectional view of the array base palte of first embodiment of the invention.Described gate driver circuit 21 wraps
Include substrate 120 and each Rotating fields being sequentially formed in substrate 120: the first metal layer Ml, the first insulating barrier
121, the second metal level M2.Wherein, the first insulating barrier 121 is buffer layer (the Interlayer dielectric of TFT 14
Isolation, is called for short ILD), the first metal layer MlFor the grid layer of TFT 14, the second metal level M2For TFT 14 source layer or
Drain electrode layer.For ease of describing, the embodiment of the present invention is all with the second metal level M2For being described as a example by source layer, certainly, second
Metal level M2All embodiments of the present invention can also be realized for drain electrode layer.
In the present embodiment, grid layer MlWith source layer M2Least partially overlapped, the grid layer M of laplWith source layer
M2Arranged by the first insulating barrier 121 insulation being held between the two, to form the first electric capacity Cst1.This newly increase first
Electric capacity Cst1With existing storage electric capacity CstLiquid crystal 13 provided along responds required electricity such that it is able to increase the electric capacity of GOA,
Reduce narrow frame and the high PPI design of the area shared by electric capacity, beneficially display panels 10.
Refering to Fig. 5, for the structure sectional view of the array base palte of second embodiment of the invention.For and embodiment illustrated in fig. 4
Identical structural detail, the present embodiment uses identical label.On the basis of the description of previous embodiment, the grid of the present embodiment
Drive circuit 21 farther includes to be positioned at grid layer MlAway from source layer M2The channel layer 122 of side and between grid layer Ml
And the second insulating barrier 123 between channel layer 122.Wherein, channel layer 122 is the polysilicon semiconductor of heavy doping N+ of TFT 14
(polycrystalline silicon, P-Si) layer, the second insulating barrier 123 is gate insulator (Gate Insulation
Layer,GI)。
In the present embodiment, the first insulating barrier 121 and the second insulating barrier 123 are provided with and grid layer MlSpaced
Through hole 124, source layer M2Electrically connect with channel layer 122 via through hole 124.Channel layer 122 and grid layer MlIt is least partially overlapped,
Channel layer 122 and the grid layer M of laplArranged by the second insulating barrier 123 insulation being held between the two, to be formed
Second electric capacity Cst2.Second electric capacity Cst2With the first electric capacity Cst1Series connection, the electric capacity (C=C after series connectionst1+Cst2) more than the first electricity
Hold Cst1Such that it is able on the basis of embodiment illustrated in fig. 4, increase the electric capacity of GOA.Further, the second electric capacity Cst2With the first electric capacity
Cst1Arranging for superposition, be compared to previous embodiment, the present embodiment also will not increase the area shared by electric capacity, beneficially liquid crystal
The narrow frame of display floater 10 and high PPI design.
Refering to Fig. 6, for the structure sectional view of the array base palte of third embodiment of the invention.For and embodiment illustrated in fig. 5
Identical structural detail, the present embodiment uses identical label.On the basis of the description of previous embodiment, the grid of the present embodiment
Drive circuit 21 farther include to be positioned at channel layer 122 away from grid layer MlThe light shield layer M of side0And between channel layer 122
With light shield layer M0Between the 3rd insulating barrier 125.
In the present embodiment, the second insulating barrier 123 and the 3rd insulating barrier 125 are also equipped with and channel layer 122 interval sets
The through hole 124 put, grid layer MlVia through hole 124 and light shield layer M0Electrical connection.Light shield layer M0At least partly weigh with channel layer 122
Folded setting, the light shield layer M of lap0Set by the 3rd insulating barrier 125 insulation being held between the two with channel layer 122
Put, to form the 3rd electric capacity Cst3.3rd electric capacity Cst3With the first electric capacity Cst1With the second electric capacity Cst2Series connection, the electric capacity after series connection
(C=Cst1+Cst2+Cst3) more than the first electric capacity Cst1Such that it is able on the basis of embodiment illustrated in fig. 4, increase GOA further
Electric capacity.Further, the 3rd electric capacity Cst3With the first electric capacity Cst1With the second electric capacity Cst2Arrange for superposition, be compared to aforementioned enforcement
Example, the present embodiment will not increase narrow frame and the high PPI design of the area shared by electric capacity, beneficially display panels 10.
Refering to Fig. 7, for the structure sectional view of the array base palte of third embodiment of the invention.For and embodiment illustrated in fig. 6
Identical structural detail, the present embodiment uses identical label.On the basis of the description of previous embodiment, the grid of the present embodiment
Drive circuit 21 farther includes to be positioned at source layer M2Away from grid layer M1The touch-control routing layer M of side3And between source layer
M2With touch-control routing layer M3Between the 4th insulating barrier 126.
In the present embodiment, the first insulating barrier 121 and the 4th insulating barrier 126 are also equipped with and source layer M2Interval is arranged
Through hole 124, grid layer M1Via through hole 124 and touch-control routing layer M3Electrical connection.Touch-control routing layer M3With source layer M2At least portion
Divide and overlap, the touch-control routing layer M of lap3With source layer M2Exhausted by the 4th insulating barrier 126 that is held between the two
Edge is arranged, to form the 4th electric capacity Cst4.4th electric capacity Cst4With the first electric capacity Cst1, the second electric capacity Cst2, the 3rd electric capacity Cst3String
Connection, the electric capacity (C=C after series connectionst1+Cst2+Cst3+Cst4) more than the first electric capacity Cst1Such that it is able in embodiment illustrated in fig. 4
On the basis of increase further the electric capacity of GOA.Further, the 4th electric capacity Cst4With the first electric capacity Cst1, the second electric capacity Cst2, the 3rd electricity
Hold Cst3Arranging for superposition, be compared to previous embodiment, the present embodiment also will not increase the area shared by electric capacity, beneficially liquid
The narrow frame of LCD panel 10 and high PPI design.
Above-mentioned Fig. 5～embodiment illustrated in fig. 6, can be considered that the gate driver circuit 21 of the embodiment of the present invention includes that stacking is arranged
Multiple conductive layers and insulating barrier between adjacent conductive layer, plurality of conductive layer is for selecting free grid layer M1, source
Pole layer (or drain electrode layer) M2, light shield layer M0, channel layer 122 and touch-control routing layer M3At least three in the group formed is many
Individual conductive layer is electrically connected and is connected at least two electric capacity being one another in series.
The embodiment of the present invention also provides for a kind of liquid crystal display 80 as shown in Figure 8, and this liquid crystal display 80 includes above-mentioned
The display panels 10 and light source module 81 of light is provided for display panels 10.Owing to this liquid crystal display 80 also has
There is the above-mentioned design of above-mentioned array base palte 12, the most also there is identical beneficial effect.
It is to be appreciated that the foregoing is only embodiments of the invention, not thereby limit the scope of the claims of the present invention, every
Utilizing equivalent structure or equivalence flow process conversion that description of the invention and accompanying drawing content made, between the most each embodiment, technology is special
That levies be combined with each other, or is directly or indirectly used in other relevant technical fields, and the patent being the most in like manner included in the present invention is protected
In the range of protecting.
Claims (10)
1. an array base palte, it is characterised in that be formed with gate driver circuit, described raster data model electricity on described array base palte
Road includes grid layer, source/drain layer and the first insulating barrier between described grid layer and described source/drain layer,
Wherein said grid layer is least partially overlapped with described source/drain layer, and then by described grid layer and described source/drain layer
Form the first electric capacity needed for described gate driver circuit.
Array base palte the most according to claim 1, it is characterised in that described gate driver circuit farther includes to be positioned at institute
State the channel layer away from described source/drain layer side of grid layer and between described grid layer and described channel layer
Second insulating barrier, wherein said channel layer is least partially overlapped with described grid layer, and electrically connects with described source/drain layer,
And then formed the second electric capacity with described first capacitances in series by described grid layer and described channel layer.
Array base palte the most according to claim 2, it is characterised in that on described first insulating barrier and described second insulating barrier
Being provided with through hole spaced with described grid layer, described source/drain layer is electrically connected with described channel layer via described through hole
Connect.
Array base palte the most according to claim 2, it is characterised in that described gate driver circuit farther includes to be positioned at institute
State the light shield layer away from described grid layer side of channel layer and the 3rd between described channel layer and described light shield layer
Insulating barrier, wherein said light shield layer and the least partially overlapped setting of described channel layer, and electrically connect with described grid layer, Jin Eryou
Described channel layer is formed and described first electric capacity and the 3rd electric capacity of described second capacitances in series with described light shield layer.
Array base palte the most according to claim 4, it is characterised in that on described second insulating barrier and described 3rd insulating barrier
Being provided with through hole spaced with described channel layer, described grid layer electrically connects with described light shield layer via described through hole.
Array base palte the most according to claim 4, it is characterised in that described gate driver circuit farther includes to be positioned at institute
State the touch-control routing layer away from described grid layer side of source/drain layer and touch with described between described source/drain layer
The 4th insulating barrier between control routing layer, wherein touch-control routing layer and the least partially overlapped setting of described source/drain layer, and with
Described grid layer electrically connects, and then is formed and described first electric capacity, described by described source/drain layer and described touch-control routing layer
Second electric capacity, the 4th electric capacity of described 3rd capacitances in series.
Array base palte the most according to claim 6, it is characterised in that on described first insulating barrier and described 4th insulating barrier
Being provided with through hole spaced with described source/drain layer, described grid layer is via described through hole and described touch-control routing layer
Electrical connection.
Array base palte the most according to claim 6, it is characterised in that described grid layer, described source/drain layer, described
Light shield layer and described touch-control routing layer are metal level, and described channel layer is polysilicon layer.
9. a liquid crystal display, it is characterised in that described liquid crystal display includes as described in claim 1-8 any one
Array base palte.
10. an array base palte, it is characterised in that be formed with gate driver circuit, described raster data model on described array base palte
Circuit includes multiple conductive layers that stacking arranges and the insulating barrier between adjacent conductive layer, wherein said multiple conductive layers
For choosing freely described grid layer, described source/drain layer, described light shield layer, described channel layer and described touch-control routing layer institute
At least three in the group of composition, the plurality of conductive layer is electrically connected and is connected at least two electric capacity being one another in series.
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| CN201610729146.9A CN106200167B (en) | 2016-08-25 | 2016-08-25 | Array substrate and liquid crystal display |
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| CN107219660A (en) * | 2017-07-12 | 2017-09-29 | 厦门天马微电子有限公司 | A kind of array base palte, display panel and display device |
| CN107527599A (en) * | 2017-08-16 | 2017-12-29 | 深圳市华星光电半导体显示技术有限公司 | Scan drive circuit, array base palte and display panel |
| CN108766382A (en) * | 2018-06-06 | 2018-11-06 | 深圳市华星光电半导体显示技术有限公司 | Bootstrap capacitor, GOA circuits and the display panel of GOA circuits |
| CN108761939A (en) * | 2018-05-28 | 2018-11-06 | 武汉华星光电技术有限公司 | Array substrate, display panel and display |
| CN108957884A (en) * | 2018-07-23 | 2018-12-07 | 深圳市华星光电技术有限公司 | array substrate, liquid crystal display panel and array substrate manufacturing method |
| WO2019119714A1 (en) * | 2017-12-22 | 2019-06-27 | 武汉华星光电技术有限公司 | Array substrate, liquid crystal panel, and liquid crystal display device |
| CN110568686A (en) * | 2019-08-08 | 2019-12-13 | 深圳市华星光电半导体显示技术有限公司 | array substrate and display panel |
| US10690978B2 (en) | 2018-05-28 | 2020-06-23 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Array substrate, display panel, and display |
| CN113363300A (en) * | 2021-06-01 | 2021-09-07 | 霸州市云谷电子科技有限公司 | Array substrate and display panel |
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| CN107219660A (en) * | 2017-07-12 | 2017-09-29 | 厦门天马微电子有限公司 | A kind of array base palte, display panel and display device |
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| CN108766382A (en) * | 2018-06-06 | 2018-11-06 | 深圳市华星光电半导体显示技术有限公司 | Bootstrap capacitor, GOA circuits and the display panel of GOA circuits |
| CN108957884A (en) * | 2018-07-23 | 2018-12-07 | 深圳市华星光电技术有限公司 | array substrate, liquid crystal display panel and array substrate manufacturing method |
| CN110568686A (en) * | 2019-08-08 | 2019-12-13 | 深圳市华星光电半导体显示技术有限公司 | array substrate and display panel |
| CN113363300A (en) * | 2021-06-01 | 2021-09-07 | 霸州市云谷电子科技有限公司 | Array substrate and display panel |
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