CN104238214B - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN104238214B CN104238214B CN201410355954.4A CN201410355954A CN104238214B CN 104238214 B CN104238214 B CN 104238214B CN 201410355954 A CN201410355954 A CN 201410355954A CN 104238214 B CN104238214 B CN 104238214B
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- array base
- base palte
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- display area
- shifting deposit
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Abstract
The invention relates to an array substrate and a display panel. The array substrate comprises an effective display area, wherein a plurality of first pixels are arranged in the effective display area; a grid electrode driving circuit is arranged on the array substrate and is arranged in the effective display area; the grid electrode driving circuit comprises multiple stages of shift register cells which are arranged along the longitudinal direction of the array substrate at intervals; a row of second pixels are arranged between every two adjacent stages of shift register cells; in addition, the heights of the shift register cells are sequentially and gradually reduced along the direction away from the first pixel connected with the shift register cell of each stage towards the direction close to the first pixel. According to the array substrate, the narrow bezel can be realized, an area where the grid electrode driving circuit is located can be used for displaying, and the influence on display frame of the display panel due to the fact that the grid electrode driving circuit is arranged in the effective display area is reduced.
Description
Technical field
The present invention relates to technical field of liquid crystal display, in particular it relates to a kind of array base palte and display floater.
Background technology
In the preparation process of the array base palte of liquid crystal indicator, can be by etching technics by gate driver circuit
(Gate-driver IC) is prepared on array base palte (Array), and that is, GOA (Gate-driver On Array), so permissible
Reduce the space shared by gate driver circuit, such that it is able to reduce the width of screen frame, contribute to realizing LCD
The narrow frame of plate.
Fig. 1 is the schematic diagram of the existing array base palte being provided with gate driver circuit；Fig. 2 is array base palte shown in Fig. 1
Sectional view along A-A；Fig. 3 is the schematic diagram of array base palte lastrow pixel shown in Fig. 1.As shown in Figure 1-Figure 3, array base palte 1
Fringe region 3 including effective display area (Active Area) 2 with positioned at effective display area both sides.Wherein, effective display area 2
It is provided with multiple pixels 6, multiple pixels 6 become along the transversely arranged one-tenth multirow of array base palte 1, the longitudinal arrangement along array base palte 1
Multiple row.Fringe region 3 is provided with gate driver circuit 4, holding wire 5 and public electrode wire 7；Specifically, holding wire 5 is to raster data model
Circuit 4 provides signal, and gate driver circuit 4 is according to this signal to the multiple gate lines on-load voltage successively on array base palte 1；And
Public electrode wire 7 is then used for providing Vcom signal to public electrode.
In above-mentioned array base palte 1, because gate driver circuit 4, holding wire 5 and public electrode wire 7 are arranged on marginal zone
On domain 3, this makes fringe region 3 need to have certain width, thus limits the reduction further of the width of fringe region 3,
So that the width of frame cannot be reduced in liquid crystal indicator further.
Content of the invention
It is contemplated that at least solving one of technical problem present in prior art it is proposed that a kind of array base palte and aobvious
Show panel, gate driver circuit is arranged in the effective display area on array base palte for it, thus reducing the side of array base palte
The width in edge region, contributes to realizing narrow frame；And, along the first pixel being connected away from every grade of shifting deposit unit to close
The direction of this first pixel, the height of every grade of shifting deposit unit reduces successively, sets gate driver circuit such that it is able to reduce
Put the impact in effective display area, display floater display picture being caused.
There is provided a kind of array base palte for realizing the purpose of the present invention, it includes effective display area, described effective display area
Multiple first pixels of interior setting, described array base palte is provided with gate driver circuit, and described gate driver circuit is arranged on described
In effective display area；Described gate driver circuit includes stages shift deposit unit, and multistage described shifting deposit unit is along described
It is provided with a line second pixel between the longitudinally spaced setting of array base palte, and adjacent the two poles of the earth shifting deposit unit；And, along far
From the first connected pixel of every grade of shifting deposit unit to the direction near this first pixel, the height of described shifting deposit unit
Successively decrease successively.
Wherein, described array base palte also includes fringe region, described fringe region is located at the one of described effective display area
Side or both sides；Described gate driver circuit is located at the edge of described effective display area, and connects with described fringe region.
Wherein, described array base palte is provided with drive circuit holding wire, and described drive circuit holding wire is located at described effective
In viewing area, and it is connected with the shifting deposit unit of described gate driver circuit, for providing letter to described shifting deposit unit
Number.
Wherein, described drive circuit holding wire is located on described array base palte the surface of data wire or underface.
Wherein, described array base palte is provided with drive circuit holding wire, and described drive circuit holding wire is located at described array
On the fringe region positioned at described effective display area one or both sides on substrate, and post with the displacement of described gate driver circuit
Memory cell connects, for providing signal to described shifting deposit unit.
Wherein, described array base palte is provided with public electrode wire, and described public electrode wire is located in described effective display area,
And be connected with public electrode, for providing voltage signal to public electrode.
Wherein, described public electrode wire is located on described array base palte the surface of data wire or underface.
Wherein, described array base palte is provided with public electrode wire, and described public electrode wire is located on described array base palte
In the fringe region of described effective display area one or both sides, and it is connected with public electrode, for described public electrode
Voltage signal is provided.
Wherein, every grade of described shifting deposit unit includes multiple first subelements, each first subelement and one second
Pixel is corresponding in the longitudinal direction of described array base palte, and the height of each described first subelement and the second corresponding pixel
Degree sum, with and described shifting deposit unit be connected described first pixel height equal.
Wherein, along the first pixel being connected away from every grade of shifting deposit unit to the direction near this first pixel, described
The height of multiple first subelements in shifting deposit unit successively decreases successively.
Wherein, described array base palte is additionally provided with black matrix, described black matrix includes the first black matrix and the second black matrix,
Described first black matrix is arranged at the top of described shifting deposit unit, each described first black matrix and the shifting being disposed below
Position deposit unit synchronously successively decreases in same direction；Described second black matrix is arranged above the gate line of described array base palte.
As another technical scheme, the present invention also provides a kind of display floater, including array base palte, described array base palte
The above-mentioned array base palte being provided using the present invention.
The invention has the advantages that：
The array base palte that the present invention provides, its gate driver circuit is arranged in the effective display area of array base palte, permissible
Reduce the width of the fringe region that effective display area one or both sides are located on array base palte, thus contributing to realizing narrow frame.
And, it is provided with a line second pixel between adjacent two-stage shifting deposit unit so that effective display area inner grid drives electricity
Road region can still be used for shows.Additionally, along away from every grade of shifting deposit unit be connected the first pixel near this first
The direction of pixel, the height of this shifting deposit unit gradually successively decreases, and so that the aperture opening ratio of gate driver circuit region is progressively subtracted
Little, such that it is able to reduce, gate driver circuit is arranged on the impact in effective display area, display floater display picture is caused.
The display floater that the present invention provides, it adopts the above-mentioned array base palte that the present invention provides, and can reduce array base palte
The width of the upper fringe region being located at effective display area one or both sides, thus contribute to realizing narrow frame；And so that grid is driven
Dynamic circuit region can still be used for shows；And gate driver circuit is arranged in effective display area to display floater for reduction
The impact that display picture causes.
Brief description
Accompanying drawing is used to provide a further understanding of the present invention, and constitutes the part of specification, with following tool
Body embodiment is used for explaining the present invention together, but is not construed as limiting the invention.In the accompanying drawings：
Fig. 1 is the schematic diagram of the existing array base palte being provided with gate driver circuit；
Fig. 2 is array base palte shown in Fig. 1 along the sectional view of A-A；
Fig. 3 is the schematic diagram of array base palte lastrow pixel shown in Fig. 1.
The schematic diagram of the array base palte that Fig. 4 provides for first embodiment of the invention；
Fig. 5 is the schematic top plan view of array base palte shown in Fig. 4；
Fig. 6 is the schematic diagram of array base palte lastrow pixel shown in Fig. 4；
The schematic diagram of the array base palte that Fig. 7 provides for second embodiment of the invention.
Description of reference numerals
1：Array base palte；2：Effective display area；3：Fringe region；4：Gate driver circuit；5：Holding wire；6：Pixel；7：
Public electrode wire；
10：Array base palte；11：Effective display area；12：Fringe region；13：Shifting deposit unit；14：Drive circuit signal
Line；16：Public electrode wire；110：First pixel；111：Second pixel；130：First subelement.
Specific embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.It should be appreciated that this place is retouched
The specific embodiment stated is merely to illustrate and explains the present invention, is not limited to the present invention.
The schematic diagram of the array base palte that Fig. 4 provides for first embodiment of the invention；Fig. 5 is bowing of array base palte shown in Fig. 4
Depending on schematic diagram.As shown in Figure 4 and Figure 5, array base palte 10 includes effective display area (Active Area) 11 and fringe region 12.
Multiple first pixels 110 are set in effective display area 11, the plurality of first pixel 110 along array base palte 10 horizontal and vertical according to
Secondary setting, that is, horizontal along array base palte 10, multiple first pixels 110 can be divided into multirow, along the longitudinal direction of array base palte 10, multiple
First pixel 110 can be divided into multiple row (multiple row first pixel is not shown).Fringe region 12 be located at effective display area 11 side or
Both sides.Array base palte 10 is provided with gate driver circuit, and this gate driver circuit is arranged in effective display area 11；Specifically,
Gate driver circuit includes stages shift deposit unit 13, specifically, every grade of shifting deposit unit 13 and a line the first pixel 110
It is connected；Stages shift deposit unit 13 is along the longitudinally spaced setting of array base palte 10；And adjacent two-stage shifting deposit unit 13
Between be provided with a line the second pixel 111.
In the present embodiment, gate driver circuit is arranged in effective display area 11 so that need not in fringe region 12
Setting gate driver circuit, such that it is able to reduce the width of fringe region 12, contributes to realizing the narrow frame of display floater.And
And, a line the second pixel 111 is set between adjacent two-stage shifting deposit unit 13, gate driver circuit location can be made
Domain can still be used for shows.
In the present embodiment, as shown in figure 5, edge is away from connected a line the first pixel 110 of every grade of shifting deposit unit 13
To the direction near this first pixel 110, the height of this shifting deposit unit 13 successively decreases successively.Wherein, so-called " highly " refers to
Distance in the longitudinal direction of array base palte 10.
In the present embodiment, array base palte 10 is additionally provided with black matrix (not shown), black matrix includes the first black square
Battle array and the second black matrix, the first black matrix is arranged at the top of shifting deposit unit 13, each first black matrix with it
The shifting deposit unit 13 of side is synchronous in same direction to successively decrease；Second black matrix is arranged on the gate line of array base palte 10
Side.
In the present embodiment, due to along a line the first pixel 110 being connected away from every grade of shifting deposit unit 13 to leaning on
The direction of this first pixel 110 nearly, the height of this shifting deposit unit 13 gradually successively decreases so that gate driver circuit region
Aperture opening ratio progressively reduce, such that it is able to reduce gate driver circuit is arranged in effective display area 11, display floater is shown
The impact that picture causes.
Specifically, as shown in fig. 6, every grade of shifting deposit unit 13 includes multiple first subelements 130, each first son is single
Unit is 130 corresponding in the longitudinal direction of array base palte 10 with second pixel 111, and each first subelement 130 and right with it
The height sum of the second pixel 111 answered, with and shifting deposit unit 13 be connected a line the first pixel 110 height equal.
In the case, as shown in fig. 6, the height of every grade of shifting deposit unit 13 successively decreases successively shows as：Edge is posted away from every grade of displacement
A line the first pixel 110 that memory cell 13 is connected is to the direction near this first pixel 110, multiple in shifting deposit unit 13
The height of the first subelement 130 successively decreases successively；In other words, the height of the first adjacent subelement 130 of any two all not phases
With, the amplitude of the height change of every grade of shifting deposit unit 13 so can be made to reach gentle and linear to greatest extent, thus
Reduce the impact that display floater display picture is caused.
Preferably, in the present embodiment, gate driver circuit be located at effective display area 11 edge, and with fringe region 12
Connect；So setting can reduce the technology difficulty preparing gate driver circuit it is easier to realize, and, raster data model is electric
Road is arranged on the edge of effective display area, so that the height of every grade of shifting deposit unit 13 only need to be successively decreased in one direction,
As shown in Figure 5 and Figure 6.
Drive circuit holding wire 14 and public electrode wire 16 are provided with array base palte 10, this drive circuit holding wire 14 He
Public electrode wire 16 is located in fringe region 12.And, drive circuit holding wire 14 and the shift LD list of gate driver circuit
Unit 13 connection, in order to provide signal to shifting deposit unit 13；Public electrode wire 16 is connected with public electrode, for common electrical
Pole provides voltage signal.
The array base palte 10 that the present embodiment provides, its gate driver circuit is arranged on the effective display area 11 of array base palte 10
Interior, the width of the fringe region 12 that effective display area 11 one or both sides are located on array base palte 10 can be reduced, thus helping
In realizing narrow frame.And, it is provided with a line the second pixel 111 between adjacent two-stage shifting deposit unit 13 so that effectively
Viewing area 11 inner grid drive circuit region can still be used for shows.Additionally, being connected along away from every grade of shifting deposit unit 13
A line the first pixel 110 near this first pixel 110 direction, the height of this shifting deposit unit 13 gradually successively decreases, and makes
The aperture opening ratio of gate driver circuit region progressively reduces, and such that it is able to reduce, gate driver circuit is arranged on effective display
The impact in area 11, display floater display picture being caused.
It should be noted that in the present embodiment, gate driver circuit is arranged on the edge of effective display area 11, and and side
Edge region 12 connects, but the present invention is not limited to this, and in actual applications, gate driver circuit can also be arranged on effective display
The inside in area 11, do not connect with fringe region 12 it is readily appreciated that, in the case, two along shifting deposit unit 13 are lateral
Center position, its height incremented by successively.
The schematic diagram of the array base palte that Fig. 7 provides for second embodiment of the invention.As shown in fig. 7, what the present embodiment provided
Array base palte 10, compared with above-mentioned first embodiment, equally includes effective display area 11, and its gate driver circuit is equally arranged
In effective display area 11, and along a line the first pixel 110 being connected away from every grade of shifting deposit unit 13 near this
The direction of one pixel 110, the height of this shifting deposit unit 13 successively decreases successively, because the above is in first embodiment of the invention
In there has been detailed description, will not be described here.
Only the array base palte 10 of the present embodiment offer is retouched in detail with the difference of above-mentioned first embodiment below
State.In the present embodiment, array base palte 10 is again provided with drive circuit holding wire 14 and public electrode wire 16, but with above-mentioned
Unlike one embodiment, drive circuit holding wire 14 and public electrode wire 16 are located in effective display area 11.Specifically, drive
Circuit signal line 14 is connected with the shifting deposit unit 13 of gate driver circuit, for providing signal to shifting deposit unit 13；
Public electrode wire 16 is connected with public electrode, for providing voltage signal to public electrode.
In the present embodiment, drive circuit holding wire 14 and public electrode wire 16 are also disposed in effective display area 11,
Thus removing the fringe region of the one or both sides being located at effective display area 11, it is possible to achieve the display floater of Rimless.
Preferably, in the present embodiment, the number that drive circuit holding wire 14, public electrode wire 16 are located on array base palte 10
Surface or underface according to line.Wherein, so-called " top " is the direction towards beholder of display floater, and so-called " lower section " is
The direction away from beholder of display floater.Above-mentioned setting can be realized in the case of the aperture opening ratio not reducing array base palte
Drive circuit holding wire 14, public electrode wire 16 are arranged in effective display area 11.Easy to understand, which increase Array
It is masked the number of times of plate technique, thus increased production cost in technique；Therefore, in actual applications it is also possible to setting is driven
Same layer on array base palte 10 for the data line bit on dynamic circuit signal line 14, public electrode wire 16 and array base palte 10, this
Sample would not change the number of times being masked plate technique in Array technique, thus not increasing production cost.
As another technical scheme, the embodiment of the present invention also provides a kind of display floater, including array base palte, this array
Substrate adopts the array base palte that the above embodiment of the present invention provides.
Display floater provided in an embodiment of the present invention, it adopts the array base palte that the above embodiment of the present invention provides, permissible
Reduce the width of the fringe region that effective display area one or both sides are located on array base palte, thus contributing to realizing narrow frame；
And so that gate driver circuit region can still be used for is shown；And gate driver circuit is arranged on effective display area by reduction
The interior impact that display floater display picture is caused.
It is understood that the embodiment of above principle being intended to be merely illustrative of the present and the exemplary enforcement adopting
Mode, but the invention is not limited in this.For those skilled in the art, in the essence without departing from the present invention
In the case of god and essence, various modifications and improvement can be made, these modifications and improvement are also considered as protection scope of the present invention.
Claims (12)
1. a kind of array base palte, it includes effective display area, arranges multiple first pixels in described effective display area, and its feature exists
In described array base palte is provided with gate driver circuit, and described gate driver circuit is arranged in described effective display area；
Described gate driver circuit includes stages shift deposit unit, and multistage described shifting deposit unit is along described array base palte
It is provided with a line second pixel between longitudinally spaced setting, and adjacent the two poles of the earth shifting deposit unit；And, shift along away from every grade
The first pixel that deposit unit is connected is successively decreased successively to the direction near this first pixel, the height of described shifting deposit unit.
2. array base palte according to claim 1 is it is characterised in that also include fringe region, institute on described array base palte
State the one or both sides that fringe region is located at described effective display area；
Described gate driver circuit is located at the edge of described effective display area, and connects with described fringe region.
3. array base palte according to claim 1 is it is characterised in that described array base palte is provided with drive circuit signal
Line, described drive circuit holding wire is located in described effective display area, and the shifting deposit unit with described gate driver circuit
Connect, for providing signal to described shifting deposit unit.
4. array base palte according to claim 3 is it is characterised in that described drive circuit holding wire is located at described array base
The surface of the data wire on plate or underface.
5. array base palte according to claim 1 is it is characterised in that described array base palte is provided with drive circuit signal
Line, the marginal zone positioned at described effective display area one or both sides that described drive circuit holding wire is located on described array base palte
On domain, and it is connected with the shifting deposit unit of described gate driver circuit, for providing signal to described shifting deposit unit.
6. array base palte according to claim 1 is it is characterised in that described array base palte is provided with public electrode wire, institute
State public electrode wire to be located in described effective display area, and be connected with public electrode, for providing voltage signal to public electrode.
7. array base palte according to claim 6 is it is characterised in that described public electrode wire is located on described array base palte
The surface of data wire or underface.
8. array base palte according to claim 1 is it is characterised in that described array base palte is provided with public electrode wire, institute
State public electrode wire to be located in the fringe region positioned at described effective display area one or both sides on described array base palte, and with
Public electrode connects, for providing voltage signal to described public electrode.
9. array base palte according to claim 1 is it is characterised in that every grade of described shifting deposit unit includes multiple first
Subelement, each first subelement is corresponding in the longitudinal direction of described array base palte with second pixel, and each described
One subelement and the height sum of the second corresponding pixel, with and described first pixel that is connected of described shifting deposit unit
Height equal.
10. array base palte according to claim 9 is it is characterised in that along the being connected away from every grade of shifting deposit unit
One pixel is passed successively to the direction near this first pixel, the height of multiple first subelements in described shifting deposit unit
Subtract.
11. array base paltes according to claim 1 are it is characterised in that being additionally provided with black matrix on described array base palte, described
Black matrix includes the first black matrix and the second black matrix, and described first black matrix is arranged at the top of described shifting deposit unit,
Each described first black matrix and the shifting deposit unit being disposed below synchronously successively decrease in same direction；
Described second black matrix is arranged above the gate line of described array base palte.
A kind of 12. display floaters, including array base palte it is characterised in that described array base palte adopts claim 1-11 any
Array base palte described in one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410355954.4A CN104238214B (en) | 2014-07-24 | 2014-07-24 | Array substrate and display panel |
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| CN201410355954.4A CN104238214B (en) | 2014-07-24 | 2014-07-24 | Array substrate and display panel |
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| CN104238214B true CN104238214B (en) | 2017-02-15 |
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| CN104464533B (en) * | 2014-12-10 | 2017-03-15 | 京东方科技集团股份有限公司 | A kind of display floater, display device |
| CN104536176B (en) | 2014-12-25 | 2017-07-14 | 上海天马微电子有限公司 | Array substrate, display panel and display device |
| CN104537993B (en) | 2014-12-29 | 2018-09-21 | 厦门天马微电子有限公司 | Organic light emitting display panel |
| CN104536229B (en) * | 2015-01-12 | 2017-02-01 | 京东方科技集团股份有限公司 | Array substrate and display panel |
| CN104699349B (en) * | 2015-04-01 | 2017-12-05 | 上海天马微电子有限公司 | Array substrate, manufacturing method thereof and display panel |
| CN105206212A (en) * | 2015-08-27 | 2015-12-30 | 京东方科技集团股份有限公司 | Display panel and display apparatus |
| CN105261621B (en) | 2015-09-06 | 2018-01-30 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
| CN105139806B (en) | 2015-10-21 | 2018-05-01 | 京东方科技集团股份有限公司 | Array base palte, display panel and display device |
| CN105575318B (en) * | 2016-03-18 | 2019-02-26 | 京东方科技集团股份有限公司 | A kind of display panel and display device |
| CN106097968A (en) * | 2016-08-26 | 2016-11-09 | 京东方科技集团股份有限公司 | Display floater and display device |
| TWI639996B (en) | 2016-10-28 | 2018-11-01 | 友達光電股份有限公司 | Display panel and display wall |
| CN106950770B (en) * | 2017-03-28 | 2019-08-02 | 厦门天马微电子有限公司 | Array substrate and its manufacturing method and display device |
| CN106952607B (en) * | 2017-05-25 | 2020-04-17 | 京东方科技集团股份有限公司 | Display substrate, display panel and display device |
| CN109658837A (en) * | 2017-10-12 | 2019-04-19 | 群创光电股份有限公司 | Semiconductor device and the method for driving semiconductor device |
| CN107862998B (en) * | 2017-11-09 | 2020-05-19 | 深圳市华星光电半导体显示技术有限公司 | Flexible GOA display panel and manufacturing method thereof |
| WO2020004663A1 (en) * | 2018-06-29 | 2020-01-02 | 京セラ株式会社 | Display device |
| CN109272957A (en) * | 2018-11-07 | 2019-01-25 | 中国科学院微电子研究所 | Frameless display structure and frameless display |
| EP3987508A1 (en) * | 2019-11-08 | 2022-04-27 | Google LLC | Display with discrete gate-in-panel circuitry |
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