CN104238214A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN104238214A CN104238214A CN201410355954.4A CN201410355954A CN104238214A CN 104238214 A CN104238214 A CN 104238214A CN 201410355954 A CN201410355954 A CN 201410355954A CN 104238214 A CN104238214 A CN 104238214A
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- base palte
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Abstract
The invention relates to an array substrate and a display panel. The array substrate comprises an effective display area, wherein a plurality of first pixels are arranged in the effective display area; a grid electrode driving circuit is arranged on the array substrate and is arranged in the effective display area; the grid electrode driving circuit comprises multiple stages of shift register cells which are arranged along the longitudinal direction of the array substrate at intervals; a row of second pixels are arranged between every two adjacent stages of shift register cells; in addition, the heights of the shift register cells are sequentially and gradually reduced along the direction away from the first pixel connected with the shift register cell of each stage towards the direction close to the first pixel. According to the array substrate, the narrow bezel can be realized, an area where the grid electrode driving circuit is located can be used for displaying, and the influence on display frame of the display panel due to the fact that the grid electrode driving circuit is arranged in the effective display area is reduced.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly, relate to a kind of array base palte and display panel.
Background technology
In the preparation process of the array base palte of liquid crystal indicator, gate driver circuit (Gate-driver IC) can be prepared on array base palte (Array) by etching technics, i.e. GOA (Gate-driver On Array), the space shared by gate driver circuit can be reduced like this, thus the width of screen frame can be reduced, contribute to the narrow frame realizing display panels.
Fig. 1 is the existing schematic diagram being provided with the array base palte of gate driver circuit; Fig. 2 is for array base palte shown in Fig. 1 is along the sectional view of A-A; Fig. 3 is the schematic diagram of the lastrow of array base palte shown in Fig. 1 pixel.As shown in Figure 1-Figure 3, array base palte 1 comprises effective display area (Active Area) 2 and is positioned at the fringe region 3 of both sides, effective display area.Wherein, effective display area 2 is provided with multiple pixel 6, and multiple pixel 6 is along the transversely arranged one-tenth multirow of array base palte 1, and the longitudinal arrangement along array base palte 1 becomes multiple row.Fringe region 3 is provided with gate driver circuit 4, signal wire 5 and public electrode wire 7; Particularly, signal wire 5 provides signal to gate driver circuit 4, gate driver circuit 4 according to this signal to the multiple gate lines on-load voltage successively on array base palte 1; Public electrode wire 7 is then for providing Vcom signal to public electrode.
In above-mentioned array base palte 1, because gate driver circuit 4, signal wire 5 and public electrode wire 7 are arranged on fringe region 3, this makes fringe region 3 need have certain width, thus limit the further reduction of the width of fringe region 3, thus make the width that cannot reduce frame in liquid crystal indicator further.
Summary of the invention
The present invention is intended at least to solve one of technical matters existed in prior art, propose a kind of array base palte and display panel, gate driver circuit is arranged in the effective display area on array base palte by it, thus reduces the width of the fringe region of array base palte, contributes to realizing narrow frame; And, along the first pixel be connected away from every grade of shifting deposit unit to the direction near this first pixel, the height of every grade of shifting deposit unit reduces successively, thus can reduce and be arranged in effective display area gate driver circuit on the impact that display panel display frame causes.
There is provided a kind of array base palte for realizing object of the present invention, it comprises effective display area, and arrange multiple first pixel in described effective display area, described array base palte is provided with gate driver circuit, and described gate driver circuit is arranged in described effective display area; Described gate driver circuit comprises stages shift deposit unit, and multistage described shifting deposit unit is arranged along the longitudinal separation of described array base palte, and is provided with a line second pixel between adjacent the two poles of the earth shifting deposit unit; Further, along the first pixel be connected away from every grade of shifting deposit unit to the direction near this first pixel, the height of described shifting deposit unit successively decreases successively.
Wherein, described array base palte also comprises fringe region, described fringe region is positioned at the one or both sides of described effective display area; Described gate driver circuit is positioned at the edge of described effective display area, and connects with described fringe region.
Wherein, described array base palte is provided with driving circuit signal wire, and described driving circuit signal wire is positioned at described effective display area, and is connected with the shifting deposit unit of described gate driver circuit, for providing signal to described shifting deposit unit.
Wherein, directly over described driving circuit signal wire is positioned on described array base palte data line or immediately below.
Wherein, described array base palte is provided with driving circuit signal wire, described driving circuit signal wire is positioned on the fringe region being positioned at one or both sides, described effective display area on described array base palte, and be connected with the shifting deposit unit of described gate driver circuit, for providing signal to described shifting deposit unit.
Wherein, described array base palte is provided with public electrode wire, and described public electrode wire is positioned at described effective display area, and is connected with public electrode, for providing voltage signal to public electrode.
Wherein, directly over described public electrode wire is positioned on described array base palte data line or immediately below.
Wherein, described array base palte is provided with public electrode wire, and described public electrode wire is positioned at the fringe region being positioned at one or both sides, described effective display area on described array base palte, and is connected with public electrode, for providing voltage signal to described public electrode.
Wherein, every grade of described shifting deposit unit comprises multiple first subelement, each first subelement is corresponding in the longitudinal direction of described array base palte with second pixel, and the height sum of each described first subelement and second pixel corresponding with it, the height of described first pixel be connected with described shifting deposit unit is equal.
Wherein, along the first pixel be connected away from every grade of shifting deposit unit to the direction near this first pixel, the height of multiple first subelements in described shifting deposit unit successively decreases successively.
Wherein, described array base palte is also provided with black matrix, described black matrix comprises the first black matrix and the second black matrix, and described first black arranged in matrix is in the top of described shifting deposit unit, and each described first black matrix synchronously successively decreases along identical direction with the shifting deposit unit be positioned at below it; Described second black arranged in matrix is above the gate line of described array base palte.
As another technical scheme, the present invention also provides a kind of display panel, comprises array base palte, and described array base palte adopts above-mentioned array base palte provided by the invention.
The present invention has following beneficial effect:
Array base palte provided by the invention, its gate driver circuit is arranged in the effective display area of array base palte, can reduce the width of fringe region array base palte being positioned at one or both sides, effective display area, thus contributes to realizing narrow frame.Further, between adjacent two-stage shifting deposit unit, be provided with a line second pixel, make inner grid driving circuit region, effective display area still can be used for display.In addition, along the first pixel be connected away from every grade of shifting deposit unit to the direction near this first pixel, the height of this shifting deposit unit successively decreases gradually, the aperture opening ratio of gate driver circuit region is progressively reduced, thus can reduce gate driver circuit is arranged in effective display area the impact that display panel display frame causes.
Display panel provided by the invention, it adopts above-mentioned array base palte provided by the invention, can reduce the width of fringe region array base palte being positioned at one or both sides, effective display area, thus contributes to realizing narrow frame; And make gate driver circuit region still can be used for display; And gate driver circuit is arranged in effective display area the impact that display panel display frame causes by reduction.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, and forms a part for instructions, is used from explanation the present invention, but is not construed as limiting the invention with embodiment one below.In the accompanying drawings:
Fig. 1 is the existing schematic diagram being provided with the array base palte of gate driver circuit;
Fig. 2 is for array base palte shown in Fig. 1 is along the sectional view of A-A;
Fig. 3 is the schematic diagram of the lastrow of array base palte shown in Fig. 1 pixel.
The schematic diagram of the array base palte that Fig. 4 provides for first embodiment of the invention;
Fig. 5 is the schematic top plan view of array base palte shown in Fig. 4;
Fig. 6 is the schematic diagram of the lastrow of array base palte shown in Fig. 4 pixel;
The schematic diagram of the array base palte that Fig. 7 provides for second embodiment of the invention.
Description of reference numerals
1: array base palte; 2: effective display area; 3: fringe region; 4: gate driver circuit; 5: signal wire; 6: pixel; 7: public electrode wire;
10: array base palte; 11: effective display area; 12: fringe region; 13: shifting deposit unit; 14: driving circuit signal wire; 16: public electrode wire; 110: the first pixels; 111: the second pixels; 130: the first subelements.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Should be understood that, embodiment described herein, only for instruction and explanation of the present invention, is not limited to the present invention.
The schematic diagram of the array base palte that Fig. 4 provides for first embodiment of the invention; Fig. 5 is the schematic top plan view of array base palte shown in Fig. 4.As shown in Figure 4 and Figure 5, array base palte 10 comprises effective display area (Active Area) 11 and fringe region 12.Multiple first pixel 110 is set in effective display area 11, the plurality of first pixel 110 sets gradually along the horizontal and vertical of array base palte 10, namely along the transverse direction of array base palte 10, multiple first pixel 110 can be divided into multirow, along the longitudinal direction of array base palte 10, multiple first pixel 110 can be divided into multiple row (multiple row first pixel is not shown).Fringe region 12 is positioned at the one or both sides of effective display area 11.Array base palte 10 is provided with gate driver circuit, and this gate driver circuit is arranged in effective display area 11; Particularly, gate driver circuit comprises stages shift deposit unit 13, and particularly, every grade of shifting deposit unit 13 is connected with a line first pixel 13; Stages shift deposit unit 13 is arranged along the longitudinal separation of array base palte 10; And be provided with a line second pixel 111 between adjacent two-stage shifting deposit unit 13.
In the present embodiment, gate driver circuit is arranged in effective display area 11, makes without the need to arranging gate driver circuit in fringe region 12, thus the width of fringe region 12 can be reduced, contribute to the narrow frame realizing display panel.Further, a line second pixel 111 is set between adjacent two-stage shifting deposit unit 13, gate driver circuit region can be made still to can be used for display.
In the present embodiment, as shown in Figure 5, along a line first pixel 110 be connected away from every grade of shifting deposit unit 13 to the direction near this first pixel 110, the height of this shifting deposit unit 13 successively decreases successively.Wherein, so-called " highly " refers to the distance in the longitudinal direction of array base palte 10.
In the present embodiment, array base palte 10 is also provided with black matrix (not shown), black matrix comprises the first black matrix and the second black matrix, first black arranged in matrix is in the top of shifting deposit unit 13, and each first black matrix synchronously successively decreases along identical direction with the shifting deposit unit 13 be positioned at below it; Second black arranged in matrix is above the gate line of array base palte 10.
In the present embodiment, due to along a line first pixel 110 be connected away from every grade of shifting deposit unit 13 to the direction near this first pixel 110, the height of this shifting deposit unit 13 successively decreases gradually, the aperture opening ratio of gate driver circuit region is progressively reduced, thus the impact being arranged on by gate driver circuit and in effective display area 11, display panel display frame being caused can be reduced.
Particularly, as shown in Figure 6, every grade of shifting deposit unit 13 comprises multiple first subelement 130, each first subelement 130 is corresponding in the longitudinal direction of array base palte 10 with second pixel 111, and the height sum of each first subelement 130 and second pixel 111 corresponding with it, equal with the height of a line first pixel 110 that shifting deposit unit 13 is connected.In the case, as shown in Figure 6, the height of every grade of shifting deposit unit 13 successively decreases successively and shows as: along a line first pixel 110 be connected away from every grade of shifting deposit unit 13 to the direction near this first pixel 110, the height of multiple first subelements 130 in shifting deposit unit 13 successively decreases successively; In other words, the height of any two adjacent the first subelements 130 is all not identical, and the amplitude of the height change of every grade of shifting deposit unit 13 can be made like this to reach mild and linear to greatest extent, thus reduces the impact that causes display panel display frame.
Preferably, in the present embodiment, gate driver circuit is positioned at the edge of effective display area 11, and connects with fringe region 12; The technology difficulty that can reduce to prepare gate driver circuit is set like this, be easier to realize, and, gate driver circuit is arranged on the edge of effective display area, also make the height of every grade of shifting deposit unit 13 only need successively decrease along a direction, as shown in Figure 5 and Figure 6.
Array base palte 10 is provided with driving circuit signal wire 14 and public electrode wire 16, this driving circuit signal wire 14 and public electrode wire 16 are positioned at fringe region 12.Further, driving circuit signal wire 14 is connected with the shifting deposit unit 13 of gate driver circuit, in order to provide signal to shifting deposit unit 13; Public electrode wire 16 is connected with public electrode, for providing voltage signal to public electrode.
The array base palte 10 that the present embodiment provides, its gate driver circuit is arranged in the effective display area 11 of array base palte 10, can reduce the width of the fringe region 12 array base palte 10 being positioned at one or both sides, effective display area 11, thus contributes to realizing narrow frame.Further, between adjacent two-stage shifting deposit unit 13, be provided with a line second pixel 111, make inner grid driving circuit region, effective display area 11 still can be used for display.In addition, along a line first pixel 110 be connected away from every grade of shifting deposit unit 13 to the direction near this first pixel 110, the height of this shifting deposit unit 13 successively decreases gradually, the aperture opening ratio of gate driver circuit region is progressively reduced, thus the impact being arranged on by gate driver circuit and in effective display area 11, display panel display frame being caused can be reduced.
It should be noted that, in the present embodiment, gate driver circuit is arranged on the edge of effective display area 11, and connects with fringe region 12, but the present invention is not limited to this, in actual applications, gate driver circuit can also be arranged on the inside of effective display area 11, does not namely connect with fringe region 12, easy understand, in the case, along two side direction center positions of shifting deposit unit 13, it increases progressively highly successively.
The schematic diagram of the array base palte that Fig. 7 provides for second embodiment of the invention.As shown in Figure 7, the array base palte 10 that the present embodiment provides is compared with above-mentioned first embodiment, comprise effective display area 11 equally, and its gate driver circuit is arranged in effective display area 11 equally, and along a line first pixel 110 be connected away from every grade of shifting deposit unit 13 to the direction near this first pixel 110, the height of this shifting deposit unit 13 successively decreases successively, because foregoing there has been detailed description in the first embodiment of the invention, does not repeat them here.
The array base palte 10 only provided with regard to the present embodiment is below described in detail with the difference of above-mentioned first embodiment.In the present embodiment, array base palte 10 is provided with equally driving circuit signal wire 14 and public electrode wire 16, but with above-mentioned first embodiment unlike, driving circuit signal wire 14 and public electrode wire 16 are positioned at effective display area 11.Particularly, driving circuit signal wire 14 is connected with the shifting deposit unit 13 of gate driver circuit, for providing signal to shifting deposit unit 13; Public electrode wire 16 is connected with public electrode, for providing voltage signal to public electrode.
In the present embodiment, driving circuit signal wire 14 and public electrode wire 16 are also arranged in effective display area 11, thus remove the fringe region being positioned at the one or both sides of effective display area 11, the display panel of Rimless can be realized.
Preferably, in the present embodiment, directly over driving circuit signal wire 14, public electrode wire 16 are positioned on array base palte 10 data line or immediately below.Wherein, the direction towards beholder that so-called " top " is display panel, the direction away from beholder that so-called " below " is display panel.Above-mentioned setting can, when not reducing the aperture opening ratio of array base palte, realize driving circuit signal wire 14, public electrode wire 16 to be arranged in effective display area 11.Easy understand, which increases the number of times carrying out mask plate technique in Array technique, thus adds production cost; Therefore, in actual applications, driving circuit signal wire 14, public electrode wire 16 and the same layer of data line bit on array base palte 10 on array base palte 10 also can be set, the number of times carrying out mask plate technique in Array technique would not be changed like this, thus can not production cost be increased.
As another technical scheme, the embodiment of the present invention also provides a kind of display panel, comprises array base palte, the array base palte that this array base palte adopts the above embodiment of the present invention to provide.
The display panel that the embodiment of the present invention provides, its array base palte adopting the above embodiment of the present invention to provide, can reduce the width of fringe region array base palte being positioned at one or both sides, effective display area, thus contributes to realizing narrow frame; And make gate driver circuit region still can be used for display; And gate driver circuit is arranged in effective display area the impact that display panel display frame causes by reduction.
Be understandable that, the illustrative embodiments that above embodiment is only used to principle of the present invention is described and adopts, but the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (12)
1. an array base palte, it comprises effective display area, and arrange multiple first pixel in described effective display area, it is characterized in that, described array base palte is provided with gate driver circuit, and described gate driver circuit is arranged in described effective display area;
Described gate driver circuit comprises stages shift deposit unit, and multistage described shifting deposit unit is arranged along the longitudinal separation of described array base palte, and is provided with a line second pixel between adjacent the two poles of the earth shifting deposit unit; Further, along the first pixel be connected away from every grade of shifting deposit unit to the direction near this first pixel, the height of described shifting deposit unit successively decreases successively.
2. array base palte according to claim 1, is characterized in that, described array base palte also comprises fringe region, and described fringe region is positioned at the one or both sides of described effective display area;
Described gate driver circuit is positioned at the edge of described effective display area, and connects with described fringe region.
3. array base palte according to claim 1, it is characterized in that, described array base palte is provided with driving circuit signal wire, described driving circuit signal wire is positioned at described effective display area, and be connected with the shifting deposit unit of described gate driver circuit, for providing signal to described shifting deposit unit.
4. array base palte according to claim 3, is characterized in that, described driving circuit signal wire to be positioned at directly over the data line on described array base palte or immediately below.
5. array base palte according to claim 1, it is characterized in that, described array base palte is provided with driving circuit signal wire, described driving circuit signal wire is positioned on the fringe region being positioned at one or both sides, described effective display area on described array base palte, and be connected with the shifting deposit unit of described gate driver circuit, for providing signal to described shifting deposit unit.
6. array base palte according to claim 1, is characterized in that, described array base palte is provided with public electrode wire, and described public electrode wire is positioned at described effective display area, and is connected with public electrode, for providing voltage signal to public electrode.
7. array base palte according to claim 1, is characterized in that, described public electrode wire to be positioned at directly over the data line on described array base palte or immediately below.
8. array base palte according to claim 1, it is characterized in that, described array base palte is provided with public electrode wire, described public electrode wire is positioned at the fringe region being positioned at one or both sides, described effective display area on described array base palte, and be connected with public electrode, for providing voltage signal to described public electrode.
9. array base palte according to claim 1, it is characterized in that, every grade of described shifting deposit unit comprises multiple first subelement, each first subelement is corresponding in the longitudinal direction of described array base palte with second pixel, and the height sum of each described first subelement and second pixel corresponding with it, the height of described first pixel be connected with described shifting deposit unit is equal.
10. array base palte according to claim 9, is characterized in that, along the first pixel be connected away from every grade of shifting deposit unit to the direction near this first pixel, the height of multiple first subelements in described shifting deposit unit successively decreases successively.
11. array base paltes according to claim 1, it is characterized in that, described array base palte is also provided with black matrix, described black matrix comprises the first black matrix and the second black matrix, described first black arranged in matrix is in the top of described shifting deposit unit, and each described first black matrix synchronously successively decreases along identical direction with the shifting deposit unit be positioned at below it;
Described second black arranged in matrix is above the gate line of described array base palte.
12. 1 kinds of display panels, comprise array base palte, it is characterized in that, described array base palte adopts the array base palte described in claim 1-11 any one.
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