CN106158941A - 一种双向耐压的绝缘栅双极晶体管结构 - Google Patents

一种双向耐压的绝缘栅双极晶体管结构 Download PDF

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CN106158941A
CN106158941A CN201610865714.8A CN201610865714A CN106158941A CN 106158941 A CN106158941 A CN 106158941A CN 201610865714 A CN201610865714 A CN 201610865714A CN 106158941 A CN106158941 A CN 106158941A
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way pressure
single crystalline
pressure igbt
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张广银
谭骥
卢烁今
朱阳军
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching

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Abstract

本发明公开了一种双向耐压的绝缘栅双极晶体管结构，与传统器件结构相比，在漂移区内部插入了与漂移区掺杂性质相反的异性掺杂区两个P柱区。通过改进，漂移区厚度减小，通态压降减小，晶体管的终端结构加工工艺难度和成本降低。

Description

一种双向耐压的绝缘栅双极晶体管结构
技术领域
本发明涉及功率器件领域，具体地说涉及一种双向耐压的绝缘栅双极晶体管结构。
背景技术
逆阻型绝缘栅双极型晶体管(RB-IGBT)是一种新型的IGBT器件，它是将IGBT元胞结构与耐高压的二极管元胞结构集成到同一个芯片上，具有双向耐压能力。由于现在常规的IGBT器件，为了实现通态压降和关断损耗之间良好的折中关系，在集电极上部都会有一个高掺杂的场截止(FS)层，由于高掺杂FS层的存在，在反向耐压时，元胞背面是不能够耐压的，因此逆阻型绝缘栅双极晶体管采用的都是外延的非穿通(NPT)结构，使得IGBT的厚度相对较大，器件的通态压降较大，增加了损耗。同时，较大外延层厚度也使得终端结构的实现更加困难，从而增加了工艺难度和成本，比如，扩散隔离终端需要更长时间推进硼离子，改进RB-IGBT的漂移区有望减小IGBT的厚度。
外延层厚度较大，使得器件的通态压降增大，损耗增加，且终端结构的工艺难度和成本也相应增加。
发明内容
(一)要解决的技术问题
基于以上问题，本发明提供了一种双向耐压的绝缘栅双极晶体管漂移区结构，用于减小RB-IGBT的厚度，解决现有器件通态压降大、损耗大、制作工艺难度大和成本高的问题。
(二)技术方案
本发明提出一种双向耐压的绝缘栅双极晶体管结构，包括一单晶衬底，两个P柱区和一N型外延层，其中：
所述单晶衬底为刻蚀有等距离凹槽的多个凹槽的衬底的一个单元；
所述两个P柱区外延形成于所述单晶衬底的凹槽中；
所述N型外延层形成于单晶衬底和两个P柱区的顶端。
上述单晶衬底、两个P柱区和N型外延层共同构成双向耐压的绝缘栅双极晶体管的漂移区。
上述两个P柱区材料的掺杂浓度与单晶衬底的掺杂浓度相同。
上述N型外延层是在单晶衬底和两个P柱区上经刻蚀和CMP平整化后外延生长得到的。
上述N型外延层的掺杂浓度与单晶衬底的掺杂浓度相同。
上述双向耐压的绝缘栅双极晶体管结构，在单晶衬底的下方还包括一P+集电区和一集电极，其中集电极位于P+集电区下方。
上述双向耐压的绝缘栅双极晶体管结构，在N型外延层上方还包括一p基区、两个多晶硅栅极、两个栅氧化层、两个N+源区、一P+基区、一发射极。
上述N型外延层上表面具有Trench结构，且Trench结构与两个P柱区相隔离。
上述单晶衬底的两侧凹槽等宽，其总宽度与凹槽间距离相等。
上述双向耐压的绝缘栅双极晶体管结构的制备方法与传统的IGBT正面和背面工艺相同。
(三)有益效果
本发明具有以下有益效果：
1、本发明利用电荷补偿原理在漂移区中引入异性电荷，从而在高耐压的前提下，减小了漂移区的厚度；
2、绝缘栅双极晶体管结构中漂移区的厚度减小，且P+柱区与晶体管上表面不相连，无论在正向还是反向时都可以相互耗尽，实现了双向的耐压；
3、高掺杂和更薄的漂移区使得通态压降减小，降低了通态损耗，同时降低了终端结构的工艺难度和成本。
附图说明
图1是双向耐压的绝缘栅双极晶体管结构；
图2是衬底刻蚀凹槽后的结构示意图；
图3是单晶衬底的结构示意图；
图4是填充单晶衬底凹槽形成P柱区后的结构示意图；
图5是生长N型外延层后的结构示意图。
【附图标记说明】
1-多晶硅栅极； 2-栅氧化层；
3-P柱区； 4-P+集电区；
5-P+基区； 6-N+源区；
7-发射极； 8-单晶衬底；
9-集电极； 10-N型外延层；
11-P基区
具体实施方式
如图1所示，本发明提出一种双向耐压的绝缘栅双极晶体管结构，包括一多晶硅栅极1、两个栅氧化层2、两个P柱区3、一P+集电区4、一P+基区5、一N+源区6、一发射极7、一单晶衬底8、一集电极9、一N型外延层10和一P基区11。
其中单晶衬底8、两个P柱区和N型外延层10构成双相耐压的绝缘栅双极晶体管结构的漂移区。两个P柱区3被单晶衬底8和N型外延层10完全隔离，既不与元胞上部的基区接触，也不与元胞底部的集电极区接触。同时，两个P柱区3的掺杂浓度和单晶衬底、N型外延层的掺杂浓度相同。
该双向耐压的绝缘栅双极晶体管结构的漂移区掺杂浓度高于传统的外延层浓度，且整体的外延层厚度小于传统外延层的厚度，因此，器件处于导通状态时可以明显降低导通电阻。在漂移区中引入掺杂性质相反的异性掺杂区两个P柱区3后，在耐压时，可以和单晶衬底8的杂质相互耗尽，形成近似的本征层，使纵向电场平坦分布从而提高击穿电压。
该双向耐压的绝缘栅双极晶体管结构在正向耐压时，空间电荷区从正面的N型外延层向外拓展，由于N型外延层10使得两个P柱区3与P基区相隔离，则N型外延层中的N型杂质可以和两个P柱区3的P型杂质相互补偿，从而提高击穿电压；在反向耐压时，由于单晶衬底使得两个P柱区3与P+集电区4隔离，空间电荷区从单晶衬底8的底部开始拓展，也可以与两个P柱区3相互耗尽形成耐压层，具备双向耐压能力。
漂移区厚度的减小，使得通态压降减小，晶体管的终端结构加工工艺难度和成本降低。
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明。
实施例
如图1所示，一种双向耐压的绝缘栅双极晶体管结构，包括一多晶硅栅极1、两个栅氧化层2、两个P柱区3、一P+集电区4、一P+基区5、一N+源区6、一发射极7、一单晶衬底8、一集电极9、一N型外延层10和一P基区11。
其中单晶衬底8、两个P柱区和N型外延层10构成双相耐压的绝缘栅双极晶体管结构的漂移区。该结构的工艺实现方式和现有的技术相兼容，除漂移区外，本实施例中双向耐压的绝缘栅双极晶体管结构的其他部分制备工艺与现有的技术相同。在此详细介绍其制备过程，其制备过程如下：
S1、如图2所示，以衬底为起始材料，在衬底材料上涂抹一层光刻胶，厚度为2μm，掩模曝光并进行深槽刻蚀，刻蚀深度为5μm，形成等间距的多个凹槽，凹槽宽度与凹槽间距离相等；
S2、如图3所示，取衬底的一个单元作为单晶衬底8，进行后续工艺；
S3、如图4所示，对单晶衬底8的凹槽进行牺牲氧化，氧化厚度为50nm；随后刻蚀掉氧化层，进行外延填充形成两个P+柱区，填充的杂质类型为P+，掺杂浓度和单晶衬底的掺杂浓度相同；
S4、如图5所示，对单晶衬底8凹槽外部分和两个P+柱区进行CMP平整化，随后外延生长N型外延层10，N型外延层材料的掺杂浓度和单晶衬底的掺杂浓度相同；
S5、对N型外延层10进行沟槽栅的沟槽刻蚀形成Trench结构，刻蚀深度取决于IGBT的需求，一般在5μm到10μm左右；
S6、进行沟槽栅的牺牲氧化，形成二氧化硅层，其厚度为50nm，通过刻蚀进行表面平整化，制备栅氧化层2，厚度为100nm左右；
S7、进行多晶硅的填充，形成多晶硅栅极1；
S8、根据IGBT的设计要求和阈值电压的目标，设计离子注入的剂量和能量以及推进时间和温度进行离子注入，形成P基区11；
S9、然后进行N+源区6的制备，注入的剂量和能量根据需求设计，然后进行高温推进；
S10、为了抑制栓锁而进行P+掺杂，即P+基区5的制备；
S11、淀积磷硅玻璃并回流，进行刻蚀接触孔和欧姆接触，形成正面电极7，完成正面工艺；
S12、进行背面工艺，首先进行背面减薄，根据不同的需求，设计背面P+注入的能量和剂量进行离子注入形成P+集电区4；
S13、进行背面退火，退火时间和温度为450度和60分钟，最后进行背面蒸金(Al/Ti/Ni/Ag)，形成背面集电极9，完成器件制备。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

1.一种双向耐压的绝缘栅双极晶体管结构，包括一单晶衬底，两个P柱区和一N型外延层，其中：
所述单晶衬底为刻蚀有等距离的多个凹槽的衬底的一个单元；
所述两个P柱区外延形成于所述单晶衬底的凹槽中；
所述N型外延层形成于所述单晶衬底和所述两个P柱区的顶端。
2.如权利要求1所述的双向耐压的绝缘栅双极晶体管结构，其特征在于，所述单晶衬底、所述两个P柱区和所述N型外延层构成漂移区。
3.如权利要求1所述的双向耐压的绝缘栅双极晶体管结构，其特征在于，所述两个P柱区材料的掺杂浓度与所述单晶衬底的掺杂浓度相同。
4.如权利要求1所述的双向耐压的绝缘栅双极晶体管结构，其特征在于，所述N型外延层于所述单晶衬底和所述两个P柱区经刻蚀和CMP平整化后外延生长得到。
5.如权利要求4所述的双向耐压的绝缘栅双极晶体管结构，其特征在于，所述N型外延层的掺杂浓度与所述单晶衬底的掺杂浓度相同。
6.如权利要求1所述的双向耐压的绝缘栅双极晶体管结构，其特征在于，在所述单晶衬底的下方还包括一P+集电区和一集电极，所述集电极位于所述P+集电区下方。
7.如权利要求6所述的双向耐压的绝缘栅双极晶体管结构，其特征在于，在所述N型外延层上方还包括一P基区、两个多晶硅栅极、两个栅氧化层、两个N+源区、一P+基区、一发射极。
8.如权利要求1所述的双向耐压的绝缘栅双极晶体管结构，其特征在于，所述N型外延层上表面具有Trench结构。
9.如权利要求9所述的双向耐压的绝缘栅双极晶体管结构，其特征在于，所述Trench结构与所述两个P柱区相隔离。
10.如权利要求1所述的双向耐压的绝缘栅双极晶体管结构，其特征在于，所述单晶衬底的两侧凹槽等宽，其总宽度与凹槽间距离相等。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106711189A (zh) * 2017-01-12 2017-05-24 中国科学院微电子研究所 一种超结器件
CN109300978A (zh) * 2018-10-25 2019-02-01 上海超致半导体科技有限公司 一种超结igbt器件结构及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569354A (zh) * 2010-12-16 2012-07-11 三菱电机株式会社 绝缘栅型双极晶体管及其制造方法
CN104241126A (zh) * 2014-09-17 2014-12-24 中航（重庆）微电子有限公司 沟槽型igbt及制备方法
WO2015127673A1 (zh) * 2014-02-28 2015-09-03 电子科技大学 一种双向igbt器件

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569354A (zh) * 2010-12-16 2012-07-11 三菱电机株式会社 绝缘栅型双极晶体管及其制造方法
WO2015127673A1 (zh) * 2014-02-28 2015-09-03 电子科技大学 一种双向igbt器件
CN104241126A (zh) * 2014-09-17 2014-12-24 中航（重庆）微电子有限公司 沟槽型igbt及制备方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106711189A (zh) * 2017-01-12 2017-05-24 中国科学院微电子研究所 一种超结器件
CN109300978A (zh) * 2018-10-25 2019-02-01 上海超致半导体科技有限公司 一种超结igbt器件结构及其制造方法

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