CN106158928B - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing method Download PDFInfo
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- CN106158928B CN106158928B CN201510133571.7A CN201510133571A CN106158928B CN 106158928 B CN106158928 B CN 106158928B CN 201510133571 A CN201510133571 A CN 201510133571A CN 106158928 B CN106158928 B CN 106158928B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 88
- 229910001385 heavy metal Inorganic materials 0.000 claims abstract description 80
- 230000007547 defect Effects 0.000 claims abstract description 50
- 239000013078 crystal Substances 0.000 claims abstract description 48
- 238000009792 diffusion process Methods 0.000 claims description 16
- 239000002245 particle Substances 0.000 claims description 13
- 239000010931 gold Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 230000001133 acceleration Effects 0.000 claims description 6
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 19
- 238000011084 recovery Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 238000009826 distribution Methods 0.000 description 8
- 230000000670 limiting effect Effects 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000002425 crystallisation Methods 0.000 description 4
- 230000008025 crystallization Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 230000002441 reversible effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000956 alloy Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- -1 As shown in Fig. 2 Substances 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000001755 vocal effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/34—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being on the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/2225—Diffusion sources
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
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Abstract
It includes substrate that the embodiment of the present invention, which provides a kind of semiconductor device and its manufacturing method, the semiconductor device, is formed with crystal defect in the superficial layer of the substrate；Wherein, heavy metal atom is imported in the substrate, also, the concentration of the heavy metal atom in the crystal defect is higher than the concentration of the heavy metal atom in other regions in the substrate.According to embodiments of the present invention, it is capable of forming the semiconductor device with high switching speed and low forward voltage Vf.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of semiconductor device and its manufacturing methods.
Background technique
Semiconductor device is widely used in electronic equipment.Fast recovery diode (Fast Recovery Diode,
FRD) be a kind of semiconductor device with the characteristics such as switching characteristic is good, reverse recovery time is short, be mainly used in Switching Power Supply,
In the electronic circuits such as pulse-width modulator (Pulse Width Modulator, PWM), frequency converter, as two pole of high-frequency rectification
Pipe, freewheeling diode or damper diode use.
Fig. 1 shows the structural representation of fast recovery diode documented by patent document 1 (the clear 63-119585A of JP Tetsukai)
Figure is formed with p-type diffusion as shown in Figure 1, having N+ diffusion layer 2 in the N-type substrate 1 of the fast recovery diode in N-type substrate
Layer 3,3a, thus form P-N junction between p type diffused layer and N-type substrate, upper surface and N+ diffusion layer 2 in N-type substrate 1
Lower surface is respectively formed with electrode 8a, 8b, also, the fast recovery diode also has gold diffusion area 6.
In patent document 1, it by forming gold diffusion area 6, and the depth and shape of control p type diffused layer, can drop
Reverse recovery time Trr, forward voltage Vf and the reverse leakage current Ir of low fast recovery diode.
It should be noted that the above description of the technical background be intended merely to it is convenient to technical solution of the present invention carry out it is clear,
Complete explanation, and facilitate the understanding of those skilled in the art and illustrate.Cannot merely because these schemes of the invention
Background technology part is expounded and thinks that above-mentioned technical proposal is known to those skilled in the art.
Summary of the invention
But inventors have found that in patent document 1, the gold atom even concentration in gold diffusion area 6, this will lead to electricity
Resistance between pole 8a and 8b increases, to increase forward voltage Vf, not only improves switching speed and therefore, it is very difficult to reach, but also reduces
The effect of forward voltage Vf.
The embodiment of the present invention provides a kind of semiconductor device and its manufacturing method, is formed in the superficial layer of semiconductor substrate
Crystal defect, adjustment heavy metal concentration distribution, can either improve the switching speed of semiconductor device, and can reduce forward voltage
Vf。
According to the embodiment of the present application in a first aspect, providing a kind of semiconductor device, the semiconductor device includes substrate,
Crystal defect is formed in the superficial layer of the substrate；Wherein, heavy metal atom, also, the knot are imported in the substrate
The concentration of the heavy metal atom in brilliant defect is higher than the concentration of the heavy metal atom in other regions in the substrate.
According to the second aspect of the embodiment of the present application, wherein the crystal defect is formed in opposite two of the substrate
The superficial layer on a surface.
According to the third aspect of the embodiment of the present application, wherein the crystal defect is formed by particle-beam exposure, and
And the crystal defect is formed in out of, the substrate surface plays 0.5 micron -30 microns depth bounds.
According to the fourth aspect of the embodiment of the present application, wherein in the area for being imported with the heavy metal atom of the substrate
In domain, the concentration range of heavy metal atom is 1 × 1015atom/cm3-1×1018atom/cm3。
According to the 5th of the embodiment of the present application the aspect, wherein the semiconductor device further includes being formed in the crystallization to lack
The electrode on sunken surface.
According to the 6th of the embodiment of the present application the aspect, wherein the heavy metal atom is gold atom (Au) or pt atom
(Pt)。
According to the 7th of the embodiment of the present application the aspect, a kind of manufacturing method of semiconductor device is provided, which comprises
Crystal defect is formed in the superficial layer of substrate；
Heavy metal atom is imported into the substrate；
Wherein, the concentration of the heavy metal atom in the crystal defect be higher than the substrate in other regions it is described
The concentration of heavy metal atom.
According to the eighth aspect of the embodiment of the present application, wherein particle ray is irradiated on the surface of Xiang Suoshu substrate, to be formed
State crystal defect.
According to the 9th of the embodiment of the present application the aspect, wherein irradiating acceleration energy used by the particle ray is
3MeV-30MeV, the exposure dose of the particle ray are 1 × 1010atom/cm2-1×1013atom/cm2。
According to the tenth of the embodiment of the present application the aspect, wherein importing the heavy metal atom in Xiang Suoshu substrate includes:
The diffusion source of the heavy metal atom is formed on opposite two surface of the substrate or a surface；And
It is diffused into the heavy metal atom in the diffusion source in the substrate.
The beneficial effects of the present invention are: the concentration of the heavy metal atom in the crystal defect of substrate surface layer is higher than substrate
In other regions heavy metal atom concentration, thereby, it is possible to form partly leading with high switching speed and low forward voltage Vf
Body device.
Referring to following description and accompanying drawings, only certain exemplary embodiments of this invention is disclosed in detail, specifies original of the invention
Reason can be in a manner of adopted.It should be understood that embodiments of the present invention are not so limited in range.In appended power
In the range of the spirit and terms that benefit requires, embodiments of the present invention include many changes, modifications and are equal.
The feature for describing and/or showing for a kind of embodiment can be in a manner of same or similar one or more
It uses in a other embodiment, is combined with the feature in other embodiment, or the feature in substitution other embodiment.
It should be emphasized that term "comprises/comprising" refers to the presence of feature, one integral piece, step or component when using herein, but simultaneously
It is not excluded for the presence or additional of one or more other features, one integral piece, step or component.
Detailed description of the invention
Included attached drawing is used to provide to be further understood from the embodiment of the present invention, and which constitute one of specification
Point, for illustrating embodiments of the present invention, and come together to illustrate the principle of the present invention with verbal description.Under it should be evident that
Attached drawing in the description of face is only some embodiments of the present invention, for those of ordinary skill in the art, is not paying wound
Under the premise of the property made is laborious, it is also possible to obtain other drawings based on these drawings.In the accompanying drawings:
Fig. 1 is the structural schematic diagram of the fast recovery diode of patent document 1；
Fig. 2 is the vertical section schematic diagram of the semiconductor device of embodiment 1；
Fig. 3 is schematic diagram of the concentration along substrate genesis analysis of the heavy metal atom of embodiment 1；
Fig. 4 is a flow diagram of the manufacturing method of the semiconductor device of embodiment 2；
Fig. 5 is the flow diagram that heavy metal atom is imported into substrate of embodiment 2.
Specific embodiment
Referring to attached drawing, by following specification, aforementioned and other feature of the invention be will be apparent.In specification
In attached drawing, only certain exemplary embodiments of this invention is specifically disclosed, which show the portions that can wherein use principle of the invention
Divide embodiment, it will thus be appreciated that the present invention is not limited to described embodiments, on the contrary, the present invention includes falling into appended power
Whole modifications, modification and equivalent in the range of benefit requirement.
In this application, for convenience of description, the surface of the setting anode electrode (anode) of substrate is known as " upper table
The face opposite with " upper surface " of substrate is known as " lower surface " by face ", and "upper" direction refers to as a result, is directed toward from " lower surface "
The direction of " upper surface ", "lower" direction is contrary with "upper", also, "upper" direction and "lower" direction are referred to as longitudinal direction.At this
In application, the setting of "up" and "down" is in contrast, merely to illustrating conveniently, not representing specifically used semiconductor device
Or orientation when manufacturing the semiconductor device.
Embodiment 1
The embodiment of the present invention 1 provides a kind of semiconductor device.Fig. 2 is the vertical section schematic diagram of the semiconductor device, such as Fig. 2
Shown, which includes substrate 201, and crystal defect 202 is formed in the superficial layer of the substrate 201.
In the present embodiment, heavy metal atom, also, the huge sum of money in crystal defect 202 can be imported in substrate 201
The concentration for belonging to atom is higher than the concentration of the heavy metal atom in other regions in substrate 201.
In the present embodiment, which may include electrode 203, which can be formed in crystallization and lack
202 surface is fallen into, and is contacted with the surface of crystal defect 202.
In the present embodiment, the concentration of the heavy metal atom in crystal defect is higher, as a result, electrode 202 and crystal defect
The 202 contact site stable alloy easy to form being made of electrode material and heavy metal atom, so that contact resistance is reduced,
So that reducing the forward voltage Vf of the semiconductor device.For example, the material in electrode 202 is aluminium (Al), heavy metal is golden (Au)
In the case where, in contact site AuAl easy to form2、Au5Al2Etc. stable alloy material.
In the present embodiment, the concentration of the heavy metal atom in crystal defect is higher, forms more deep energy level as a result,
Shorten minority carrier lifetime, to improve the switching speed of the semiconductor device.
In the present embodiment, in the region except the crystal defect 202 of the substrate 201, the concentration of heavy metal atom is lower,
Caused by thereby, it is possible to inhibit due to heavy metal atom resistance substrate increase phenomenon, thus make the semiconductor device have compared with
Low forward voltage Vf.
According to the present embodiment, the switching speed of semiconductor device can either be improved, and can reduce forward voltage Vf.
In the present embodiment, which can be the common semiconductor substrate of semiconductor field, such as silicon substrate etc..
In the present embodiment, which can be formed by particle-beam exposure, for example, the particle ray can
To be electron ray, hydrogen ion ray or helium ion irradiation etc..Irradiating acceleration energy used by the particle ray can be
3MeV-30MeV, the exposure dose of the particle ray can be 1 × 1010atom/cm2-1×1013atom/cm2.As ion is penetrated
The difference of the factors such as type, acceleration voltage, exposure dose and the irradiation time of line is formed by the depth of crystal defect 202
Also different, for example, the crystal defect 202, which can be formed in, plays 0.5 micron -30 microns of depth model from the surface of substrate 201
It encloses in H.
In the present embodiment, which can be respectively formed in the superficial layer on opposite two surface of substrate,
As shown in Fig. 2, crystal defect 202a, 202b can be respectively formed in the superficial layer of the upper and lower surfaces of substrate 201.But
It is that the present embodiment is not limited to this, only can also forms crystal defect in a surface of substrate.
In the present embodiment, heavy metal atom can be along the longitudinal direction of substrate, with two between crystal defect 202a and 202b
Hold the formal distribution that concentration is high, intermediate concentration is low.Fig. 3 be heavy metal atom concentration along substrate genesis analysis schematic diagram,
In Fig. 3, the longitudinal axis represents each region of substrate and the fore-and-aft distance of crystal defect 202b, and horizontal axis represents the dense of heavy metal atom
Degree.As shown in figure 3, heavy metal atom is assembled at crystal defect in crystal defect 202b, thus, heavy metal atom it is dense
Spend it is higher, further away from crystal defect 202b, the concentration of heavy metal atom is lower, heavy metal atom concentration reach minimum with
Afterwards, closer to crystal defect 202a, the concentration of heavy metal atom is higher, and in crystal defect 202a, heavy metal atom occurs again
Aggregation, thus, the concentration of heavy metal atom becomes high value again.As a result, in Fig. 3, the concentration distribution of heavy metal atom is in cross
To " U " font.
In the present embodiment, the concentration of the heavy metal atom of crystal defect 202a and 202b can be identical, but the present embodiment
It is not limited to this, the concentration of the heavy metal atom of the two can also be different.
In the present embodiment, heavy metal atom has concentration distribution profile as shown in Figure 3, as a result, crystal defect 202a
It is higher than the heavy metal atom concentration in other regions in substrate with the heavy metal atom concentration in 202b, is partly led thus it is possible to improve
The switching speed of body device, and can reduce forward voltage Vf.
It should be noted that the concentration distribution profile of Fig. 3 is only citing, in the present embodiment, heavy metal atom can be with
There are other concentration distribution profiles, as long as the concentration of the heavy metal atom in crystal defect can be made to be higher than other regions in substrate
The concentration of heavy metal atom, for example, be arranged in the case where substrate same surface by two electrodes, can substrate with
In the region of electrode contact, keep heavy metal atom concentration higher, also, make the concentration of heavy metal atom in substrate in longitudinal direction
It is upper to increase and monotone decreasing at a distance from the region of the contact.
In the present embodiment, in the region for being imported with heavy metal atom of substrate 201, the concentration range of heavy metal atom
It can be 1 × 1015atom/cm3-1×1018atom/cm3.Certainly, the present embodiment is not limited to this, which can also be with
It is other values.
In the present embodiment, which for example can be gold atom (Au) or pt atom (Pt), but the present embodiment
It is not limited to this, can also be other heavy metal atoms.
In the present embodiment, the quantity of electrode 203 can be two, for example, two electrodes can be respectively anode
(anode) 203a and cathode (cathode) 203b, and two the electrodes 203a and 203b can be located at substrate crystallization and lack
Fall into the surface of 202a and 202b.The semiconductor device can be formed as vertical structure as a result,.But the present embodiment is not limited to
This, the quantity of the electrode can be 1 or 3 or more；Also, have 2 with top electrode in the case where, this 2 or more
Electrode can also be arranged on the same surface of substrate, the semiconductor device can be formed as transverse structure as a result, in addition,
Partial electrode can also be arranged on the same surface of substrate, partial electrode is arranged in opposite two surface of substrate.
In the present embodiment, can also have in the substrate 201 field limiting ring (Field Limiting Ring, FLR),
There are field plate (Field Plate), equal potential belt (Equipotential-Ring, EQR) and channel barrier layer (Channel
Stopper, CS) etc., the field limiting ring, field plate, equal potential belt and channel barrier layer can be used for reducing the table of semiconductor device 200
Face electric field, and prevent from forming parasitic channel in surface of silicon.About field limiting ring, field plate, equal potential belt and buy barrier layer
Illustrate, the prior art can be referred to, this embodiment is not repeated.
Embodiment 2
The embodiment of the present application 2 provides a kind of manufacturing method of semiconductor device, for manufacturing semiconductor described in embodiment 1
Device.
Fig. 4 is a flow diagram of the manufacturing method of the semiconductor device of the present embodiment.As shown in figure 4, the manufacture
Method includes:
S401 forms crystal defect in the superficial layer of substrate；
S402 imports heavy metal atom into substrate.
In addition, in the present embodiment, the manufacturing method of the semiconductor device can also include:
S403, in the table surface forming electrode of crystal defect.
In the present embodiment, the concentration of the heavy metal atom in crystal defect is higher than the heavy metal original in other regions in substrate
The concentration of son, thereby, it is possible to form the semiconductor device with high switching speed and low forward voltage Vf.
It, can be using the method to the surface of substrate irradiation particle ray, to form crystallization in the S401 of the present embodiment
Defect.For example, the particle ray can be electron ray, hydrogen ion ray or helium ion irradiation etc..Irradiate the particle ray institute
The acceleration energy used can be 3MeV-30MeV, and the exposure dose of the particle ray can be 1 × 1010atom/cm2-1×
1013atom/cm2.It, can be with by adjusting factors such as the type of ion irradiation, acceleration voltage, exposure dose and irradiation times
The depth of crystal defect 202 is adjusted, and controls the extent of lattice damage in crystal defect 202.
In the S402 of the present embodiment, it is former can be imported into substrate using the method spread from substrate surface for heavy metal
Son.For example, the diffusion source of heavy metal atom can be arranged in substrate surface, and at a certain temperature, by the regular hour,
Diffuse into heavy metal atom in semiconductor substrate.
It is in the present embodiment, corresponding with the concentration distribution of the semiconductor device structure of Fig. 2 and the heavy metal atom of Fig. 3,
Heavy metal atom can be imported into substrate using the method for Fig. 5.As shown in figure 5, this method comprises:
S501 forms the diffusion source of heavy metal atom on opposite two surface of substrate or a surface；
S502 is diffused into the heavy metal atom in diffusion source in substrate.
In step S501, the diffusion source example of heavy metal atom can be formed on 201 surface of substrate by way of evaporation
Such as, which for example can be the layer gold that thickness range is 50 angstroms -5 microns.Certainly, the present embodiment is without being limited thereto, heavy metal
The generation type in the diffusion source of atom can be other way, and thickness is also possible to other values.
In step S502, at a temperature of the substrate for being provided with diffusion source can be made to be in certain, by certain time, make
Heavy metal atom is diffused into substrate, for example, the temperature can be 750 DEG C -1200 DEG C, which be can be 60 minutes.One
It is that temperature in the case that silicon substrate heavy metal atom is gold, in step S502 can be in substrate in a specific embodiment
It is 750 DEG C, the time can be 60 minutes.
In the present embodiment, the concentration distribution of heavy metal atom shown in Fig. 3 can be reached according to step S501 and S502.
It should be noted that method shown in fig. 5 is only a specific embodiment, the present embodiment is not limited to this,
Heavy metal atom can also be imported into substrate using other methods, as long as the dense of the heavy metal atom in crystal defect can be made
Degree is higher than the concentration of the heavy metal atom in other regions in substrate.
In step S403, electrode can be formed using the common method of semiconductor field, for example, by using evaporated metal
The mode of layer and the graphical metal layer forms electrode, it is, of course, also possible to using other methods.In addition, the formation of electrode
Position can be with the explanation in reference implementation example 1, and details are not described herein again.
According to an embodiment of the present application 2, it is capable of forming the semiconductor device with high switching speed and low forward voltage Vf.
Combining specific embodiment above, invention has been described, it will be appreciated by those skilled in the art that this
A little descriptions are all exemplary, and are not limiting the scope of the invention.Those skilled in the art can be according to the present invention
Spirit and principle various variants and modifications are made to the present invention, these variants and modifications are also within the scope of the invention.
Claims (8)
1. a kind of semiconductor device, which is characterized in that
The semiconductor device includes substrate, and crystal defect is formed in the superficial layer of the substrate, and the crystal defect is formed
Superficial layer in opposite two surface of the substrate；
Wherein, heavy metal atom is imported in the substrate, also, the concentration of the heavy metal atom in the crystal defect
Higher than the concentration of the heavy metal atom in other regions in the substrate,
The semiconductor device further includes the electrode for being formed in the surface of the crystal defect, in the superficial layer and the electrode
Joint portion be formed with AuAl2Or Au5Al2。
2. semiconductor device as described in claim 1, which is characterized in that
The crystal defect is formed by particle-beam exposure, also, the crystal defect is formed in from the substrate surface
Into 0.5 micron -30 microns of depth bounds.
3. semiconductor device as described in claim 1, which is characterized in that
In being imported in the region of the heavy metal atom for the substrate, the concentration range of heavy metal atom is 1 ×
1015atom/cm3-1×1018atom/cm3。
4. semiconductor device as described in claim 1, which is characterized in that
The heavy metal atom is gold atom (Au).
5. a kind of manufacturing method of semiconductor device, which is characterized in that the described method includes:
Crystal defect is formed in the superficial layer of substrate, the crystal defect is formed in opposite two surface of the substrate
Superficial layer；
Heavy metal atom is imported into the substrate；
Wherein, the concentration of the heavy metal atom in the crystal defect is higher than the huge sum of money in other regions in the substrate
Belong to the concentration of atom.
6. the manufacturing method of semiconductor device as claimed in claim 5, which is characterized in that
Particle ray is irradiated to the surface of the substrate, to form the crystal defect.
7. the manufacturing method of semiconductor device as claimed in claim 6, which is characterized in that
Irradiating acceleration energy used by the particle ray is 3MeV-30MeV, the exposure dose of the particle ray is 1 ×
1010atom/cm2-1×1013atom/cm2。
8. the manufacturing method of semiconductor device as claimed in claim 5, which is characterized in that imported in Xiang Suoshu substrate described heavy
Metallic atom includes:
The diffusion source of the heavy metal atom is formed on opposite two surface of the substrate or a surface；And
It is diffused into the heavy metal atom in the diffusion source in the substrate.
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