CN104716174B

CN104716174B - Semiconductor devices and the method being used for producing the semiconductor devices

Info

Publication number: CN104716174B
Application number: CN201410809118.9A
Authority: CN
Inventors: 根本道生; 吉村尚
Original assignee: Fuji Electric Co Ltd
Current assignee: Fuji Electric Co Ltd
Priority date: 2009-11-02
Filing date: 2010-11-02
Publication date: 2018-08-31
Anticipated expiration: 2030-11-02

Abstract

In n^‑P anode layers (2) are formed in one main surface of drift layer (1).In n^‑Impurity concentration is formed in another main surface of drift layer (1) is more than n^‑The n of drift layer (1)⁺Cathode layer (3).Anode electrode (4) is formed on the surface of p anode layers (2).In n⁺Cathode electrode (5) is formed on the surface of cathode layer (3).In n^‑Net dopant concentration is formed in drift layer (1) to be more than the body impurity concentration of chip and be less than n⁺The wide buffering area of N-shaped (6) of the body impurity concentration of cathode layer (3).n^‑The electricalresistivityρ of drift layer (1)₀Relative to rated voltage V₀Meet 0.12V₀≤ρ₀≤0.25V₀.The net dopant concentration total amount of wide buffering area (6) is greater than or equal to 4.8 × 10¹¹Atom/cm²And it is less than or equal to 1.0 × 10¹²Atom/cm²。

Description

Semiconductor devices and the method being used for producing the semiconductor devices

The application is entitled " semiconductor devices and the method being used for producing the semiconductor devices ", international filing date For on November 2nd, 2010, application No. is the invention of 201080049553.6 (international application no PCT/JP2010/069528) is special The divisional application of profit application.

Technical field

The present invention relates to high speed operation and the semiconductor devices with low-loss and soft recovery characteristics (such as diode or Igbt (IGBT)) and method for manufacturing the semiconductor devices.

Background technology

Power semiconductor is used for power conversion apparatus (such as converter and inversion with high efficiency and low-power consumption Device), and be essential for control electric rotating machine or servo motor.Power control device require low-loss, low-power consumption, High speed operation, high efficiency and the characteristic without environmental problem (that is, being not adversely affected to the external world).In order to meet with low The demand of loss and efficient power control device, it has been proposed that there is the diode of wide buffer structure to be used as and be used for power control The diode of the improved type of device processed.Wide buffer structure refers to wherein n^-The impurities concentration distribution of drift layer is in n^-Drift layer Adjacent central portion with peak value (local maximum) and with being tilted with towards anode and cathode including impurities concentration distribution Direction decline region wide buffering area structure.

Diode with wide buffer structure allows to reduce the emitter injection efficiency of the relevant technologies and in high speed operation (for example, carrier frequency：More than or equal to 5kHz) in realize soft recovery characteristics and anti-oscillation effect, the realization is in service life It is unapproachable in distributed controll technology.

Have been presented for the method for using hydrogen to cause donor (hydrogen-induced donor) has wide buffering as manufacture The method of the diode of structure.In the method, floating region (FZ) body chip proton (hydrogen ion, H⁺) irradiate so that proton H⁺It arrives Up to passing through the unapproachable n of general N-shaped doped chemical (phosphorus or arsenic) ion implantation^-Crystalline substance is consequently formed in the depth of drift layer Lattice defect, and be then heat-treated.In the method, with the irradiation of proton and heat treatment so that donor is (for example, be known as The donor that hydrogen causes donor or mutually associates with hydrogen) by including proton H⁺Defects Complex proton H in the wafer⁺Range Rp It is formed about (for example, with reference to following patent document 1 (paragraph 0020 and 0021) and following patent document 2 (abstract)).In addition, Propose wherein oxygen be introduced into chip and with hydrogen cause donor combination, be consequently formed the wide buffering area of high concentration method (for example, with reference to Following patent document 3 (paragraph 0011)).

Generally, for silicon (Si) power semiconductor, the FZ chip cheaper than epitaxial wafer is used from economic angle To manufacture IGBT or diode.Additionally, it is known that neutron beam is used to irradiate silicon wafer to use nuclear transmutation that silicon is converted into as stabilization The phosphorus (P) of isotope, thus formation exists as the method for the phosphorus of impurity in chip (hereinafter referred to as neutron exposure chip) It is effective when being evenly distributed impurity in chip.The change in resistance of neutron exposure chip (for example, 6 inches chip) is about ± 8%.

As the method for forming neutron exposure chip, it has been proposed that by with proton H⁺Irradiation and heat treatment by matter Sub- H⁺It is changed to donor and concentration is more than to the donor injection n base area (n of the chip before neutron exposure^-Drift layer) method (for example, with reference to following patent document 4).

Reference listing

Patent document

Patent document 1：Japanese Patent Application Laid-Open (JP-A) No.2003-318412

Patent document 2：International Publication No.WO2007/055352

Patent document 3：JP-A No.2007-266233

Patent document 4：JP-A No.2008-91853

The disclosure of invention

The problem to be solved in the present invention

However, introducing the impurity for being mixed with raw gas by ion implanting or thermal diffusion according to the relevant technologies In the FZ chips of element (gas doping), change in resistance is more than the change in resistance of neutron exposure chip, and about 6 inches ± 12% in chip.Big change in resistance directly affects the variation of breakdown voltage.Therefore, breakdown voltage variation is reexamined Decline be necessary.In the case of the semiconductor devices with non-punch-through, the breakdown voltage V of semiconductor devices_B(V) It can be indicated by following formula 1.

[expression formula 1]

V_B=W²/(0.29ρ₀)

In expression formula 1, W is the width (μm) of depletion layer, and ρ₀It is the resistivity (body resistivity) of silicon wafer.Above-mentioned In expression formula 1, for example, in the semiconductor devices with non-punch-through manufactured using the FZ chips of gas doping, work as electricity Resistance rate ρ₀Variation be ± 12% when, breakdown voltage V_BVariation be also 12%.Other than breakdown voltage, the change of switching characteristic Change is also 12%.When the variation of switching characteristic is more than or equal to 12%, guarantee is likely to occur problem to the operation of the device. Change in resistance is decreased below 12% by one of the method that the variation of switching characteristic is reduced to less than or equal to 12%.Example Such as, as described above, in order to reduce change in resistance, using its resistivity by the way that change in resistance is decreased below ± 12% Neutron exposure is effective come the neutron exposure chip controlled.

However, when body resistivity when adjusting, needs atomic pile by neutron exposure, and establish and safeguard that atom is anti- Heap is answered to need huge cost.Therefore, it is economically impractical to possess atomic pile for a Semiconductor Manufacturing Company.It is necessary to The external agency with atomic pile is asked to adjust body resistivity.However, there are a few external mechanism, including external machine Structure.Increase in demand to interior or industrial power semiconductor, and only external agency's processing power semiconductor is difficult.Separately Outside, processing cost is high.Therefore, the breakdown voltage variation that can reliably reduce or solve semiconductor devices or switching characteristic are found The method of variation is desirable as the method in addition to the method for using neutron exposure.

When semiconductor devices using the FZ chips of gas doping without the use of neutron exposure chip come when manufacturing, with chip Diameter become greater than 6 inches, the variation of slice resistivity increases.Therefore, it is technically difficult to change in resistance being reduced to Less than ± 12%.In addition, when using cutting krousky (CZ) chip come when manufacturing semiconductor devices, manufacture be initially it is uniform and N-shaped chip with high resistivity is difficult.Therefore, it is tired change in resistance to be decreased below ± 12% using CZ chips Difficult.Therefore it provides being influenced even if changing on breakdown voltage when the change in resistance of FZ chips is greater than or equal to ± 12% Smaller semiconductor devices with novel device structure and the method for manufacturing the semiconductor devices are desirable.

As removal breakdown voltage variation method, patent document 3 disclose using ion implanting come introduce proton and It is treated with heat such that proton is diffused into entire n at 500 DEG C^-Thus drift layer controls n^-The method of the impurity concentration of drift layer. However, in fact, the number of the donor mutually to associate with hydrogen is removed at a temperature of greater than or equal to 550 DEG C due to having obtained instruction According to, therefore control wide scope (such as, entire n^-Drift layer) in impurity concentration be difficult.Specifically, control has height Low concentration n needed for the semiconductor devices of breakdown voltage^-The impurity concentration of drift layer is extremely difficult.Therefore, when manufacture has When having the semiconductor devices of high-breakdown-voltage, reduce breakdown voltage even if being obtained when application technology disclosed in Patent Document 3 The effect of variation is also difficult.

The present invention has been made to solve the above-mentioned problems, and the object of the present invention is to provide can reduce breakdown potential The method of the semiconductor devices and manufacture semiconductor devices of the variation of pressure and the variation of switching characteristic.In addition, the mesh of the present invention Be, provide the semiconductor devices that can reduce manufacturing cost and manufacture semiconductor devices method.

The means used to solve the problem

It to solve the above-mentioned problems and achieves the object of the present invention, according to an aspect of the present invention, provides one kind and partly lead Body device, the semiconductor devices include：First semiconductor layer of the first conductive type；A main table in the first semiconductor layer is set On face and impurity concentration is more than the second semiconductor layer of the second conductive type of the first semiconductor layer；It is arranged in the first semiconductor layer In another main surface and impurity concentration is more than the third semiconductor layer of the first conductive type of the first semiconductor layer；And setting is the In semi-conductor layer and impurity concentration is more than the local maximum of the first semiconductor layer and impurities concentration distribution and is less than the second half The wide buffering area of the first conductive type of conductor layer and the impurity concentration of third semiconductor layer.The net dopant concentration total amount of wide buffering area More than or equal to 4.8 × 10¹¹Atom/cm²And it is less than or equal to 1.0 × 10¹²Atom/cm².The electricalresistivityρ of first semiconductor layer₀ (Ω cm) is relative to rated voltage V₀(V) meet 0.12V₀≤ρ₀≤0.25V₀。

The net dopant concentration total amount of wide buffering area can be greater than or equal to 5.2 × 10¹¹Atom/cm²And less than or equal to 1.0 × 10¹²Atom/cm², and the electricalresistivityρ of the first semiconductor layer₀Relative to rated voltage V₀(V) 0.133V can be met₀≤ρ₀≤ 0.25V₀。

Multiple wide buffering areas may be provided in the first semiconductor layer.

The ratio γ of the sum of width of multiple wide buffering areas and the width of the first semiconductor layer, when being applied with level and breakdown The ratio η of the sum of decline of electric field strength of multiple wide buffering areas when the equal reverse biased of voltage and critical electric field strength, And as the first semiconductor layer substrate the measured value of donor concentrations and the deviation ratio α of standard value can meet 4 α (γ/η)/ [(2-α)(2+α)]<α。

First semiconductor layer can be FZ silicon substrates.

It to solve the above-mentioned problems and achieves the object of the present invention, according to another aspect of the present invention, provides a kind of half Conductor device, the semiconductor devices include：The drift layer of the first conductive type；It is arranged in a main surface of drift layer and impurity Concentration is more than the base layer of the second conductive type of drift layer；Be arranged in a main surface of drift layer to be contacted with base layer and Impurity concentration is more than the emitter layer of the first conductive type of base layer；It is contacted with drift layer, base layer and emitter layer exhausted Velum；The gate electrode adjacent with drift layer, base layer and emitter layer across insulating film；Another master in drift layer is set On surface and impurity concentration is more than the collector layer of the second conductive type of drift layer；And it is arranged in drift layer and impurity concentration Be less than base layer and the impurity concentration of collector layer more than the local maximum of drift layer and impurities concentration distribution first is led The wide buffering area of electric type.The net dopant concentration total amount of wide buffering area is greater than or equal to 4.8 × 10¹¹Atom/cm²And it is less than or equal to 1.0×10¹²Atom/cm², and the electricalresistivityρ of drift layer₀(Ω cm) is relative to rated voltage V₀(V) meet 0.12V₀≤ρ₀≤ 0.25V₀。

The net dopant concentration total amount of wide buffering area can be greater than or equal to 5.2 × 10¹¹Atom/cm²And less than or equal to 1.0 × 10¹²Atom/cm², and the electricalresistivityρ of drift layer₀(Ω cm) is relative to rated voltage V₀(V) 0.133V can be met₀≤ρ₀≤ 0.25V₀。

Multiple width buffering areas may be provided in drift layer.

The sum of width of multiple width buffering areas with the ratio γ of the width of drift layer, when being applied with level and breakdown voltage phase Deng reverse biased when ratio η, Yi Jicheng with critical electric field strength of the sum of the decline of electric field strength of multiple wide buffering areas It can meet 4 α (γ/η)/[(2- α) (2+ α)] for the measured value of the donor concentrations of the substrate of drift layer and the deviation ratio α of standard value< α。

It may additionally include according to the semiconductor devices of above-mentioned aspect and buffered with drift layer or width in a main surface of substrate The first conductive type field barrier layer that area contacts and contacted on the other major surface with collector layer.

It may also include the drift layer or wide slow in a main surface side with substrate according to the semiconductor devices of above-mentioned aspect Rush the first conductive type field barrier layer that area contacts and contacted on the other major surface with collector layer.Drift layer, wide buffering The net dopant concentration total amount of area and field barrier layer can be greater than or equal to 1.2 × 10¹²Atom/cm²And less than or equal to 2.0 × 10¹²Atom/cm²。

Drift layer can be FZ silicon substrates.

It to solve the above-mentioned problems and achieves the object of the present invention, in accordance with a further aspect of the present invention, provides a kind of system The method of manufacturing semiconductor device, the semiconductor devices include：First semiconductor layer of the first conductive type；It is arranged in the first semiconductor In one main surface of layer and impurity concentration is more than the second semiconductor layer of the second conductive type of the first semiconductor layer；Setting is the In another main surface of semi-conductor layer and impurity concentration is more than the third semiconductor layer of the first conductive type of the first semiconductor layer； And it is arranged in the first semiconductor layer being inserted between the second semiconductor layer and third semiconductor layer and impurity concentration is more than the The local maximum of semi-conductor layer and impurities concentration distribution is less than the second semiconductor layer and the impurity of third semiconductor layer is dense The wide buffering area of the first conductive type of degree.This method includes：The second half are formed in a main surface of the first semiconductor layer to lead First forming step of body layer；And it is irradiated on the first semiconductor layer with hydrogen ion in the projected range to the first semiconductor layer The second semiconductor layer and more than or equal to 300 DEG C and less than or equal to 550 DEG C at a temperature of be heat-treated, thus The second forming step of wide buffering area is formed in the first semiconductor layer.In the second forming step, in the first semiconductor layer It forms total net dopant concentration and is greater than or equal to 4.8 × 10¹¹Atom/cm²And it is less than or equal to 1.0 × 10¹²Atom/cm²Width it is slow Rush area, and the electricalresistivityρ of the first semiconductor layer₀Relative to rated voltage V₀(V) meet 0.12V₀≤ρ₀≤0.25V₀。

It may also include according to the method for the manufacture semiconductor devices of above-mentioned aspect：Before the first forming step, higher than Or equal to 1000 DEG C at a temperature of be heat-treated in oxidizing atmosphere to introduce oxygen into the introducing step of the first semiconductor layer.

In being introduced into step, concentration can be greater than or equal to 1 × 10¹⁶Atom/cm³Oxygen introduce the first semiconductor layer.

It to solve the above-mentioned problems and achieves the object of the present invention, according to another aspect of the invention, provides a kind of system The method of manufacturing semiconductor device, the semiconductor devices include：First semiconductor layer of the first conductive type；It is arranged in the first semiconductor In one main surface of layer and impurity concentration is more than the second semiconductor layer of the second conductive type of the first semiconductor layer；Setting is the In another main surface of semi-conductor layer and impurity concentration is more than the third semiconductor layer of the first conductive type of the first semiconductor layer； And it is arranged in the first semiconductor layer and impurity concentration is more than the local maxima of the first semiconductor layer and impurities concentration distribution Wide buffering area of the value less than the first conductive type of the impurity concentration of the second semiconductor layer and third semiconductor layer.This method is included in Ratio to the first semiconductor layer will be in the projected range of the part of the position depth for the third semiconductor layer that formed by subsequent step Another main surface of the first semiconductor layer is irradiated with hydrogen ion and more than or equal to 300 DEG C and less than or equal to 550 DEG C At a temperature of be heat-treated, thus form the second forming step of wide buffering area in the first semiconductor layer.Step is formed second In rapid, total net dopant concentration is formed in the first semiconductor layer and is greater than or equal to 4.8 × 10¹¹Atom/cm²And it is less than or equal to 1.0×10¹²Atom/cm²Wide buffering area, and the electricalresistivityρ of the first semiconductor layer₀Relative to rated voltage V₀(V) meet 0.12V₀≤ρ₀≤0.25V₀。

Before may additionally include the first forming step according to the method for the manufacture semiconductor devices of above-mentioned aspect, being higher than or It is heat-treated in oxidizing atmosphere to introduce oxygen into the introducing step of the first semiconductor layer at a temperature of equal to 1000 DEG C.

It, can be by being formed hydrogen cause donor with hydrionic irradiation, wide buffering area being consequently formed in the second forming step.

First semiconductor layer can be FZ silicon substrates.

According to the present invention, wide setting buffers are in electricalresistivityρ₀(Ω cm) is relative to rated voltage V₀(V) meet 0.12V₀≤ ρ₀≤0.25V₀The first semiconductor layer (drift layer) in.The net dopant concentration total amount of wide buffering area is greater than or equal to 4.8 × 10¹¹ Atom/cm²And it is less than or equal to 1.0 × 10¹²Atom/cm².By this method, even if the change of the resistivity when the first semiconductor layer When changing about ± 12%, it is also possible to reduce the variation of the breakdown voltage of semiconductor devices according to the resistivity of the first semiconductor layer And the range changed.Furthermore, it is possible to reduce the change of the switching characteristic of semiconductor devices according to the resistivity of the first semiconductor layer The range changed and changed.

In addition, when forming multiple wide buffering areas in drift layer, space-charge region can be finely controlled during switch Extension.

Formed in a main surface of the first semiconductor layer after the second semiconductor layer (anode/base layer), to than It is irradiated with hydrogen ion in the projected range of the part of the second semiconductor layer or third semiconductor layer depth that are formed in the subsequent process A main surface for first semiconductor layer or another main surface, and more than or equal to 300 DEG C and less than or equal to 550 DEG C At a temperature of be heat-treated.By this method, wide buffering area is formed in the first semiconductor layer (drift layer) under these conditions. In this case, the electricalresistivityρ of the first semiconductor layer₀(Ω cm) is relative to rated voltage V₀(V) meet above-mentioned condition.By this method, Even if when the variation of the resistivity of the first semiconductor layer is about ± 12%, it is also possible to reduce the breakdown voltage of semiconductor devices The range changed according to the variation of the resistivity of the first semiconductor layer.Furthermore, it is possible to which the switch for reducing semiconductor devices is special The range that property changes according to the variation of the resistivity of the first semiconductor layer.

In addition, when irradiating substrate with hydrogen ion in the second forming step, the electrons and holes in wide buffering area can be prevented The reduction of mobility.

In the present invention, FZ chips can be used to be manufactured with low cost the semiconductor devices with wide buffer structure.

Invention effect

According to the present invention, the effect of the variation of the variation and switching characteristic that reduce breakdown voltage can be obtained.In addition, can obtain Reduce the effect of manufacturing cost.

Brief description

[Fig. 1] Fig. 1 is the diagram of the structure and net dopant concentration distribution that show semiconductor devices according to first embodiment.

[Fig. 2] Fig. 2 is the diagram for showing to manufacture the technique of semiconductor devices according to first embodiment.

[Fig. 3] Fig. 3 is the diagram for showing to manufacture the technique of semiconductor devices according to first embodiment.

[Fig. 4] Fig. 4 is the performance plot for showing the relationship between the body resistivity of semiconductor devices and breakdown voltage.

[Fig. 5] Fig. 5 is the spy for showing the relationship between the body resistivity of semiconductor devices and the varying width of breakdown voltage Property figure.

[Fig. 6] Fig. 6 is the diagram for showing to be distributed according to the structure and net dopant concentration of the semiconductor devices of the relevant technologies.

[Fig. 7] Fig. 7 is the diagram of the structure and net dopant concentration distribution that show semiconductor devices according to second embodiment.

[Fig. 8] Fig. 8 is the diagram of the structure and net dopant concentration distribution that show semiconductor devices according to third embodiment.

[Fig. 9] Fig. 9 is the diagram for showing to manufacture the technique of semiconductor devices according to third embodiment.

[Figure 10] Figure 10 is to show to manufacture another exemplary diagram of the technique of semiconductor devices according to third embodiment.

[Figure 11] Figure 11 is to show to manufacture another exemplary diagram of the technique of semiconductor devices according to third embodiment.

[Figure 12] Figure 12 is to show to manufacture another exemplary diagram of the technique of semiconductor devices according to third embodiment.

[Figure 13] Figure 13 is to show to be shown according to what the structure and net dopant concentration of the semiconductor devices of fourth embodiment were distributed Figure.

[Figure 14] Figure 14 is net dopant concentration distribution and the internal electric intensity for showing drift layer when a reverse bias is applied The performance plot of relationship between distribution.

For realizing the optimal mode of the present invention

Hereinafter, the semiconductor devices and its system of exemplary embodiment according to the present invention will be described in detail with reference to the attached drawings Make method.The present invention is not limited to following embodiments, without departing from the spirit and scope of the present invention.In the following description, a kind of Conduction type is N-shaped, and another conduction type is p-type.However, obtaining identical effect type is reversed.

(first embodiment)

It will be described below wherein using proton ion (H⁺) irradiate silicon wafer and in n^-Wide buffer structure is formed in drift layer To control the n in silicon wafer^-The diode of the impurity concentration of drift layer and the method for manufacturing diode.

Fig. 1 is the diagram of the structure and net dopant concentration distribution that show semiconductor devices according to first embodiment.Such as exist Shown in the sectional view (upside of paper) of semiconductor devices in Fig. 1, formed according to the on n-type semiconductor substrate (chip) The diode of one embodiment.The body resistivity of chip is ρ₀(Ωcm).P anode layers 2 are formed in a main surface of chip. N is formed in another main surface of chip⁺Cathode layer 3.Semiconductor substrate is inserted in p anode layers 2 (the second semiconductor layer) and n⁺Cathode layer Part (the first semiconductor layer) between 3 (third semiconductor layers) is n^-Drift layer 1.Anode is formed on the surface of p anode layers 2 Electrode 4.In n⁺Cathode electrode 5 is formed on the surface of cathode layer 3.

In Fig. 1, such as in the performance plot for showing the relationship between the distance away from anode electrode 4 and net dopant concentration (log) Shown in (downside of paper), n^-The net dopant concentration of drift layer 1 has wherein in n^-The centre of drift layer 1 nearby for peak value and According to specific gradient towards p anode layers 2 and n⁺The mountain shape distribution curve that cathode layer 3 declines, and there is wherein net dopant concentration Higher than n^-The mound shape region of the net dopant concentration of drift layer 1.N-shaped mound shape region is referred to as wide buffering area 6.Wide buffering area 6 it is miscellaneous The local maximum of matter concentration distribution is less than n⁺The impurity concentration of cathode layer 3 and p anode layers 2.That is, wide buffering area 6 is arranged in n^-Drift It moves in layer 1, and its net dopant concentration is more than the body impurity concentration of chip and is less than n⁺The impurity of cathode layer 3 and p anode layers 2 is dense Degree.

The structure of diode according to the present invention has following two main points：The body resistivity ρ of semiconductor substrate (chip)₀ The rated voltage V of (Ω cm) relative to diode₀(V) meet following formula 2；And the effective dose of wide buffering area 6 is (same The net dopant concentration total amount of layer) it is greater than or equal to 4.8 × 10¹¹Atom/cm²And it is less than or equal to 1.0 × 10¹²Atom/cm²。

[expression formula 2]

0.12V₀≤ρ₀≤0.25V₀

Fig. 2 and 3 is the diagram for showing to manufacture the technique of semiconductor devices according to first embodiment.It can be by with proton H⁺ 11 are irradiated (referring to Fig. 2 (c) and 3 (c))) and to including the p anode layers 2 formed on one of its major and anode The chip of electrode 4 is heat-treated, and wide buffering area 6 is formed from anode electrode.It is manufactured next, will be described in detail with reference to figure 2 and 3 The technique of semiconductor devices according to first embodiment.In the present embodiment, for example, description manufacture is had ruler shown in FIG. 1 Very little and net dopant concentration diode (rated voltage：V₀=1200V；And rated current：150A) the case where.

Fig. 2 (a) shows the main manufacturing processes of diode to 2 (g) in order.First, prepare resistivity be 144 Ω cm extremely 300 Ω cm are (for example, 150 Ω cm (phosphorus concentrations：2.0×10¹³Atom/cm³) and thickness be about 500 μm FZ chips 10 as brilliant Piece (semiconductor substrate).FZ chips 10 are used as the first semiconductor layer.Hereinafter, the impurity concentration of FZ chips 10 is referred to as body Concentration, and its resistivity is referred to as body resistivity (Fig. 2 (a)).When resistivity is more than 1 Ω cm, electricalresistivityρ (Ω cm) and donor Concentration N (atoms/cm³) between relationship by ρ=4.596 × 10¹⁵/ N is indicated.

Then, standard diode manufacturing process is executed to be formed as the p anode layers 2 of the second semiconductor layer, to side Edge end on structure part includes protection ring (not shown), insulating film 12 and anode electricity in a main surface of FZ chips 10 Pole 4.The impurity concentration of p anode layers 2 is such as 5 × 10¹⁶Atom/cm³, and its junction depth away from surface is such as 3 μm.In addition, Anode electrode 4 (is hereinafter referred to as Al-Si by the aluminium alloy of the aluminium silicon (AlSi) of the silicon such as including about 1wt% etc (1%)) it is made (Fig. 2 (b)).

Then, with the proton H accelerated by cyclotron⁺The surface of 11 irradiation anode electrodes 4.At this point, convolution accelerates The accelerating potential of device is such as 7.9MeV, and proton H⁺11 dosage is such as 2.0 × 10¹²Atom/cm².In addition, being inhaled using aluminium Device (not shown) is received, and adjusts the thickness of the aluminium absorber with proton H⁺11 irradiate FZ chips 10 by aluminium absorber, with Make proton H⁺The range on 11 surfaces away from FZ chips 10 is 60 μm.In Fig. 2 (c), because with H⁺11 irradiate and are generated in FZ chips Crystal defect 13 by X indicate (Fig. 2 (c)).

Then, for example, being heat-treated up to 1 hour in nitrogen atmosphere (it may include hydrogen) to make up crystalline substance at 350 DEG C Volume defect 13.By this method, n-type high concentration region is formed with from the Depth Expansion on 60 μm of the surface away from chip to about ± 20 μm.It is high Concentration area is wide buffering area 6 (in two dotted lines) (Fig. 2 (d)).

Then, another main surface of FZ chips 10 (rear surface of FZ chips 10) is ground with wet etching 30 so that FZ chips 10 have desired thickness.In this stage, as rated voltage V₀For 1200V when, the thickness of FZ chips 10 is usually 100 μm in the range of 160 μm.In the first embodiment, in this stage, the thickness of FZ chips 10 is 120 μm (Fig. 2 (e)).

Then, the p-type impurity ion implanting of such as phosphonium ion etc is ground to the FZ chips 10 with wet etching 30 Surface (rear surface).In the case, accelerating potential is such as 50keV, and the dosage of phosphorus is such as 1 × 10¹⁵Atom/cm² (impurity concentration：1×10¹⁹Atom/cm³) (Fig. 2 (f)).Then, for example, YAG second harmonic lasers device will be swashed using the method for double pulse measurement Beam emissions are to ion implanting surface.The p-type impurity ion (phosphonium ion such as injected) of injection is by laser irradiation come electric shock It is living, and formed the third semiconductor layer (Fig. 2 (g)) as n+ cathode layers 3.

The method of double pulse measurement makes multiple pulse laser beams from multiple laser irradiation devices continuously be irradiated to each laser The irradiation sequential of beam irradiation area, these pulse laser beams offsets with one another scheduled delay.In JP-A-2005-223301 Disclose the method for double pulse measurement.When laser beam by the method for double pulse measurement come when irradiating, the total energy density of each laser beam irradiation area is Such as 3J/cm².In addition, dipulse delay time is such as 300nsec (nanosecond).

Finally, metal material is deposited on n by the order of aluminium, titanium, nickel and gold⁺With formation and n on the surface of cathode layer 3⁺Cathode The cathode electrode 5 of the surface Ohmic contact of layer 3.By this method, diode is completed.P anode layers 2 in FZ chips 10 and n⁺Cathode Semiconductor substrate between layer 3 is partially in n^-In drift layer 1.Performance plot (g-1) shown on the right side of Fig. 2 (g) be with The corresponding net dopant concentration distribution curve of sectional view of diode shown in Fig. 2 (g).

Additionally, it is preferred that increasing following manufacturing process before diode manufacturing process starts.First, although in the accompanying drawings not It shows, but phosphosilicate glass is applied on FZ chips 10 shown in Fig. 2 (a), and by pushing away trap (drive-in) work Skill from two diffusion into the surfaces of chip and introduces phosphorus and oxygen up to 10 hours at 1300 DEG C.Then, a main table of chip is wiped off Phosphorus-diffused layer on face, and then mirror-finished.It then, only will maximum agent corresponding with solid solubility at 1300 DEG C Amount is 1 × 10¹⁸Atom/cm³Oxygen introduce chip another main surface (for example, rear surface), wherein phosphorus-diffused layer is consequently formed Impurity concentration (surface concentration：1×10²⁰Atom/cm³；And depth：About 80 μm) be more than chip concentration chip.Then, make Diode manufacturing process (technique after Fig. 2 (b)) is carried out with the chip.It is preferred that the reason of increasing above-mentioned technique is as follows.Such as Disclosed Patent Document 3, formation and impurity concentration are more than the phosphorus-diffused layer conduct of the concentration of chip on the rear surface of the wafer Layer for the impurity for absorbing such as heavy metal etc, and the oxygen concentration on the surface from anode layer is mixed to the net of wide buffering area The peak value (hereinafter referred to as peak concentration) of miscellaneous concentration is (that is, proton H⁺Range Rp) increase, this allows to prevent wide buffering area In electrons and holes mobility because with proton H⁺11 irradiate and decline.

When using chip (the FZ chips such as using polysilicon as raw material) comprising low concentration oxygen, can higher than Or equal to 1000 DEG C at a temperature of executed in wrapping oxygen containing atmosphere and push away trap technique or thermal oxidation technology.The reason is that, oxygen is in silicon It is permeated and is spread by being heat-treated in substrate, and the oxygen concentration of chip increases.In the case, the concentration of oxygen distribution is more than Or it is equal to 1 × 10¹⁶Atom/cm³And it is less than or equal to 1 × 10¹⁷Atom/cm³, which is by Secondary Ion Mass Spectrometry (SIMS) The sufficiently high impurity concentration for measuring to detect, and can obtain and prevent under the mobility of the electrons and holes in wide buffering area Identical effect drops.By heat treatment at a temperature of greater than or equal to 1300 DEG C, oxygen concentration can be greater than or equal to 1 × 10¹⁸ Atom/cm³.However, when oxygen concentration is more than above-mentioned value, oxygen deposition may be generated or oxygen causes defect.It is therefore preferable that oxygen concentration is small In or equal to 1 × 10¹⁸Atom/cm³.That is, being preferred from the oxygen concentration on the surface of anode layer to the peak concentration of wide buffering area (that is, proton H⁺Range Rp) be greater than or equal to 1 × 10¹⁶Atom/cm³And it is less than or equal to 1 × 10¹⁸Atom/cm³。

In addition, including when by with proton H⁺Irradiation chip come the complex defect in hole that is formed when introducing the hydrogen into chip with Pass through the donor active part that principal current flows in the semiconductor device wherein together and marginal end binding of introduced oxygen Structure is formed in part.Equally, adjacent edge end on structure beneath portions form the phosphorus expansion that impurity concentration is more than the concentration of N-shaped chip Dissipate layer.Therefore, the resistivity of chip increases, and the impurity concentration of adjacent edge end on structure beneath portions increases, this causes The equipotential line density of the depletion layer extended when reverse biased is applied to main pn-junction increases.In this manner it is possible to reduce Influence of the breakdown voltage caused by external charge by insulating film to the surface of edge termination structure part.In addition, when close to When the defect concentrations of edge termination structure beneath portions increases, near service life reduce.Therefore, it is possible to prevent electric current Or remaining carrier is concentrated on when being powered and during Reverse recovery between active part and edge termination structure part On boundary.

In addition to hydrogen (H⁺) other than ion, lithium ion (Li⁺) or oxonium ion (O^-) charged particle (ion) irradiated becomes N-shaped donor.However, the quality of lithium ion or oxonium ion is more than hydrionic quality, and it is sufficiently wide with identical energy harvesting Range be difficult.Therefore, when ion must inject the depth on about 60 μm of the surface away from chip, hydrogen ion (H⁺) it is optimal Choosing.

Fig. 4 is the performance plot for showing the relationship between the body resistivity of semiconductor devices and breakdown voltage.Fig. 6 is to show root The diagram being distributed according to the structure and net dopant concentration of the semiconductor devices of the relevant technologies.Fig. 4 shows that wherein wide setting buffers exist n^-Diode according to the present invention (diode shown in the critical piece sectional view of Fig. 1 in drift layer 1；Hereinafter referred to For example), wherein wide setting buffers are in n^-The diode (the first convenient example) according to the relevant technologies in drift layer 1, with And include not including wide buffering area and there is flat doping concentration distribution (it is described as flat concentration distribution in Fig. 4) n^-The diode (hereinafter referred to as the second convenient example) according to the relevant technologies of drift layer 1.It provides according to first and second The diode of convenient example is as comparative example.n^-The thickness of drift layer 1 is 120 μm and (as shown in Figure 1, for stringent, passes through 120 μm subtract p anode layers 2 and n⁺The thickness of cathode layer 3 and the n obtained^-The thickness of drift layer 1 is 116.5 μm.However, in order to just In explanation, n^-The thickness of drift layer 1 is described as 120 μm).

Wherein wide buffering area 6 is arranged in n^-Diode (according to the example with the first convenient example) in drift layer 1, When changing the effective dose of wide buffering area 6 in various ways, that is, when the effective dose of wide buffering area 6 is 1.0 × 10¹¹Atom/ cm²、2.5×10¹¹Atom/cm²、4.0×10¹¹Atom/cm²、4.8×10¹¹Atom/cm²、5.0×10¹¹Atom/cm²、5.2× 10¹¹Atom/cm²、5.7×10¹¹Atom/cm²And 6.0 × 10¹¹Atom/cm²When, indicate the breakdown voltage of semiconductor devices The change of resistivity (trunnion axis) relative to chip (substrate).In this example, the effective dose of wide buffering area 6 is more than or waits In 4.8 × 10¹¹Atom/cm².For wherein n^-Drift layer 1 have flat doping concentration distribution according to the two of the relevant technologies Pole pipe (the second convenient example), as the n for being 120 μm including thickness^-When the resistivity of the chip of drift layer 1 changes, breakdown voltage Value is indicated by the curve of entitled " according to the flat concentration distribution of the relevant technologies ".

First, in the flat doping concentration distribution according to the relevant technologies, in n^-The constant thickness (120 μm) of drift layer Under conditions of, when resistivity increases, breakdown voltage increases and is focused on steady state value.In general, when designing device, root According to breakdown voltage, be powered when loss and switching characteristic between balance select n^-The thickness and resistivity of drift layer.Example Such as, n^-The thickness of drift layer is relative to rated voltage V₀(V) it is about 0.1V₀(μm).In addition, the rated voltage V of substrate₀(V) and allusion quotation Type electricalresistivityρ₀(Ω cm) is rule of thumb indicated by following formula 3.

[expression formula 3]

ρ₀=0.045V₀

For example, the typical resistivity ρ of substrate₀The rated voltage V of (Ω cm) in 600V₀Place is about 27 Ω cm, 1200V's Rated voltage V₀Place is about 54 Ω cm, the rated voltage V in 1700V₀Place is about 77 Ω cm, the rated voltage V in 3300V₀Place is about For 149 Ω cm, in the rated voltage V of 4500V₀Place is about 203 Ω cm and the rated voltage V in 6500V₀Place is about 293 Ω cm. It, can be according to operational tolerance by the typical resistivity of substrate at the high voltage-rated more than or equal to 1700V in addition, specifically ρ₀(Ω cm) is set as 1.5 times bigger than above-mentioned value.In order to inhibit high overcharged voltage, the typical resistivity ρ of substrate during switch₀(Ω Cm the 80% of above-mentioned value can) be reduced to.

In the rated voltage V of 1200V₀Place, manufactured device have high actual breakdown voltage, and wherein boundary is in specified electricity It is about 20% in pressure.For example, in the rated voltage V of 1200V₀Place, actual breakdown voltage are set as 1400V.In the case, such as As seen from Figure 4, in the diode according to the relevant technologies by flat concentration distribution expression, it is in actual breakdown voltage The resistivity of substrate is 46 Ω cm when 1400V.Similarly, as seen from Fig. 4, wherein the effective dose of wide buffering area be 1 × 10¹¹Atom/cm²、2.5×10¹¹Atom/cm²、4×10¹¹Atom/cm²、4.8×10¹¹Atom/cm²、5.0×10¹¹Atom/ cm²、5.2×10¹¹Atom/cm²、5.7×10¹¹Atom/cm²And 6 × 10¹¹Atom/cm²Diode in, in practical breakdown Resistivity value is respectively 55 Ω cm, 68 Ω cm, 100 Ω cm, 144 Ω cm, 150 Ω cm, 160 Ω m, 200 Ω when voltage is 1400V Cm and 250 Ω cm.

As shown in figure 4, according to the resistivity of chip, variation range (the hereinafter referred to as resistivity of the resistivity of chip Variation range) by consumingly reflection to the variation range of the breakdown voltage of semiconductor devices.That is, when the resistivity of chip is given In width range (hereinafter referred to as change in resistance width) when variation, the breakdown of change in resistance width and semiconductor devices The varying width (hereinafter referred to as breakdown voltage varying width) of voltage is directly related.In the case of the second convenient example, For example, resistivity is 46 Ω cm when breakdown voltage is 1400V.In the range of about 30 Ω cm to about 80 Ω cm (including 46 Ω The resistivity value of cm), breakdown voltage value changes greatly.For example, when change in resistance is 46 Ω cm ± 12% (about 41 Ω cm to 52 Ω cm) when, (hereinafter referred to as breakdown voltage changes model to the variation range of breakdown voltage corresponding with resistivity range of variation Enclose) it is from about 1290V to 1480V.That is, the intermediate value relative to 1385V, breakdown voltage variation range with about 13.7% breakdown potential Press varying width corresponding.Breakdown voltage varying width must be the smaller value needed for market, for example, being less than or equal to 5%.Cause This, in order to meet the breakdown voltage varying width needed for market, change in resistance width must further decrease.However, as above It is described, the change in resistance of the FZ chips of the high resistivity (for example, being greater than or equal to 20 Ω cm) ensured with wafer manufacturer Width range is less than or equal to ± 12% (varying width in gas doping：24%), and in neutron exposure chip be less than or Equal to ± 8% (varying width：16%).Even if in neutron exposure chip, breakdown voltage varying width is noticeably greater than feasible value.

In the first convenient example (including the diode according to the wide buffer structure of the relevant technologies), it is in effective dose 2.5×10¹¹Atom/cm²Wide buffering diode in the case of, breakdown voltage be 1400V (rated voltage V₀=1200V) when Resistivity is about 68 Ω cm, (referring to the A in Fig. 4) as shown in Figure 4.When the variation of resistivity is ± 12%, change in resistance Ranging from from about 60 Ω cm to 76 Ω cm.As seen from Fig. 4, corresponding with the resistivity range of variation of 60 Ω cm to 76 Ω cm Breakdown voltage variation range is from 1320V to 1460V.Relative to the intermediate value of 1390V, breakdown voltage variation range and about 10.1% Breakdown voltage varying width it is corresponding.Breakdown voltage varying width is less than 13.7% breakdown voltage in the first convenient example Varying width, and more than 5% breakdown voltage varying width needed for market.Therefore, breakdown voltage varying width is still inadequate. Similarly, it is 4.0 × 10 in effective dose¹¹Atom/cm²Wide buffering diode in the case of, as seen from Fig. 4, puncturing Voltage is 1400V (rated voltage V₀=1200V) when resistivity be about 100 Ω cm.It is corresponding with ± 12% change in resistance Breakdown voltage variation range be from 1340V to 1430V, and breakdown voltage varying width is about 6.5%.Therefore, also less than The breakdown voltage varying width for being less than or equal to 5% needed for sufficient market.

On the other hand, in the example (diode with wide buffer structure according to the present invention), wide buffering wherein The effective dose in area is 4.8 × 10¹¹Atom/cm²Wide buffering diode in the case of, as seen from Fig. 4 (referring in Fig. 4 B), when breakdown voltage is 1400V, resistivity is 144 Ω cm.When the variation of resistivity is ± 12%, resistivity range of variation For from about 126.7 Ω cm to 161.3 Ω cm.Breakdown voltage variation range corresponding with the resistivity range of variation be from 1363V to 1425V.That is, the intermediate value relative to 1394V, breakdown voltage varying width is 4.4%.Effective dose is 5.0 wherein ×10¹¹Atom/cm²、5.7×10¹¹Atom/cm²And 6.0 × 10¹¹Atom/cm²Wide buffering diode in, similarly, such as As seen from Figure 4, resistivity value corresponding with the breakdown voltage of 1400V is 150 Ω cm, 200 Ω cm and 250 Ω cm.Work as electricity The variation of resistance rate be 12% when, resistivity range of variation be from 132 Ω cm to 168 Ω cm, from 176 Ω cm to 114 Ω cm and From 220 Ω cm to 280 Ω cm.Breakdown voltage variation range corresponding with resistivity range of variation in order be from 1371V to 1431V, from 1378V to 1422V and from 1380V to 1415V.That is, breakdown voltage varying width is in order relative to 1401V Intermediate value be 4.3%, be 3.1% and the intermediate value relative to 1397V is 2.5% relative to the intermediate value of 1400V.Therefore, puncture Voltage change width is reduced to slightly larger than 2% to the range slightly larger than 4%.Therefore, in all examples, meet needed for market 5% breakdown voltage varying width.

Fig. 5 is the performance plot for showing the relationship between the body resistivity of semiconductor devices and breakdown voltage varying width. Relationship between body resistivity shown in Fig. 4 and the breakdown voltage varying width (%) of semiconductor devices is shown in Fig. 5.That is, such as With reference to described in figure 4, select the effective dose of wide buffering area so that actual breakdown voltage relative to given body resistivity value for 1400V, and draw on the vertical axis according to each body resistivity be 12% when breakdown voltage variation range calculate breakdown Voltage change width (%) (trunnion axis indicative of body resistance rate (Ω cm)).

(second is conventional for the diode according to the relevant technologies in the body resistivity with 46 Ω cm and not including wide buffering area Example) in, breakdown voltage varying width is 13.7% (it is higher value), and it is wide not meet the variation of the breakdown voltage needed for market Degree.Even if in structure (first convenient example) of the wherein wide setting buffers in drift layer, when body resistivity is smaller value When 55 Ω cm, 68 Ω cm and 100 Ω cm, breakdown voltage varying width be about more than 5.0% 11.5%, 10.1% and 6.5%, and do not meet the breakdown voltage varying width needed for market.Therefore, the structure is not included in the present invention.When width buffers Area is arranged in drift layer but effective dose is excessive (for example, effective dose is more than 1.0 × 10¹²Atom/cm²) when, with 1400V The corresponding body resistivity of breakdown voltage be more than 300 Ω cm.Therefore, the structure is not included in the present invention.It will hereinafter Reason is described.

On the contrary, according to the present invention diode (example) of the wherein wide setting buffers in drift layer, breakdown potential Pressure varying width is 4.4% at the body resistivity of 144 Ω cm, is 4.3% at the body resistivity of 150 Ω cm, in 160 Ω cm Body resistivity at be 4.0%, be 3.1% at the body resistivity of 200 Ω cm and be at the body resistivity of 250 Ω cm 2.5%.That is, the breakdown voltage varying width of semiconductor devices, which is reduced to needed for market, is less than or equal to 5.0%.Such as from Fig. 4 As it can be seen that width buffering area corresponding with 144 Ω cm, 150 Ω cm, 160 Ω cm, 200 Ω cm and the body resistivity of 250 Ω cm Effective dose be respectively 4.8 × 10¹¹Atom/cm²、5.0×10¹¹Atom/cm²、5.2×10¹¹Atom/cm²、5.7×10¹¹It is former Son/cm²And 6.0 × 10¹¹Atom/cm².Therefore, as seen from Fig. 4, the effective dose of wide buffering area according to the present invention is big In or equal to 4.8 × 10¹¹Atom/cm²And it is less than or equal to 6.0 × 10¹¹Atom/cm².It can confirm, even if when wide buffering area Effective dose increases to 1.0 × 10¹²Atom/cm²When, breakdown voltage varying width further decreases, and body resistivity is less than Or it is equal to 300 Ω cm.

That is, in the semiconductor device according to the invention, effective dose is greater than or equal to 4.8 × 10 wherein¹¹Atom/ cm²And it is less than or equal to 1.0 × 10¹²Atom/cm²Wide buffer structure in, breakdown voltage varying width can decrease below or Equal to the one third for the breakdown voltage varying width not being arranged in the diode according to the relevant technologies of wide buffering area.It is slow in width It rushes in structure, effective dose is more preferably greater than or equal to 5.0 × 10¹¹Atom/cm²And it is less than or equal to 1.0 × 10¹²Atom/ cm², and most preferably more than or equal to 5.2 × 10¹¹Atom/cm²And it is less than or equal to 1.0 × 10¹²Atom/cm², this can The breakdown voltage varying width of semiconductor devices is set reliably to be reduced to less than or equal to 4%.

Specifically, when body resistivity is greater than or equal to 144 Ω cm, the breakdown voltage varying width of semiconductor devices is not Depending on body resistivity.Certainly, breakdown voltage varying width further includes the variation of parameter, such as n^-The thickness or root of drift layer According to the effective dose for forming wide buffering area.However, by combining grinding back surface and etching to chip, the variation of drift layer thickness 3% is may be less than or equal to, and by controlling proton H⁺Injection and annealing temperature, effective dose may be less than or equal to 1%. In the factor for determining breakdown voltage varying width, most important factor is change in resistance width.Therefore, by reducing breakdown potential Press the effect acquired in varying width larger.

In the present invention, except rated voltage V₀At rated voltage other than=1200V, breakdown voltage varying width can subtract It is small.This is because regardless of total doping concentration (dosage) of the entire drift layer of rated voltage be it is constant (less than or equal to about 1.2×10¹²Atom/cm²).In the rated voltage V of 1200V₀Place, when body resistivity is greater than or equal to 144 Ω cm, breakdown potential It presses varying width to be less than or equal to needed for market and is less than or equal to 5%.Numerical value " 144 " with about 12% (≈ 144/1200 × 100%) rated voltage of numerical value " 1200 " is corresponding.As shown in figure 5, when body resistivity is greater than or equal to the number with about 12% When being worth the corresponding 150 Ω cm of rated voltage of " 1200 ", breakdown voltage varying width further decreases.When the bulk resistor of chip When rate is greater than or equal to 160 Ω cm corresponding with 13.3% rated voltage of numerical value " 1200 ", breakdown voltage varying width Less than or equal to 4%, which is less than 5% breakdown voltage varying width needed for market certainly.Similarly, as rated voltage V₀ For 600V when, body resistivity be 72 Ω cm (0.12V₀=0.12 × 600=72).Therefore, in the body more than or equal to 72 Ω cm At resistivity, breakdown voltage varying width is less than or equal to 5%.Similarly, can confirm, in the rated voltage V of 1700V₀With it is big In or equal to the body resistivity of 204 Ω cm, 3300V rated voltage V₀With more than or equal to 396 Ω cm body resistivity and The rated voltage V of 4500V₀At the body resistivity more than or equal to 540 Ω cm, breakdown voltage varying width decrease below or Equal to 5%.Therefore it is necessary condition for the body resistivity of semiconductor device according to the invention is (that is, the resistivity of semiconductor substrate ρ₀) meet following formula 4.

[expression formula 4]

ρ₀≥0.12V₀

Work as electricalresistivityρ₀Preferably greater than or equal to 0.125V₀, more preferably equal to or greater than 0.133V₀When, breakdown voltage variation Width can reliably be reduced to less than or equal to 5%.

Work as electricalresistivityρ₀When more than essential value, it is however generally that, exhausting for carrier accelerates during switch, and switchs wave Shape is possible to vibrate.For example, can confirm, as the rated voltage V in 1200V₀When locating body resistivity more than or equal to 300 Ω cm, Even if in the diode of the wide buffer structure according to the present invention with wherein wide setting buffers in drift layer, due to Carrier exhausts during Reverse recovery, also generates oscillatory occurences.It moreover has been found that when body resistivity is too high, oscillatory occurences is logical Often generated at other rated voltages.An important factor for phenomenon is entire n^-Total doping concentration (dosage) of drift layer.This is Because the extension of space-charge region depends on total doping concentration (dosage) according to Poisson's equation during Reverse recovery, and thus The sum of scanned out carrier is also determined by total doping concentration.Therefore, can confirm, when body resistivity is in the rated voltage of 1200V V₀Place more than 300 Ω cm, body resistivity 600V rated voltage V₀Place is more than 150 Ω cm, body resistivity in the specified of 1700V Voltage V₀Place more than 425 Ω cm, body resistivity 3300V rated voltage V₀Place is more than 825 Ω cm and body resistivity exists The rated voltage V of 4500V₀When place is more than 1125 Ω cm, identical oscillatory occurences is generated.In rated voltage V₀With body resistivity ρ₀ Between opening relationships ρ₀≤0.25V₀.Therefore, body resistivity ρ₀It must satisfy following formula 5.

[expression formula 5]

ρ₀≤0.25V₀

Width buffer structure according to the present invention is characterized by, and wide buffering area is in n^-It is formed in a part for drift layer, and And with substrate concentration (body impurity concentration) a part or its net dopant concentration be less than substrate concentration a part contact. By this method, breakdown voltage can be determined independent of bulk concentration.Therefore, breakdown voltage varying width can reduce.It is wide slow wherein It rushes area and is distributed in entire n^-In structure on drift layer, to the control of impurity concentration and breakdown voltage be solely dependent upon ion implanting and Driving.Therefore, when rated voltage changes (specifically, when breakdown voltage increases), hydrogen causes donor to be distributed in n^-In drift layer In broad range more than or equal to 100 μm, and its impurity concentration must reduce.Currently, actually it is difficult to obtain n^-Drift The above-mentioned concentration distribution of layer.

On the contrary, in the present invention, it can be in body resistivity ρ₀On the basis of determine main rated voltage V₀.Actual breakdown voltage is logical It crosses and causes the impurity concentration of donor to be determined with body net dopant concentration (that is, resistivity) phase Calais hydrogen.Therefore, no matter semiconductor devices Breakdown voltage how all can with the application of the invention, and the effective dose of the donor mutually to associate with hydrogen have relatively small error In the case of, the present invention can reduce influence of the change in resistance width to breakdown voltage varying width.It by this method, can be easily Manufacture the diode with small breakdown voltage varying width.

In Fig. 2 (c), with proton H⁺11 irradiation front surfaces (anode electrode).However, as shown in Fig. 2 (c), proton H can be used⁺ 11 irradiation rear surfaces (cathode electrode).Other techniques of method shown in Fig. 3 are identical as the technique of manufacturing method shown in Fig. 2. That is, the difference between Fig. 2 and Fig. 3 is technique (c).

As described above, semiconductor devices according to first embodiment, wide buffering area 6 is arranged in n^-In drift layer 1, the n^-Drift It is its body resistivity ρ to move layer₀(Ω cm) is relative to rated voltage V₀(V) meet the substrate of expression formula 2.The net doping of wide buffering area 6 The total amount of concentration is within the above range.By this method, even if when the variation of body resistivity is about ± 12%, the breakdown of diode The range that voltage changes relative to the variation of body resistivity can also reduce.In addition, the switching characteristic of semiconductor devices relative to The variation of body resistivity and the range that changes can reduce.Therefore, the variation of breakdown voltage and the variation of switching characteristic can reduce.

In addition, according to the method for manufacturing semiconductor devices according to first embodiment, in a main surface of FZ chips 10 (n^-Drift layer 1) on formed after p anode layers 2, to the p anode layers 2 or n than that will be formed in the subsequent process⁺Cathode layer 3 is deep Part projected range in use H⁺The front surface or rear surface of 11 irradiation FZ chips 10, and more than or equal to 300 DEG C and It is heat-treated at a temperature of less than or equal to 550 DEG C.By this method, under these conditions in n^-It is formed in drift layer 1 wide slow Rush area 6.In the case, resistivity (body resistivity) ρ of FZ chips 10₀Relative to rated voltage V₀Meet above-mentioned condition.With this Mode, even if when the variation of the resistivity of body FZ chips 10 is about ± 12%, the breakdown voltage of semiconductor devices is relative to FZ The variation of the resistivity of chip 10 and the range that changes can also reduce.In addition, the switching characteristic of semiconductor devices is relative to FZ crystalline substances The variation of the resistivity of piece 10 and the range that changes can reduce.Therefore, the variation of breakdown voltage and the variation of switching characteristic can subtract It is small.

With proton H⁺11 irradiations before forming wide buffering area 6, to introduce oxygen into FZ chips 10 under these conditions.With this Mode, when with proton H⁺When 11 irradiation chip, it can prevent the mobility of the electrons and holes in wide buffering area 6 from declining.

In addition, allowing to be manufactured with low cost the diode with wide buffer structure using FZ chips 10.By this method, it can drop Low manufacturing cost.

(second embodiment)

Fig. 7 is the diagram of the structure and net dopant concentration distribution that show semiconductor devices according to second embodiment.According to Multiple wide buffering areas 6 of first embodiment may be provided at n^-In drift layer 1.

In a second embodiment, as shown in fig. 7, forming multiple wide buffering areas 6 (three wide buffering areas in Fig. 7).As a result, Multiple wide buffering areas 6 allow to be finely controlled extension of the space-charge region during switch.It is being formed with multiple wide buffering areas In structure, as rated voltage V₀For 1200V when, preferably body resistivity is greater than or equal to 144 Ω cm, and in first embodiment Body resistivity is identical.In addition, when being formed with multiple wide buffering areas 6, compared with being formed there are one the structure of wide buffering area, it is easy The wide buffering area with high impurity concentration is formed according to wide number.Therefore, there are one the structures of wide buffering area with formation It compares, during switch or when maintaining supply voltage, the decline of the electric field strength of space-charge region may be larger.Therefore, half The breakdown voltage of conductor device reduces.Therefore, body resistivity can further increase, and preferably body resistivity is greater than or equal to 0.15V₀.The upper limit of body resistivity is 0.25V₀, and it is above-described identical.The structure phase of other structures and first embodiment Together.

Next, description is formed with operation and the effect of the structure of multiple wide buffering areas.Figure 14 is shown when application The performance plot of relationship when reverse biased between the net dopant concentration distribution and internal electric intensity distribution of drift layer.In Figure 14 In, include have flat concentration distribution drift layer according to the diode of the relevant technologies and including being provided with multiple width In the diode according to the present invention of the drift layer of buffering area, when a reverse bias is applied, the net dopant concentration of drift layer is distributed It is corresponding with internal electric intensity distribution.Figure 14 (a) and 14 (b) are to show when applying reversed inclined equal with breakdown voltage of level The maximum value of pressure and electric field strength becomes critical electric field strength E_C(about 2.5 × 10⁵V/cm) in the root with flat concentration distribution The diagram of ((b)) is distributed according to electric-field intensity distribution ((a)) when leading to avalanche breakdown in the diode of the relevant technologies and donor concentrations. Figure 14 (c) and 14 (d) are to show to work as to be applied with the level reverse biased equal with breakdown voltage and with multiple wide buffering areas Diode according to the present invention in the maximum value of electric field strength become critical electric field strength E_CWhen electric-field intensity distribution ((c)) and Donor concentrations are distributed the chart of ((d)).In two diodes, it is assumed that the standard value of the donor concentrations of FZ body chips is N₀, and The measured value of the donor concentrations of FZ body chips is (1+ α) N₀(or (1- α) N₀, α>0).Alternatively, when a series of elements of execution are formed When technique, it is processed into while FZ body chips in a large amount of FZ bodies chips (for example, 50 FZ bodies chips) of unit for flowing The standard deviation of the measured value of donor concentrations can be (1+ α) N₀(or (1- α) N₀, α>0).I.e., it is assumed that the change rate of donor concentrations For ± α (α>0).

In the present embodiment, for example, using known spreading resistance profiling (profiling) method or C-V methods as measuring The method of the donor concentrations of chip.In Figure 14 (a) and 14 (c), for convenience of description, show wherein when application level and breakdown Depletion layer does not reach the so-called non-break-through type of N-shaped cathode layer when voltage identical voltage.However, wherein depletion layer can be used Reach the break-through type of N-shaped cathode layer.In the case, it is similar to non-break-through type, establishes following discussion.

For the diode according to the relevant technologies, when in electric field strength E in the depth x away from pn-junction₀The boundary condition that place is 0 When lower solution Poisson's equation, voltage value (breakdown voltage value) Φ₀It is N in donor concentrations₀When be Φ₀=-(1/2) x₀E_C.Work as electric field Intensity is when the position x as boundary condition ± locate is 0, the maximum value and minimum value Φ of breakdown voltage value ± in body donor concentrations Change (1 ± α) N₀When be Φ ±=Φ₀/(1±α/2).Therefore, change rate ΔΦ/Φ of breakdown voltage value₀For 4 α/{ (2- α) (2+ α) } (wherein ΔΦ=Φ_--Φ₊)。

In the diode according to the present invention including multiple wide buffering areas, for stringent, when solving Poisson's equation, pool The value of loose measure journey is complicated.Therefore, in the present embodiment, using simple method come calculate the change rate ΔΦ of voltage value/ Φ₀.First, as shown in Figure 14 (d), it is assumed that form a concentration of body donor concentrations N₀β times and width be W₀N wide buffering areas. In addition, it is assumed that the impurity concentration of wide buffering area is ideally distributed, and impurity concentration does not change.Assuming that β is more than 1.In Figure 14 (c) in, due to β times of the size that the gradient magnitude of the electric field strength of each wide buffering area is another wide buffering area, occur More than body portion (concentration N₀) electric field strength decline Δ E.When continuously n times occur for " decline " of electric field strength, wherein Beam overall of the total length of the part (that is, body portion rather than wide buffering area) of " decline " of electric field strength relative to drift layer does not occur The ratio γ for spending Wd is (W_d-nW₀)/W_d.Due to meeting n >=2 and 0<W₀<W_d, therefore γ is greater than or equal to 0 and is less than or equal to 1. On the other hand, reduce maximum value Es of n times of the electric field strength Δ E relative to same electric field intensity_CRatio η be Σ_iΔE_i/E_C= qβN₀nW₀/(E_Cε₀ε_Si) (wherein q is elementary charge, ε₀For the capacitivity of vacuum, and ε_SiFor the relative permitivity of silicon).η is more than Or equal to 0 and it is less than or equal to 1.I.e., it is assumed that when multiple wide buffering areas are arranged, the change rate of voltage value is by from flat The tribute of the change rate removal of the diode according to the relevant technologies of the smooth concentration distribution wide buffering area that acceptor density variation does not influence It offers and the contribution of the part of electric field strength " decline " and the value that obtains in wide buffering area.On the basis of the hypothesis, voltage Change rate ΔΦ/Φ of value₀It is multiplied by by the same ratio in the diode according to the relevant technologies with flat concentration distribution The factor (γ/η) obtains.Therefore, ΔΦ/v is established₀=4 α (γ/η)/{ (2- α) (2+ α) }.When α is more than 0% and is less than or waits When 12%, ΔΦ/v₀It is close to 4 α/{ (2- α) (2+ α) } ≈ α in the range, and establishes ΔΦ/Φ₀≈α(γ/η)。 Increase with the total n of wide buffering area, γ reduces.Therefore, varying width ΔΦ/Φ of voltage value₀Reduce.In addition, with width The concentration of buffering area is more than bulk concentration N₀The quantity n of (that is, β increases) or wide buffering area increases, the ratio η of electric field strength " decline " Increase.In addition, with the width W of wide buffering area₀Increase, η increases.Therefore, with the buffering area with high concentration and big width Quantity increase, theoretically, change rate ΔΦ/Φ of voltage (breakdown voltage)₀Reduce.

For example, being N for standard value₀=2x 10¹³Atom/cm³FZ body chips, it is assumed that N₀Change rate α be 12%, institute The quantity n of the wide buffering area formed is 3, width W₀For 6 μm and the concentration of wide buffering area is relative to N₀Multiple β be 10. In this case, since η is 2.19 and γ is 0.85, change rate ΔΦ/Φ of breakdown voltage₀For 0.047 significantly less than α (4.7%), and 5% breakdown voltage varying width needed for market can be met.Therefore, when the multiple wide buffering areas of formation are with full When the condition of sufficient following formula 6, it is possible to by change rate ΔΦ/Φ of breakdown voltage value₀Decrease below preferred FZ bodies The change rate of chip.

[expression formula 6]

4α(γ/η)/{(2-α)(2+α)}<α

In addition, when forming multiple wide buffering areas to meet 4 α (γ/η)/{ (2- α) (2+ α) }≤0.05, it is possible to reliable Ground is by change rate ΔΦ/Φ of breakdown voltage value₀Decrease below the change rate of preferred FZ bodies chip.

Above-mentioned consideration is ideal.For example, when (concentration of wide buffering area is relative to bulk concentration N by β₀Multiple) it is too big or work as When n (quantity of wide buffering area) is too big, total " decline " of electric field strength increases, and is difficult to obtain enough breakdown voltages.Work as β When only sufficiently close to 1 value, big difference is not present between " decline " the Δ E and the decline of bulk electric field intensity of electric field strength It is different, and the effect of wide buffering area reduces, and this to prevent breakdown voltage from becoming difficult.Therefore, β, W₀And n is necessary Breakdown voltage, breakdown voltage variation and prevent Reverse recovery vibrate effect on the basis of determine.In addition, each width The close Gaussian Profile by proton irradiation of the shape of buffering area.Indicate the half width and W of Gaussian Profile diffusion₀It is corresponding, and And depend on Proton emission energy.When by with proton irradiation come when forming wide buffering area, for example, to consider donor concentrations to Fixed width buffering area upper integral, and the integrated value is averaged by half width.That is, " decline " the Δ E due to electric field strength is buffered by width The summation (effective dose) of the integrated value in area determines, therefore it is not significantly dependent on the shape of wide buffering area (shape is square Shape or Gaussian Profile) between difference.Therefore, β, W are selected₀And n is with actually it is determined that the total mark of each width buffering area is dense Degree.In addition, establishing above-mentioned expression formula 6 in the case where being not dependent on rated voltage.The reason is as follows that.Critical electric field strength E_cTo root According to rated voltage, the dependence of the concentration of the body chip of determination is weaker, and to consider that dependence is substantially invariable value.Separately Outside, " decline " the Δ E of electric field strength is not dependent on each wide concentration of buffering area or the concentration of body chip, but depends on each width The integrated value (total concentration or effective dose) of the concentration of buffering area or the concentration of body chip.

With first embodiment, the sum of effective dose of multiple wide buffering areas 6 (Fig. 7) can be greater than or equal to 4.8 × 10¹¹Atom/cm²And it is less than or equal to 1.0 × 10¹²Atom/cm².In a second embodiment, when three wide buffering areas 6 have Fig. 7 Shown in peak concentration and when half width, the integral concentration of wide buffering area by the incremental order of the distance away from anode electrode 4 be 4 × 10¹¹Atom/cm²(peak concentration is 2 × 10¹⁴Atom/cm³, and half width be 20 μm), 3 × 10¹¹Atom/cm²(peak concentration It is 3 × 10¹⁴Atom/cm³, and half width be 10 μm), 2 × 10¹¹Atom/cm²(peak concentration is 4 × 10¹⁴Atom/cm³, and half Width is 5 μm), and the sum of integral concentration is 9 × 10¹¹Atom/cm²。

It is preferred that the quantity of wide buffering area 6 is greater than or equal to 2 and less than or equal to 5 to meet above-mentioned effective dose.When specified When voltage is greater than or equal to 3300V, the overall thickness of drift region is greater than or equal to 300 μm, and the thickness has enough allowances.Cause This, if it is necessary, the quantity of wide buffering area can be greater than or equal to 5.In addition, as described above, wide buffering area integral concentration The sum of it is constant in the case of, the shape or position change of each width buffering area, the change rate of breakdown voltage do not change with shape or The corresponding value of change of position.In addition, depth of the wide buffering area away from anode electrode closest to anode electrode is set as being more than W_d/ 2, therefore ensure that has the region of low impurity concentration (high resistance) in drift layer near pn-junction.In this manner it is possible to anti- Only the electric field strength near pn-junction increases during Reverse recovery or in cosmic ray incidence.Alternatively, from drift layer Between position rise close to cathode electrode wide buffering area quantity can be more than from the centre position close to anode electrode width buffering The quantity (including 0) in area.In this case, it is preferable to obtain same effect.

Even if when being formed with multiple wide buffering areas 6, it is also possible to which proton irradiation front surface or rear surface are to form each width Buffering area 6.In the case of a bipolar type transistor, at least closest to the wide buffering area 6 of anode layer, preferably using proton irradiation anode layer Thus the carrier lifetime value of proton transmission area or proton blocking area is decreased below the carrier lifetime value of body by 2 surface.

As described above, according to second embodiment, it is possible to obtain the effect being identical with the first embodiment.Due in n^-Drift Multiple wide buffering areas 6 are formed in layer 1, it is therefore possible to the extension of space-charge region is subtly adjusted during switch.

(3rd embodiment)

Fig. 8 is the diagram of the structure and net dopant concentration distribution that show semiconductor devices according to third embodiment.According to The structure of the semiconductor devices of the first and second embodiments can be applied to IGBT.

As shown in the sectional view (upside of paper) of semiconductor devices in fig. 8, according to third embodiment In IGBT, p base layers 22 are formed in the front surface (main surface) of n-type semiconductor substrate (chip).In the rear table of chip P collector layers 28 are formed on face (another main surface).The portion between p base layers 22 and p collector layers 28 of semiconductor substrate It is n to divide^-Drift layer 21.Body resistivity ρ₀(Ω cm) is identical as the body resistivity in first embodiment.That is, body resistivity is by upper It states in the range of expression formula 2 indicates or in above-mentioned preferred scope.Emission electrode 24 is formed on the surface of p base layers 22.In p Collecting electrodes 25 are formed on the surface of collector layer 28.Groove is formed in the front surface of chip to be reached by p base layers 22 n^-Drift layer 21, and gate insulating film 31 is formed on the inner wall of groove.Gate electrode 27 is embedded to by gate insulating film 31 in groove. N emitter layers 29 are formed in p base layers 22.Emission electrode 24 makes p base layers 22 be electrically connected with n emitter layers 29.In addition, hair It is insulated with gate electrode 27 by the interlayer dielectric 32 formed on gate insulating film 31 and gate electrode 27 radio pole 24.

In fig. 8, such as in the performance plot for showing the relationship between the distance away from emission electrode 24 and net dopant concentration (log) Shown in (downside of paper), n^-The net dopant concentration of drift layer 21 is substantially in n^-The centre of drift layer 21 nearby has peak value, And it tilts to decline towards p base layers 22 and p collector layers 28.That is, in n^-Impurity concentration is formed in drift layer 21 is more than n^-Drift Move the wide buffering area of N-shaped 26 that layer 21 and net dopant concentration are less than p base layers 22 and p collector layers 28.Wide buffering area 26 it is effective Dosage (total amount of the net dopant concentration of same layer) is greater than or equal to 4.8 × 10¹¹Atom/cm²And it is less than or equal to 1.0 × 10¹² Atom/cm²Or in above-mentioned preferred scope, the effective dose and the effective dose phase in diode according to first embodiment Together.By with the proton H from collecting electrodes 25⁺11 irradiations include the chip of p base layers 22 and emission electrode 24 and to crystalline substance Piece is heat-treated to form wide buffering area 26.Fig. 8 shows the IGBT with trench gate structure, but can be used has planar gate The IGBT of structure.

Since p collector layers 28 are formed in the rear surface of IGBT, by Minority carrier injection rear surface.Therefore, During cut-off, it is necessary to prevent injected minority carrier from reaching space-charge region by neutral charge area.In addition, when applying When adding voltage corresponding with breakdown voltage, preferably ensure that unspent neutral charge area at about 5 μm to about 20 μm away from rear surface In the range of, to prevent avalanche breakdown.It is therefore preferable that being arranged to the peak value that the net dopant concentration of wide buffering area 26 is distributed from n^- The depth at the center of drift layer 21 is partial to collecting electrodes 25 to be reliably prevented depletion layer, therefore ensures that above-mentioned neutral charge Area.

Next, will be described in the technique for manufacturing IGBT according to third embodiment.Fig. 9 is to show manufacture according to third The diagram of the technique of the semiconductor devices of embodiment.Figure 10 to 12 shows to manufacture semiconductor devices according to third embodiment Another exemplary diagram of technique.For example, IGBT of the description manufacture with size shown in Fig. 8 and net dopant concentration is (specified Voltage：V₀=1200V；And rated current：150A) the case where.

The example of the method for IGBT according to third embodiment will be manufactured to 9 (i) description with reference to figure 9 (a).First, it prepares Body resistivity is 144 Ω cm to 300 Ω cm (for example, 150 Ω cm (phosphorus concentrations：2.0×10¹³Atom/cm³) and thickness be about 500 μm FZ chips 10 as chip (semiconductor substrate).FZ chips 10 are referred to as the first semiconductor layer (Fig. 9 (a)).Such as first Described in embodiment, first pass through in advance push away trap technique under room temperature (for example, 20 DEG C) by concentration higher than solid solubility oxygen diffusion simultaneously Introduce FZ chips 10.

Then, p base layers 22 are formed in a main surface of FZ chips 10 by standard IGBT manufacturing process including are protected The edge termination structure part of retaining ring (not shown), groove, the gate insulating film 31 in the groove, gate electrode 27, n emitter layers 29 and interlayer dielectric 32 (Fig. 9 (b)).The impurity concentration of p base layers 22 is such as 2 × 10¹⁷Atom/cm³, and it is away from table The junction depth in face is such as 3 μm.The impurity concentration of n emitter layers 29 is such as 1 × 10²⁰Atom/cm³, and its knot away from surface Depth is such as 0.5 μm.Gate electrode 27 can be made of such as polycrystalline.

Then, with the proton H accelerated by cyclotron⁺Front surface, the i.e. another main surface of 11 irradiation FZ chips 10 (collecting electrodes 25 will be formed on later) (Fig. 9 (c)).At this point, the accelerating potential of cyclotron is such as 7.9MeV, and Proton H⁺11 dosage is such as 1.0 × 10¹⁴Atom/cm².In addition, aluminium absorber is for adjusting proton H⁺11 thickness so that its Surface away from silicon substrate is 90 μm.When the thickness of FZ chips 10 is such as 500 μm, proton H is adjusted⁺11 thickness is so that proton H⁺11 range is 410 μm.The range can be adjusted by using the accelerating potential of electrostatic accelerator.In the case, accelerate Voltage is 7.5MeV.In Fig. 9 (c), because with H⁺11 crystal defects 13 for irradiating and being generated in FZ chips 10 are indicated by X.

Then, for example, being heat-treated up to 5 hours in nitrogen atmosphere (it may include hydrogen) to make up crystalline substance at 500 DEG C Volume defect 13.By this method, n-type high concentration region is formed before and after the depth of 30 μm of the rear surface away from chip.Pass through height Concentration area forms desired wide buffering area 26 (Fig. 9 (d)).

Then, emission electrode 24 is formed to be contacted with n emitter layers 29.In addition, in the marginal end binding including protection ring Protective film (not shown) (Fig. 9 (e)) is formed on structure part.Emission electrode 24 is made of such as Al-Si (1%), and protective film It is such as polyimides or silicon nitride (SiN) film.

Then, the rear surface of FZ chips 10 is ground and wet etching 30 is to expire the reduction of the thickness of FZ chips 10 Prestige value (Fig. 9 (f)).In this stage, when rated voltage is V₀For 1200V when, the thickness of FZ chips 10 is usually at 100 μm to 160 μ In the range of m.(Fig. 9) in the third embodiment, in this stage, the thickness of FZ chips 10 is 120 μm.

Then, with such as proton H⁺Or phosphorus⁺15 etc p-type impurity irradiation is ground the FZ chips with wet etching 30 10 FZ wafer surfaces (rear surface), this will form n barrier layers 23.Dosage be configured to activation (its will hereinafter between into Row description) after impurity concentration be such as 2 × 10¹⁶Atom/cm³(FIG.9(g)).Then, by ion implanting come introduce by Form the n-type impurity of p collector layers 28, such as boron⁺14 (Fig. 9 (h)).At this point, accelerating potential is such as 50keV, and dosage quilt It is 3 × 10 to be arranged to the impurity concentration after activating¹⁷Atom/cm³.The effective dose of n barrier layers 23 is set as including wide slow It rushes area 26 and meets the range of above-mentioned effective dose condition.

Then, laser annealing is carried out to electrically activate ion implanting surface, and p collector layers 28 are consequently formed.It is sharp in order to execute It is living, furnace annealing rather than laser annealing can be carried out.In the case of furnace annealing, for example, in nitrogen atmosphere (its at 450 DEG C May include hydrogen) in be heat-treated up to 5 hours to execute activation.

Finally, metal material is deposited on the surface of p collector layers 28 by the order of such as Al-Si (1%), titanium, nickel and gold On to form the collecting electrodes 25 with the surface Ohmic contacts of p collector layers 28.By this method, IGBT (Fig. 9 (i)) is completed.

Next, by description to the variant of 3rd embodiment.It will be described with reference to figure 10 (a) to 10 (h) to manufacturing shown in Fig. 9 IGBT method (hereinafter referred to as the first manufacturing method) variant (hereinafter referred to as the second manufacturing method).Second system Make method and the first manufacturing method shown in Fig. 9 the difference is that, carried out after forming emission electrode 24 and protective film With proton H⁺11 irradiation (referring to Fig. 9 (c)), and the rear surface of FZ chips 10 is ground and wet etching 30.When with Proton H⁺When the heat resisting temperature of emission electrode 24 and the protective film of edge termination structure part is higher than heat treatment temperature after irradiation, Second manufacturing method shown in Fig. 10 is effective.

Specifically, from FZ chips 10 are prepared to the mos gate pole and edge termination structure portion formed as element surface structure The technique divided is identical as technique shown in Fig. 9 (a) and 9 (b).Then, emission electrode 24 is formed and made of polyimides Protective film (not shown) (Figure 10 (b)).Then, the rear surface of FZ chips 10 is ground and wet etching 30 is with by FZ chips 10 thickness is reduced to desired value (Figure 10 (c)).Then, with proton H⁺The rear surface (FIG.10 (d)) of 11 irradiation chips, and It is heat-treated (FIG.10 (e)).With proton H⁺During irradiation, by proton H⁺11 range is adjusted to accelerate by irradiating In the upper range of the accelerating potential of device.In addition, working as proton H⁺Range away from rear surface is set as 30 μm in electrostatic accelerator When, acceleration energy 1.5MeV.Alternatively, cyclotron can be used, and the range can be adjusted by aluminium absorber.Figure Technique after 10 (f) is identical as the technique after Fig. 9 (g) in the first manufacturing method.It is formed when by the second manufacturing method When IGBT, it is possible to reduce the quantity of the technique after the thickness reduction of FZ chips 10, and thus reduce defect, such as because of place It manages LED reverse mounting type and destroys the chip.

Next, the first variant of the first manufacturing method shown in Fig. 9 will be described (below with reference to figure 11 (a) to 11 (i) In be known as third manufacturing method).Third manufacturing method and the first manufacturing method shown in Fig. 9 the difference is that, in fig.9 The grinding of rear surface and wet etching 30 (Fig. 9 (f)) and the technique (Fig. 9 (e)) for forming emission electrode 24 are reversed (referring to Figure 11 (e) and 11 (f)).Other techniques are identical as the technique in the first manufacturing method shown in Fig. 9.When with proton H⁺After 11 irradiations Heat treatment temperature when being higher than the heat resisting temperature of emission electrode 24, IGBT according to third embodiment can pass through shown in Figure 11 the Three manufacturing methods manufacture.

Next, the variant of the second manufacturing method shown in Fig. 10 will be described (hereinafter with reference to figure 12 (a) to 12 (g) Referred to as the 4th manufacturing method).4th manufacturing method and the second manufacturing method shown in Fig. 10 the difference is that, do not execute figure The technique that the fields the n barrier layer of neighbouring p collector layers 28 is introduced shown in 10 (f), and have and blocked by wide buffering area 26 The extension of depletion layer is not so that depletion layer reaches the IGBT of the structure of p collector layers.In this manner it is possible to only brilliant by adjusting The concentration of p collector layers 28 in the rear surface of piece improves the injection efficiency in hole with depth is introduced.Other techniques and Figure 10 Shown in technique in the second manufacturing method it is identical.

In the third embodiment, it has been described that the IGBT with trench gate structure.However, flat present invention can apply to have The IGBT of face grid structure.

As described above, according to second embodiment, in IGBT, it is possible to obtain the effect being identical with the first embodiment.

(fourth embodiment)

Figure 13 is the diagram for showing to be distributed according to the structure and net dopant concentration of the semiconductor devices of fourth embodiment.According to Multiple wide buffering areas 26 of 3rd embodiment may be provided at n^-In drift layer 21.

In the fourth embodiment, as shown in figure 13, multiple wide buffering areas 26 (three wide buffering areas in Figure 13) are formed.By This, when multiple wide buffering areas 26 are arranged, it is possible to be finely controlled extension of the space-charge region during switch.It is being formed with In the structure of multiple width buffering areas, as rated voltage V₀For 1200V when, preferably body resistivity be greater than or equal to 144 Ω cm, with Body resistivity in first embodiment is identical.In addition, when being formed with multiple wide buffering areas 26, there are one wide buffering areas with formation Structure compare, be easy according to wide number formed with high impurity concentration wide buffering area.Therefore, with formation there are one The structure of wide buffering area is compared, and during switch or when maintaining supply voltage, the decline of the electric field strength of space-charge region can It can be larger.Therefore, the breakdown voltage of semiconductor devices reduces.Therefore, body resistivity can further increase, and preferred bulk resistor Rate is greater than or equal to 0.15V₀.The upper limit of body resistivity is 0.25V₀, and it is above-described identical.Other structures and third are real The structure for applying example is identical.

As shown in the first embodiment, the sum of effective dose of multiple wide buffering areas 26 can be greater than or equal to 4.8 × 10¹¹ Atom/cm²And it is less than or equal to 1.0 × 10¹²Atom/cm².In the fourth embodiment, when three wide buffering areas 26 have Figure 13 Shown in peak concentration and when half width, the first wide buffering area closest to emission electrode 24 has 4 × 10¹⁴Atom/cm³Peak It is worth concentration and 10 μm of half width, the second wide buffering area has 1.5 × 10¹⁵Atom/cm³Peak concentration and 5 μm of half width, And the wide buffering area of the third farthest from emission electrode 24 3.5 × 10¹⁵Atom/cm³Peak concentration and 3 μm of half width.Width is slow It is 2 × 10 that the integral concentration in area 26, which is rushed, by the incremental order of the distance away from emission electrode 24¹¹Atom/cm²、3×10¹¹Atom/ cm²And 4 × 10¹¹Atom/cm², and the sum of integral concentration is 8 × 10¹¹Atom/cm².In addition, the peak of n barrier layers 23 Value concentration is substantially 1.0 × 10¹²Atom/cm², and n-layer (n^-Drift layer 21, wide buffering area 26 and n barrier layers 23) the sum of effective dose (integral concentration) is 1.8 × 10¹²Atom/cm²。

IGBT must be designed to：When gate turn-on, do not occur to return (snapback) phenomenon suddenly in IV output waveforms (wherein due to indivisible electric current, big voltage occurs between collecting electrodes and emission electrode once without conductivity modulation The negative resistance phenomenon that drop and voltage drop rapidly reduce by conductivity modulation, this leads to electric current flowing).Therefore, three N-shapeds The sum of the integral concentration of layer can be more than 2.0 × 10¹²Atom/cm².Depletion layer should not reach p collector layers in cut-off state 28.Therefore, the sum of the integral concentration of three n-layers has to be larger than 1.2 × 10¹²Atom/cm².For this purpose, the integral of three n-layers The sum of concentration can be greater than or equal to 1.2 × 10¹²Atom/cm²And it is less than or equal to 2.0 × 10¹²Atom/cm².In addition, only with p Meet the range of integral concentration in the fields the n barrier layer 23 that collector layer 28 contacts.In the case, phosphorus can be introduced to form n Barrier layer 23, or proton H can be introduced⁺To form n barrier layers 23.When meeting integral concentration in all three n-layers When range, the hole as minority carrier is smoothly injected in gate turn-on from p collector layers, and can steadily be obtained Breakdown voltage.

In the case of igbts, be provided with the structure of multiple wide buffering areas operation and effect substantially with according to The operation of the diode of two embodiments is identical with effect.That is, when the change rate of the donor concentrations of FZ body chips is ± α (α>0) it, removes The ratio of the total length of body portion other than wide buffering area is γ and reduces n times of electric field strength Δ E phases in wide buffering area For critical electric field strength E_CRatio be η when, be preferably formed as multiple wide buffering areas to meet 4 α of condition (γ/η)/{ (2- α) (2 +α)}<α.As described in the third embodiment, in IGBT, in order to form p collector layers 28 in rear surface, minority is carried Stream injection rear surface.It is therefore preferable that ensuring range of the unspent neutral charge area at 5 μm to 20 μm away from rear surface.It is preferred that The peak value that the net dopant concentration of wide buffering area 26 is distributed is arranged to from n^-The depth at the center of drift layer 21 is partial to current collection electricity Pole 25 therefore ensures that above-mentioned neutral charge area to be reliably prevented depletion layer.That is, when forming multiple wide buffering areas 26 to drift about certainly When collecting electrodes are partial at the center of layer, " decline " the Δ E of preferred electric field strength can occur in the same area (referring to Figure 14 (c)).Specifically, can be more than from centre position close to the quantity of the wide buffering area of collecting electrodes from the centre position of drift layer Play the quantity (including 0) close to the wide buffering area of emission electrode.

In the fourth embodiment, when being formed with multiple wide buffering areas 26, proton H is preferably used⁺To irradiate FZ chips 10 Rear surface (side for being formed with p collector layers 28 thereon).The reason is that, when irradiating the front surface of chip, in gate oxidation films Crystal defect occurs in interface between silicon, and the crystal defect may influence the voltage characteristic of grid.In addition, when capture When level (trapping level) retains near p base layers 22, Carrier Profile changes in conducting state, and is connected Compromise characteristic between voltage and cut-off loss may deteriorate.

As described above, according to fourth embodiment, it is possible to obtain and first to the identical effect of 3rd embodiment.

N-shaped field barrier layer has been described in the IGBT according to the third and fourth embodiment.However, N-shaped field barrier layer can Applied to the diode according to the first and second embodiments.That is, can be by injecting phosphorus or with proton H⁺Irradiation and in n⁺Cathode layer 3 And n^-N barrier layers are formed between drift layer 1, compare n to make it have⁺The small impurity concentration of cathode layer 3 and neighbouring n⁺Cathode layer 3.

As described above, in accordance with the present invention, it is possible to realizing that it is small that diode or IGBT have with the technique accurately controlled Breakdown voltage varying width, significantly smaller than the product according to the relevant technologies cut-off loss and Sofe Switch characteristic.Therefore, have It may be arranged with low electrical loss and consider the IGBT or intelligent power module (IPM) of environmental problem.In addition, such as making In the power conversion apparatus of PWM inverter with IGBT module with the above characteristics etc, it is possible to prevent over-voltage breakdown or The generation of EMI and reduction heat loss.For example, there are following power conversion apparatus.Converter inverter circuit can be controlled efficiently Such as induction machine or servo motor are made, and is widely used for industry or electronics railway.Power factor improves circuit (PFC electricity Road) the AC input electric current of sinusoidal waveform is controlled to improve waveform, and it is used for Switching Power Supply.In addition, when according to the present invention When forming p-type insulating layer in the section of igbt chip to form reverse blocking IGBT, reverse blocking IGBT can be used for matrix conversion Device.Since matrix converter does not need DC link capacitors, it can be used for needing the small converter of such as elevator etc The device of part.When the present invention is applied to reverse blocking IGBT, n barrier layers are configured to have than dense in 3rd embodiment Small impurity concentration is spent (for example, 2 × 10¹⁶Atom/cm³) or skip the n barrier layer, and one or more width buffer The depletion layer that the concentration in area is adjusted to before making into blocking state does not reach p collector layers.According to the structure, when depletion layer is anti- When being extended into blocking state from the pn-junction between p collector layers and drift layer, it is possible to prevent the electric field strength of pn-junction from concentrating, And breakdown reverse voltage and forward direction breakdown voltage are maintained into identical magnitude.

Industrial applicibility

As described previously for the power semiconductor device for such as power conversion apparatus (such as converter or inverter) Part, semiconductor device according to the invention and the method for manufacturing semiconductor devices are useful.

The explanation of letter or number reference numeral

1、21 n^-Drift layer

2 p anode layers

3 n⁺Cathode layer

4 anode electrodes

5 cathode electrodes

6,26 wide buffering area

10 FZ chips

11 proton H⁺

12 insulating films

13 crystal defects

14 boron⁺

15 phosphorus⁺

22 p base layers

23 n barrier layer

24 emission electrodes

25 collecting electrodes

27 gate electrodes

28 p collector layers

29 n emitter layers

30 grindings and wet etching

31 gate insulating films

32 interlayer dielectrics

Claims

1. a kind of semiconductor devices, including：

First semiconductor layer of the first conductive type；

It is arranged in a main surface of first semiconductor layer and impurity concentration is more than the second of first semiconductor layer Second semiconductor layer of conductivity type；

It is arranged in another main surface of first semiconductor layer and impurity concentration is more than the first of first semiconductor layer The third semiconductor layer of conductivity type；And

It is arranged in first semiconductor layer and impurity concentration is slow more than the width of the first conductive type of first semiconductor layer Rush layer, and the width buffer layer has an impurities concentration distribution of mountain shape, the local maximum of the impurities concentration distribution is less than described the The impurity concentration of two semiconductor layers and the third semiconductor layer, and using the local maximum as peak value, have in the depth direction There is difference of height,

The electricalresistivityρ of wherein described first semiconductor layer₀Relative to rated voltage V₀Meet 0.12V₀≤ρ₀, 0.12 list here Position is Ω cm/V.

2. a kind of semiconductor devices, including：

The drift layer of the first conductive type；

Be arranged in a main surface of the drift layer and impurity concentration be more than the drift layer the second conductive type base stage Layer；

Be arranged in one main surface of the drift layer with contacted with the base layer and impurity concentration be more than the base The emitter layer of the first conductive type of pole layer；

The insulating film contacted with the drift layer, the base layer and the emitter layer；

The gate electrode adjacent with the drift layer, the base layer and the emitter layer across the insulating film；

Be arranged in another main surface of the drift layer and impurity concentration be more than the drift layer the second conductive type current collection Pole layer；And

Be arranged in the drift layer and impurity concentration be more than the drift layer the first conductive type wide buffer layer, and width delay Rushing layer, there is the impurities concentration distribution of mountain shape, the local maximum of the impurities concentration distribution to be less than the base layer and the current collection The impurity concentration of pole layer, and using the local maximum as peak value, there is difference of height in the depth direction,

The electricalresistivityρ of the wherein described drift layer₀Relative to rated voltage V₀Meet 0.12V₀≤ρ₀, 0.12 unit here is Ω cm/V。

3. a kind of semiconductor devices, including：

First semiconductor layer of the first conductive type；

It is arranged in first semiconductor layer and impurity concentration is multiple more than the first conductive type of first semiconductor layer Wide buffer layer, and multiple wide buffer layer has the impurities concentration distribution of mountain shape, the local maximum of the impurities concentration distribution small In the impurity concentration of second semiconductor layer and the third semiconductor layer, and using the local maximum as peak value, in depth There is difference of height on direction,

The multiple width buffer layer is set to from the different depth of another main surface,

The ratio γ of the sum of width of the multiple wide buffer layer and the thickness of first semiconductor layer, when be applied with level with The ratio of the sum of decline of electric field strength of the multiple wide buffer layer when the equal voltage of breakdown voltage and critical electric field strength The measured value of the donor concentrations of the substrate of rate η and formation first semiconductor layer and the deviation ratio α of standard value meet 4 α (γ/η)/[(2-α)(2+α)]<α。

4. a kind of semiconductor devices, including：

The drift layer of the first conductive type；

Be arranged in the drift layer and impurity concentration be more than the drift layer the first conductive type multiple wide buffer layers, and should Multiple width buffer layers have an impurities concentration distributions of mountain shape, the local maximum of the impurities concentration distribution be less than the base layer and The impurity concentration of the collector layer, and using the local maximum as peak value, there is difference of height in the depth direction,

The sum of width of the multiple width buffer layer with the ratio γ of the thickness of the drift layer, when being applied with level and breakdown potential The ratio η of the sum of decline of electric field strength of the multiple wide buffer layer when pressing equal voltage and critical electric field strength, with And form the measured value of the donor concentrations of the substrate of the drift layer and deviation ratio α 4 α of satisfaction (γ/η)/[(the 2- α) of standard value (2+α)]<α。

5. a kind of semiconductor devices, including：

First semiconductor layer of the first conductive type；

The width buffer layer causes donor to be formed by hydrogen,

The impurity for including in the third semiconductor layer is phosphorus,

Close to the wide buffer layer of the third semiconductor layer from the position of the central depths of first semiconductor layer Quantity is more than the quantity of the wide buffer layer close to second semiconductor layer from the position of the central depths, and from this The quantity that the position of heart depth is risen close to the wide buffer layer of second semiconductor layer is more than 0.

6. a kind of semiconductor devices, including：

The drift layer of the first conductive type；

Be arranged in another main surface of the drift layer and impurity concentration be more than the drift layer the second conductive type current collection Pole layer；

Setting contacted between the drift layer and the collector layer and in another main surface with the collector layer, And impurity concentration is less than the field barrier layer of the first conductive type of the collector layer；And

The width buffer layer causes donor to be formed by hydrogen,

The impurity for including in the field barrier layer is phosphorus,

The quantity of the wide buffer layer from the position of the central depths of the drift layer close to the collector layer is more than Close to the quantity of the wide buffer layer of the base layer from the position of the central depths, and from the position of the central depths Quantity close to the wide buffer layer of the base layer is more than 0.

7. such as semiconductor devices described in claim 5 or 6, which is characterized in that

The width of the impurities concentration distribution of the multiple width buffer layer becomes from another main surface to one main surface It is wide.

8. such as semiconductor devices described in claim 5 or 6, which is characterized in that

The adjacent wide respective impurity concentration of buffer layer reaches the interval of the position of the local maximum from described another Main surface broadens to one main surface.

9. the semiconductor devices as described in claim 1,3, any one of 5, which is characterized in that

The end of the depletion layer extended to one main surface when being applied with the level voltage equal with breakdown voltage is separate The third semiconductor layer.

10. the semiconductor devices as described in claim 2,4, any one of 6, which is characterized in that

The end of the depletion layer extended to one main surface when being applied with the level voltage equal with breakdown voltage is separate The collector layer.