CN106158928A - Semiconductor device and manufacture method thereof - Google Patents
Semiconductor device and manufacture method thereof Download PDFInfo
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- CN106158928A CN106158928A CN201510133571.7A CN201510133571A CN106158928A CN 106158928 A CN106158928 A CN 106158928A CN 201510133571 A CN201510133571 A CN 201510133571A CN 106158928 A CN106158928 A CN 106158928A
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- metal atom
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- crystal defect
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 87
- 229910001385 heavy metal Inorganic materials 0.000 claims abstract description 84
- 230000007547 defect Effects 0.000 claims abstract description 50
- 239000013078 crystal Substances 0.000 claims abstract description 47
- 238000009792 diffusion process Methods 0.000 claims description 17
- 239000010931 gold Substances 0.000 claims description 12
- 239000002245 particle Substances 0.000 claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 11
- 229910052737 gold Inorganic materials 0.000 claims description 11
- 230000001133 acceleration Effects 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 18
- 238000011084 recovery Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 230000008676 import Effects 0.000 description 5
- 230000000670 limiting effect Effects 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000002425 crystallisation Methods 0.000 description 4
- 230000008025 crystallization Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 230000002441 reversible effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000956 alloy Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/34—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being on the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/2225—Diffusion sources
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
Abstract
The embodiment of the present invention provides a kind of semiconductor device and manufacture method thereof, and this semiconductor device includes substrate, is formed with crystal defect in the superficial layer of described substrate；Wherein, described substrate is imported with heavy metal atom, and, the concentration of the described heavy metal atom in described crystal defect is higher than the concentration of the described heavy metal atom in other regions in described substrate.According to embodiments of the present invention, can be formed there is the semiconductor device of high switching speed and low forward voltage Vf.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of semiconductor device and manufacture method thereof.
Background technology
Semiconductor device is widely used in electronic equipment.Fast recovery diode (Fast Recovery Diode, FRD)
A kind of semiconductor device with characteristics such as switching characteristic are good, reverse recovery time is short, be mainly used in Switching Power Supply,
In the electronic circuits such as pulse-width modulator (Pulse Width Modulator, PWM), frequency converter, as high frequency
Commutation diode, fly-wheel diode or damper diode use.
Fig. 1 shows the structure of the fast recovery diode described in patent document 1 (the clear 63-119585A of TOHKEMY)
Schematic diagram, as it is shown in figure 1, have N+ diffusion layer 2, at N-type lining in the N-type substrate 1 of this fast recovery diode
The end, is formed p type diffused layer the 3rd, 3a, between p type diffused layer and N-type substrate, thus forms P-N junction, at N
The lower surface of the upper surface of type substrate 1 and N+ diffusion layer 2 is respectively formed with electrode 8a, 8b, and, this fast recovery
Diode also has gold diffusion district 6.
In patent document 1, by formation gold diffusion district 6, and control the degree of depth and shape, the energy of p type diffused layer
Enough reduce Trr reverse recovery time, forward voltage Vf and the reverse leakage current Ir of fast recovery diode.
It should be noted that to be intended merely to the introduction of technical background above convenient technical scheme is carried out clear,
Complete explanation, and facilitate the understanding of those skilled in the art to illustrate.Can not be merely because these schemes be at this
Bright background section is set forth and thinks that technique scheme is known to those skilled in the art.
Content of the invention
But, inventor finds, in patent document 1, gold atom even concentration in gold diffusion district 6, this can lead
Send a telegraph the resistance between 8a and 8b of pole to increase, thus increase forward voltage Vf, and therefore, it is very difficult to reach both to improve out
Close speed, reduce again the effect of forward voltage Vf.
The embodiment of the present invention provides a kind of semiconductor device and manufacture method thereof, is formed in the superficial layer of Semiconductor substrate
Crystal defect, adjusts heavy metal concentration distribution, can either improve the switching speed of semiconductor device, just can reduce again
To voltage Vf.
According to the first aspect of the embodiment of the present application, providing a kind of semiconductor device, described semiconductor device includes substrate,
The superficial layer of described substrate is formed with crystal defect；Wherein, described substrate is imported with heavy metal atom, and,
The concentration of the described heavy metal atom in described crystal defect is former higher than the described heavy metal in other regions in described substrate
The concentration of son.
According to the second aspect of the embodiment of the present application, wherein, described crystal defect is formed at relative two of described substrate
The superficial layer on individual surface.
According to the third aspect of the embodiment of the present application, wherein, described crystal defect is formed by particle-beam exposure, and
And, described crystal defect is formed at and plays in the depth bounds of 0.5 micron-30 microns from described substrate surface.
According to the fourth aspect of the embodiment of the present application, wherein, the district being imported with described heavy metal atom at described substrate
In territory, the concentration range of heavy metal atom is 1 × 1015atom/cm3-1×1018atom/cm3。
The 5th aspect according to the embodiment of the present application, wherein, described semiconductor device also includes that being formed at described crystallization lacks
The electrode on the surface falling into.
The 6th aspect according to the embodiment of the present application, wherein, described heavy metal atom is gold atom (Au) or pt atom
(Pt)。
The 7th aspect according to the embodiment of the present application, provides the manufacture method of a kind of semiconductor device, and described method includes:
Form crystal defect in the superficial layer of substrate；
Heavy metal atom is imported in described substrate；
Wherein, the concentration of the described heavy metal atom in described crystal defect is higher than other regions described in described substrate
The concentration of heavy metal atom.
According to the eighth aspect of the embodiment of the present application, wherein, particle ray is irradiated to the surface of described substrate, to be formed
Described crystal defect.
The 9th aspect according to the embodiment of the present application, wherein, irradiating the acceleration energy that described particle ray used is
3MeV-30MeV, the exposure dose of described particle ray is 1 × 1010atom/cm2-1×1013atom/cm2。
The tenth aspect according to the embodiment of the present application, wherein, imports described heavy metal atom in described substrate and includes:
Form the diffusion source of described heavy metal atom on relative two surface of described substrate or surface；And
The described heavy metal atom in described diffusion source is made to be diffused in described substrate.
The beneficial effects of the present invention is: the concentration of the heavy metal atom in the crystal defect of substrate surface layer is higher than substrate
In the concentration of heavy metal atom in other regions, thereby, it is possible to formed, there is high switching speed and low forward voltage Vf
Semiconductor device.
With reference to explanation hereinafter and accompanying drawing, disclose in detail only certain exemplary embodiments of this invention, specify the former of the present invention
Reason can be in adopted mode.It should be understood that embodiments of the present invention are not so limited in scope.?
In the range of the spirit and terms of claims, embodiments of the present invention include many changes, modifications and equivalent.
Describe for a kind of embodiment and/or the feature that illustrates can be in same or similar mode one or more
Other embodiments individual use, combined with the feature in other embodiments, or substitute in other embodiments
Feature.
It should be emphasized that term "comprises/comprising" refers to the existence of feature, one integral piece, step or assembly herein when using,
But it is not precluded from the existence of one or more further feature, one integral piece, step or assembly or additional.
Brief description
Included accompanying drawing is used for providing being further understood from the embodiment of the present invention, which constitutes the one of specification
Part, is used for illustrating embodiments of the present invention, and describes, with word, the principle coming together to explain the present invention.Aobvious and easy
Insight, the accompanying drawing in describing below is only some embodiments of the present invention, for those of ordinary skill in the art,
On the premise of not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.In the accompanying drawings:
Fig. 1 is the structural representation of the fast recovery diode of patent document 1；
Fig. 2 is the vertical section schematic diagram of the semiconductor device of embodiment 1；
Fig. 3 is the schematic diagram of the concentration of the heavy metal atom of embodiment 1 along substrate genesis analysis；
Fig. 4 is a schematic flow sheet of the manufacture method of the semiconductor device of embodiment 2；
Fig. 5 is the schematic flow sheet importing heavy metal atom in substrate of embodiment 2.
Detailed description of the invention
Referring to the drawings, by description below, the aforementioned and further feature of the present invention will be apparent from.In explanation
In book and accompanying drawing, specifically disclose only certain exemplary embodiments of this invention, which show and wherein can use that the present invention's is former
Some embodiments then, it will thus be appreciated that the invention is not restricted to described embodiment, on the contrary, bag of the present invention
Include whole modifications, modification and the equivalent falling within the scope of the appended claims.
In this application, for convenience of description, the surface arranging anode electrode (anode) of substrate is referred to as " upper table
The face relative with this " upper surface " of substrate is referred to as " lower surface " by face ", thus, " on " direction refers to from " lower surface "
Point to the direction of " upper surface ", D score direction with " on " in opposite direction, and, " on " direction and D score direction unite
It is referred to as longitudinally.In this application, the setting of "up" and "down" is comparatively speaking, merely to explanation is convenient, and not generation
The specifically used semiconductor device of table or orientation when manufacturing this semiconductor device.
Embodiment 1
The embodiment of the present invention 1 provides a kind of semiconductor device.Fig. 2 is the vertical section schematic diagram of this semiconductor device, as
Shown in Fig. 2, this semiconductor device 200 includes substrate 201, is formed with crystallization and lacks in the superficial layer of this substrate 201
Fall into 202.
In the present embodiment, substrate 201 can be imported with heavy metal atom, and, in crystal defect 202
The concentration of heavy metal atom is higher than the concentration of the heavy metal atom in other regions in substrate 201.
In the present embodiment, this semiconductor device 200 can include electrode 203, and this electrode 203 can be formed at knot
The surface of brilliant defect 202, and contact with the surface of crystal defect 202.
In the present embodiment, the concentration of the heavy metal atom in crystal defect is higher, and thus, electrode 202 lacks with crystallization
The contact site falling into 202 easily forms the stable alloy being made up of electrode material and heavy metal atom, thus reduces and connect
Get an electric shock and hinder so that reduce the forward voltage Vf of this semiconductor device.For example, the material at electrode 202 is aluminium (Al),
In the case that heavy metal is for gold (Au), easily form AuAl in this contact site2、Au5Al2Etc. stable alloy material
Material.
In the present embodiment, the concentration of the heavy metal atom in crystal defect is higher, thus, forms more deep energy level,
Shorten minority carrier lifetime, thus improve the switching speed of this semiconductor device.
In the present embodiment, in the region outside the crystal defect 202 of this substrate 201, the concentration of heavy metal atom is relatively
Low, thereby, it is possible to the resistance substrate that suppression causes due to heavy metal atom increases phenomenon, so that this semiconductor dress
Put and there is relatively low forward voltage Vf.
According to the present embodiment, the switching speed of semiconductor device can either be improved, forward voltage Vf can be reduced again.
In the present embodiment, this substrate 201 can be the conventional Semiconductor substrate of semiconductor applications, such as silicon substrate etc..
In the present embodiment, this crystal defect 202 can be formed by particle-beam exposure, for example, and this particle ray
Can be electron ray, hydrogen ion ray or helium ion irradiation etc..Irradiating the acceleration energy that this particle ray used can
Thinking 3MeV-30MeV, the exposure dose of this particle ray can be 1 × 1010atom/cm2-1×1013atom/cm2。
With the difference of the factors such as the species of ion irradiation, accelerating potential, exposure dose and irradiation time, the knot being formed
The degree of depth of brilliant defect 202 is also different, and for example, this crystal defect 202 can be formed at and play from the surface of substrate 201
In the depth bounds H of 0.5 micron-30 microns.
In the present embodiment, this crystal defect 202 can be respectively formed in the surface on relative two surface of substrate
Layer, as in figure 2 it is shown, crystal defect can be formed in the superficial layer of the upper and lower surface of substrate 201 respectively
202a、202b.But, the present embodiment is not limited to this, it is also possible to only forms crystallization in a surface of substrate and lacks
Fall into.
In the present embodiment, heavy metal atom can along the longitudinal direction of substrate, between crystal defect 202a and 202b with
The formal distribution that two ends concentration is high, intermediate concentration is low.Fig. 3 is the genesis analysis of the concentration of heavy metal atom along substrate
Schematic diagram, in figure 3, the longitudinal axis represents each region of substrate and the fore-and-aft distance of crystal defect 202b, and transverse axis represents
The concentration of heavy metal atom.As it is shown on figure 3, in crystal defect 202b, heavy metal atom is poly-at crystal defect
Collection, thus, the concentration of heavy metal atom is higher, and further away from crystal defect 202b, the concentration of heavy metal atom is lower,
After the concentration of heavy metal atom reaches minimum, the closer to crystal defect 202a, the concentration of heavy metal atom is got over
Height, in crystal defect 202a, heavy metal atom is assembled again, thus, the concentration of heavy metal atom becomes again
High value.Thus, in figure 3, the concentration of heavy metal atom is distributed in horizontal " U " font.
In the present embodiment, the concentration of the heavy metal atom of crystal defect 202a with 202b can be identical, but this enforcement
Example is not limited to this, and the concentration of the heavy metal atom of the two also can be different.
In the present embodiment, heavy metal atom has concentration distribution profile as shown in Figure 3, thus, crystal defect
Heavy metal atom concentration in 202a and 202b is higher than the heavy metal atom concentration in other regions in substrate, thus it is possible to
Enough improve the switching speed of semiconductor device, forward voltage Vf can be reduced again.
It should be noted that the concentration distribution profile of Fig. 3 is only citing, in the present embodiment, heavy metal atom also may be used
There being other concentration distribution profile, if can make the concentration of the heavy metal atom in crystal defect higher than in substrate other
The concentration of the heavy metal atom in region, for example, in the case that two electrodes are arranged on substrate same surface,
Heavy metal atom concentration can be made higher in the region with electrode contact for the substrate, and, make heavy metal in substrate former
The distance in the region with contacting with this in the vertical for the concentration of son increases and monotone decreasing.
In the present embodiment, in the region being imported with heavy metal atom of substrate 201, the concentration model of heavy metal atom
Enclosing can be 1 × 1015atom/cm3-1×1018atom/cm3.Certainly, the present embodiment is not limited to this, this concentration model
Enclose also can be other value.
In the present embodiment, this heavy metal atom can be for example gold atom (Au) or pt atom (Pt), but this reality
Execute example and be not limited to this, can also is that other heavy metal atom.
In the present embodiment, the quantity of electrode 203 can be two, and for example, this two electrodes can be respectively anode
(anode) 203a and negative electrode (cathode) 203b, and this two electrode 203a and 203b can lay respectively at
The surface of substrate crystal defect 202a and 202b.Thus, this semiconductor device can be formed as vertical structure.But,
The present embodiment is not limited to this, and the quantity of this electrode can be more than 1, or 3；Further, have 2
In the case of individual above electrode, this electrode of more than 2 also can be arranged on the same surface of substrate, thus, is somebody's turn to do
Semiconductor device can be formed as transversary, in addition it is also possible to partial electrode is arranged on the same surface of substrate, and will
Partial electrode is arranged on relative two surface of substrate.
In the present embodiment, this substrate 201 can also have field limiting ring (Field Limiting Ring, FLR),
Have field plate (Field Plate), equal potential belt (Equipotential-Ring, EQR) and raceway groove barrier layer (Channel
Stopper, CS) etc., this field limiting ring, field plate, equal potential belt and raceway groove barrier layer may be used for reducing semiconductor dress
Put the surface field of 200, and prevent from forming parasitic channel in surface of silicon.With regard to field limiting ring, field plate, equipotential
Ring and the explanation buying barrier layer, be referred to prior art, and the present embodiment repeats no more.
Embodiment 2
The embodiment of the present application 2 provides the manufacture method of a kind of semiconductor device, for manufacturing partly leading described in embodiment 1
Body device.
Fig. 4 is a schematic flow sheet of the manufacture method of the semiconductor device of the present embodiment.As shown in Figure 4, this system
The method of making includes:
S401, forms crystal defect in the superficial layer of substrate；
S402, imports heavy metal atom in substrate.
Additionally, in the present embodiment, the manufacture method of this semiconductor device can also include:
S403, at the table surface forming electrode of crystal defect.
In the present embodiment, the concentration of the heavy metal atom in crystal defect is former higher than the heavy metal in other regions in substrate
The concentration of son, has high switching speed and the semiconductor device of low forward voltage Vf thereby, it is possible to formed.
In the S401 of the present embodiment, the method irradiating particle ray to the surface of substrate can be used, form knot
Brilliant defect.For example, this particle ray can be electron ray, hydrogen ion ray or helium ion irradiation etc..Irradiate this grain
The acceleration energy that sub-ray is used can be 3MeV-30MeV, the exposure dose of this particle ray can be 1 ×
1010atom/cm2-1×1013atom/cm2.By adjust the species of ion irradiation, accelerating potential, exposure dose and
The factors such as irradiation time, the degree of depth of crystal defect 202 can be adjusted, and control the lattice in crystal defect 202
Degree of injury.
In the S402 of the present embodiment, the method from substrate surface diffusion can be used, in substrate, import heavy metal
Atom.For example, it is possible to arrange the diffusion source of heavy metal atom at substrate surface, and at a certain temperature, Jing Guoyi
The fixed time, heavy metal atom is made to diffuse in Semiconductor substrate.
It is in the present embodiment, corresponding with the distribution of the concentration of the semiconductor device structure of Fig. 2 and the heavy metal atom of Fig. 3,
The method that can use Fig. 5 imports heavy metal atom in substrate.As it is shown in figure 5, the method includes:
S501, in the diffusion source on relative two surface of substrate or a surface formation heavy metal atom；
S502, makes the heavy metal atom in diffusion source be diffused in substrate.
In step S501, by way of evaporation, the diffusion source of heavy metal atom can be formed on substrate 201 surface
For example, this diffusion source can be for example the layer gold that thickness range is 50 angstroms-5 microns.Certainly, the present embodiment is not limited to
This, the generation type in the diffusion source of heavy metal atom can be alternate manner, and its thickness also can be other values.
In step S502, the substrate being provided with diffusion source can be made to be at a temperature of certain, through certain time,
Making heavy metal atom be diffused in substrate, for example, this temperature can be 750 DEG C-1200 DEG C, and this time can be 60
Minute.It in a detailed description of the invention, is silicon substrate at substrate, in the case that heavy metal atom is gold, this step
Temperature in S502 can be 750 DEG C, and the time can be 60 minutes.
In the present embodiment, the concentration of the heavy metal atom shown in Fig. 3 can be reached according to step S501 and S502 to divide
Cloth.
It should be noted that the method shown in Fig. 5 is only a specific embodiment, the present embodiment is not limited to this,
Also other method can be used to import heavy metal atom in substrate, as long as the heavy metal atom in crystal defect can be made
Concentration higher than the concentration of the heavy metal atom in other regions in substrate.
In step S403, the method that semiconductor applications is conventional can be used to form electrode, for example with evaporated gold
Belong to layer and the mode of this metal level graphical forms electrode, it is, of course, also possible to use other method.Additionally, it is electric
The forming position of pole is referred to the explanation in embodiment 1, and here is omitted.
According to embodiments herein 2, the semiconductor dress with high switching speed and low forward voltage Vf can be formed
Put.
Above in association with specific embodiment, invention has been described, it will be appreciated by those skilled in the art that this
A little descriptions are all exemplary, are not limiting the scope of the invention.Those skilled in the art can be according to this
The present invention is made various variants and modifications by the spirit of invention and principle, and these variants and modifications are also in the scope of the present invention
In.
Claims (10)
1. a semiconductor device, it is characterised in that
Described semiconductor device includes substrate, is formed with crystal defect in the superficial layer of described substrate；
Wherein, described substrate is imported with heavy metal atom, and, the described heavy metal atom in described crystal defect
Concentration higher than the concentration of the described heavy metal atom in other regions in described substrate.
2. semiconductor device as claimed in claim 1, it is characterised in that
Described crystal defect is formed at the superficial layer on relative two surface of described substrate.
3. semiconductor device as claimed in claim 1, it is characterised in that
Described crystal defect is formed by particle-beam exposure, and, described crystal defect is formed at from described substrate table
Face is played in the depth bounds of 0.5 micron-30 microns.
4. semiconductor device as claimed in claim 1, it is characterised in that
In the region being imported with described heavy metal atom of described substrate, the concentration range of heavy metal atom is 1 ×
1015atom/cm3-1×1018atom/cm3。
5. semiconductor device as claimed in claim 1, it is characterised in that
Described semiconductor device also includes the electrode being formed at the surface of described crystal defect.
6. semiconductor device as claimed in claim 1, it is characterised in that
Described heavy metal atom is gold atom (Au) or pt atom (Pt).
7. the manufacture method of a semiconductor device, it is characterised in that described method includes:
Form crystal defect in the superficial layer of substrate；
Heavy metal atom is imported in described substrate；
Wherein, the concentration of the described heavy metal atom in described crystal defect is higher than other regions described in described substrate
The concentration of heavy metal atom.
8. the manufacture method of semiconductor device as claimed in claim 7, it is characterised in that
Irradiate particle ray to the surface of described substrate, to form described crystal defect.
9. the manufacture method of semiconductor device as claimed in claim 8, it is characterised in that
Irradiating the acceleration energy that described particle ray used is 3MeV-30MeV, the exposure dose of described particle ray
It is 1 × 1010atom/cm2-1×1013atom/cm2。
10. the manufacture method of semiconductor device as claimed in claim 7, it is characterised in that lead in described substrate
Enter described heavy metal atom to include:
Form the diffusion source of described heavy metal atom on relative two surface of described substrate or surface；And
The described heavy metal atom in described diffusion source is made to be diffused in described substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510133571.7A CN106158928B (en) | 2015-03-25 | 2015-03-25 | Semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
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| JP2011086883A (en) * | 2009-10-19 | 2011-04-28 | Denso Corp | Insulated gate bipolar transistor, and method for designing the same |
| CN102870201A (en) * | 2010-11-10 | 2013-01-09 | 丰田自动车株式会社 | Method of manufacturing semiconductor device |
| CN103035676A (en) * | 2011-09-28 | 2013-04-10 | 丰田自动车株式会社 | Semiconductor device and method for manufacturing the same |
| CN103872144A (en) * | 2014-03-06 | 2014-06-18 | 国家电网公司 | Soft fast recovery diode and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011086883A (en) * | 2009-10-19 | 2011-04-28 | Denso Corp | Insulated gate bipolar transistor, and method for designing the same |
| CN102870201A (en) * | 2010-11-10 | 2013-01-09 | 丰田自动车株式会社 | Method of manufacturing semiconductor device |
| CN103035676A (en) * | 2011-09-28 | 2013-04-10 | 丰田自动车株式会社 | Semiconductor device and method for manufacturing the same |
| CN103872144A (en) * | 2014-03-06 | 2014-06-18 | 国家电网公司 | Soft fast recovery diode and manufacturing method thereof |
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