CN106158890A - 影像感应器 - Google Patents

影像感应器 Download PDF

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CN106158890A
CN106158890A CN201510202825.6A CN201510202825A CN106158890A CN 106158890 A CN106158890 A CN 106158890A CN 201510202825 A CN201510202825 A CN 201510202825A CN 106158890 A CN106158890 A CN 106158890A
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dielectric layer
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image sensor
dielectric
active array
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CN106158890B (zh
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廖吉庆
赖宏岱
车行远
詹上毅
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Lijing Jicheng Electronic Manufacturing Co Ltd
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Powerchip Technology Corp
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Abstract

本发明公开一种影像感应器,包含有一半导体基底,其具有一主动阵列区以及一周边电路区;多个感光元件,设于该主动阵列区内的该半导体基底中;一第一介电层,位于该半导体基底上,覆盖该主动阵列区以及该周边电路区;以及一第二介电层,位于该第一介电层上,其中该第二介电层中具有一凹陷区域对应于该主动阵列区,显露出该第一介电层的上表面,且由该第二介电层的一侧壁所定义出来的该凹陷区域的周围与该第一介电层的该上表面具有一夹角,其中该夹角小于90度。

Description

影像感应器
技术领域
本发明涉及影像感应器(image sensor device)技术,特别是涉及一种CMOS影像感应器(CMOS image sensor,CIS)及其制作方法。
背景技术
CMOS影像感应器是本领域已知的影像感应技术,其具有主动元件,如晶体管,与每个像素相关联,因为与CMOS制作工艺相容,其优点是能够将信号处理和感测电路制作在同一个集成电路内。
CMOS影像感应器的感测单元通常由数个晶体管和一光二极管(photodiode)构成,其感光原理是将入射光线区分为各种不同波长光线的组合,例如红、蓝、绿三色,再分别由半导体基底上的多个感光元件予以接收,并将之转换为不同强弱的数字信号。
图1绘示的是现有CMOS影像感应器的剖面示意图。如图1所示,现有CMOS影像感应器包括一半导体基底10,在其主动阵列区101内设有多个感光元件110。在半导体基底10上依序沉积一第一介电层12、一第二介电层14以及一第三介电层16,其中第一介电层12覆盖主动阵列区101内的感光元件110以及周边电路区102的晶体管元件120,第二介电层14覆盖形成在第一介电层12上的金属内连线层140,而第三介电层16覆盖形成在第二介电层14上的金属内连线层160。
现有为了减少入射光线在光径上的减损,在沉积完第三介电层16后,会利用一光致抗蚀剂图案18,覆盖在第三介电层16上,再实施所谓的「峡谷(canyon)」蚀刻制作工艺,经由光致抗蚀剂图案18的开口18a所显露出的主动阵列区101内的第三介电层16表面,将第三介电层16蚀刻至一预定深度,但不会蚀穿第三介电层16或显露出下方的第二介电层14,如此于主动阵列区101正上方的第三介电层16中形成一凹陷区域21。
然而,上述现有技术的缺点在于「峡谷」蚀刻制作工艺会受到负载效应(loading effect)的影响,导致凹陷区域21的侧壁21a与凹陷区域21的底部21b之间的夹角θ1大于90度,如虚线圆圈处20所示。换言之,入射光线在进入主动阵列区101边缘角落处的感光元件110a之前,会通过比主动阵列区101中央更厚的第三介电层16,因此造成影像中央与角落有明显的明暗对比。
发明内容
本发明的目的在于提出一种改良的CMOS影像感应器及其制作方法,可以解决上述现有技术的不足与缺点。
为达上述目的,本发明于是提出一种影像感应器,包含有一半导体基底,其具有一主动阵列区以及一周边电路区;多个感光元件,设于该主动阵列区内的该半导体基底中;一第一介电层,位于该半导体基底上,覆盖该主动阵列区以及该周边电路区;以及一第二介电层,位于该第一介电层上,其中该第二介电层中具有一凹陷区域对应于该主动阵列区,显露出该第一介电层的上表面,且由该第二介电层的一侧壁所定义出来的该凹陷区域的周围与该第一介电层的该上表面具有一夹角,其中该夹角小于90度。
根据本发明实施例,该第一介电层及该第二介电层均为硅氧介电层。
根据本发明实施例,另有一第一金属内连线层,设于该半导体基底上,且该第一介电层覆盖该第一金属内连线层,一第二金属内连线层,设于该第一介电层上,且该第二介电层覆盖该第二金属内连线层。其中该第一金属内连线层与该第二金属内连线层设于该周边电路区。
为让本发明的上述目的、特征及优点能更明显易懂,下文特举优选实施方式,并配合所附的附图,作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用,并非用来对本发明加以限制者。
附图说明
图1为现有CMOS影像感应器的剖面示意图;
图2至图6为本发明实施例所绘示的制作影像感应器的方法示意图;
图7为本发明实施例所绘示的影像感应器的剖面示意图。
符号说明
1 影像感应器
10 半导体基底
12 介电层
14 介电层
16 第三介电层
18 光致抗蚀剂图案
18a 开口
20 虚线圆圈处
21 凹陷区域
21a 侧壁
21b 底部
30 牺牲介电层
32 牺牲层图案
32a 侧壁
32b 上表面
48 光致抗蚀剂图案
56 介电层
56a 侧壁
60 保护层
70 彩色滤光膜
80 微透镜结构
101 主动阵列区
102 周边电路区
110 感光元件
110a 感光元件
116 绝缘结构
120 晶体管元件
140 金属内连线层
160 金属内连线层
560 凹陷区域
θ1 夹角
θ2 夹角
θ3 夹角
具体实施方式
在下文中,将参照附图说明细节,该些附图中的内容也构成说明书细节描述的一部分,并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人士得以具以实施。当然,也可采行其他的实施例,或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此,下文的细节描述不应被视为是限制,反之,其中所包含的实施例将由随附的权利要求来加以界定。
文中所提及的「晶片」或「基底」等名称可以是在表面上已有材料层或集成电路元件层的半导体基材。基底也可以指在制作过程中的半导体基底或晶片,其上形成有不同材料层。举例而言,晶片或基底可以包括掺杂或未掺杂半导体、在绝缘材或半导体底材上形成的外延半导体、或其它已知的半导体结构。
请参阅图2至图6,其为依据本发明实施例所绘示的制作影像感应器的方法示意图,其中相同的区域、层或元件仍沿用相同的标号。首先,如图2所示,影像感应器1包括一半导体基底10,在其主动阵列区101内设有多个感光元件110,例如光二极管,彼此之间以绝缘结构116隔离。根据本发明实施例,影像感应器1可以是CMOS影像感应器。
在半导体基底10上依序沉积一介电层12以及一介电层14,其中介电层12覆盖主动阵列区101内的感光元件110以及周边电路区102的晶体管元件120,介电层14覆盖形成在介电层12上的金属内连线层140。根据本发明实施例,介电层12以及一介电层14均为透明的介电层,例如,硅氧介电层。
接着,在介电层14的上表面形成金属内连线层160,然后,在介电层14的上表面沉积一牺牲介电层30。根据本发明实施例,牺牲介电层30可以是氮氧化硅层、无定形碳(amorphous carbon)层或感光的高分子聚合物层,但不限于此。
如图3所示,接着于牺牲介电层30上形成一光致抗蚀剂图案48,使光致抗蚀剂图案48仅覆盖住主动阵列区101内的牺牲介电层30,而显露出主动阵列区101以外的牺牲介电层30。随即进行一蚀刻制作工艺,例如各向异性干蚀刻制作工艺,以光致抗蚀剂图案48作为蚀刻掩模,蚀刻被显露出来的牺牲介电层30,直到介电层14的部分上表面被显露出来,如此定义出一牺牲层图案32。
根据本发明实施例,牺牲层图案32的侧壁32a略微倾斜,而与介电层14的上表面具有一夹角θ2,且夹角θ2优选大于90度。再去除剩下的光致抗蚀剂图案48。
如图4所示,接着进行一化学气相沉积(CVD)制作工艺,例如,原子层沉积(ALD)制作工艺或者其它低温CVD制作工艺,在介电层14的上表面以及牺牲层图案32上沉积一介电层56,例如硅氧介电层。再施以平坦化制作工艺,例如化学机械研磨制作工艺或回蚀刻制作工艺,使牺牲层图案32的上表面32b被显露出来。
如图5所示,接着选择性的将牺牲层图案32移除,如此在介电层56中留下一凹陷区域560,并且显露出介电层14的部分上表面。根据本发明实施例,凹陷区域560的周围由介电层56的侧壁56a所定义出来,且侧壁56a与介电层14的上表面具有一夹角θ3,且夹角θ3优选小于90度。
如图6所示,在去除牺牲层图案32之后,可以选择继续于介电层56上以及凹陷区域560内共形的沉积一保护层60。当然,熟悉该项技术者应理解图6中的结构仅为半成品。
根据本发明另一实施例,如图7所示,可以继续于凹陷区域560内的介电层14的上表面依序形成一彩色滤光膜70以及微透镜结构80,如此即完成影像感测器1的后段制作工艺。由于彩色滤光膜制作工艺以及微透镜制作工艺都为现有,故其细节不再赘述。
本发明的主要特征在于凹陷区域560周围的介电层56的侧壁56a与介电层14的上表面具有一夹角θ3,且夹角θ3小于90度,可以有效避免现有技术中的「峡谷」蚀刻制作工艺面临的问题。此外,凹陷区域560显露出介电层14的上表面,这表示入射光线的光径上经过更少的介电层,而更能提高影像感应器的灵敏度。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。

Claims (13)

1.一种影像感应器,包含有:
半导体基底,其具有一主动阵列区以及一周边电路区;
多个感光元件,设于该主动阵列区内的该半导体基底中;
第一介电层,位于该半导体基底上,覆盖该主动阵列区以及该周边电路区;以及
第二介电层,位于该第一介电层上,其中该第二介电层中具有一凹陷区域对应于该主动阵列区,显露出该第一介电层的上表面,且由该第二介电层的一侧壁所定义出来的该凹陷区域的周围与该第一介电层的该上表面具有一夹角,其中该夹角小于90度。
2.如权利要求1所述的影像感应器,其中该第一介电层为硅氧介电层。
3.如权利要求1所述的影像感应器,其中该第二介电层为硅氧介电层。
4.如权利要求1所述的影像感应器,其中还包含有第一金属内连线层,设于该半导体基底上,且该第一介电层覆盖该第一金属内连线层。
5.如权利要求4所述的影像感应器,其中还包含有第二金属内连线层,设于该第一介电层上,且该第二介电层覆盖该第二金属内连线层。
6.如权利要求5所述的影像感应器,其中该第一金属内连线层与该第二金属内连线层设于该周边电路区。
7.一种影像感应器的制造方法,包含有:
提供一半导体基底,其具有一主动阵列区以及一周边电路区,并且具有多个感光元件设于该主动阵列区内;
在该半导体基底上形成一第一介电层,以覆盖该主动阵列区以及该周边电路区;
在对应该主动阵列区的该第一介电层上形成一牺牲层图案;
在未被该牺牲层图案覆盖的部分该第一介电层上形成一第二介电层;以及
移除该牺牲层图案以显露出部分该第一介电层。
8.如权利要求7所述的影像感应器的制造方法,其中形成该牺牲层图案的方法包含有:
在该第一介电层上形成一牺牲层;
在该牺牲层上形成一光致抗蚀剂图案;以及
进行一蚀刻制作工艺移除未被该光致抗蚀剂图案覆盖的部分该牺牲层。
9.如权利要求7所述的影像感应器的制造方法,其中该牺牲层图案包含一氮氧化硅层图案、一无定形碳层图案或者一感光的高分子聚合物层图案。
10.如权利要求7所述的影像感应器的制造方法,其中该牺牲层图案的侧壁与该第一介电层的表面具有一夹角,且该夹角大于90度。
11.如权利要求7所述的影像感应器的制造方法,其中形成该第二介电层的步骤包含一原子层沉积制作工艺或者一低温化学气相沉积制作工艺。
12.如权利要求7所述的影像感应器的制造方法,其中形成该第二介电层之后还包含一平坦化制作工艺,以移除该牺牲层图案上的部分该第二介电层。
13.如权利要求7所述的影像感应器的制造方法,其中移除该牺牲层图案之后还包含于显露出的部分该第一介电层上形成一彩色滤光膜以及一微透镜结构。
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