CN105575981A - 具有深阱结构的影像感应器及其制作方法 - Google Patents
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Abstract
本发明公开一种具有深阱结构的影像感应器及其制作方法。该影像感应器,包含有一半导体基材,具有一第一导电型,该基材上区分有多个感光区域,包括第一感光区域、第二感光区域及第三感光区域,分别对应于所述影像感应器的R像素、G像素及B像素;一绝缘结构,设于该半导体基材表面,分隔开该多个感光区域;一感光结构,设于各该多个感光区域内;以及一深阱结构,具有一第二导电型,其中该深阱结构仅与该第二、第三感光区域重叠,但是不重叠于该第一感光区域。
Description
技术领域
本发明涉及影像感应器(imagesensordevice)技术,特别是涉及一种具有深阱结构的CMOS影像感应器(CMOSimagesensor),能够降低像素间串扰(crosstalk),同时能改善量子效率(quantumefficiency)。
背景技术
CMOS主动像素感应器是本领域已知的技术。主动像素感应器指的是一电子影像感应器,具有主动元件,如晶体管,与每个像素相关联,因为与CMOS制作工艺相容,其优点是能够将信号处理和感测电路制作在同一个集成电路内。
上述CMOS主动像素感应器是通常由四个晶体管和一个“钉扎”光电二极管(pinnedphotodiode)构成。已知钉扎光电二极管在暗电流密度和图像迟滞方面表现佳,且对蓝光具有不错的颜色响应,其将二极管表面电势经由P+区“钉扎”于P阱或P基底(接地)而达到降低暗电流。
然而,上述CMOS主动像素感应器在远红外到红外波长范围内(波长从约700nm至约1mm)会遭遇灵敏性下降和串扰(crosstalk)增加等问题,主要是因为此波长范围的吸收深度大于像素深度许多。串扰增加是因为投射到图像感应器的光会深入至感应器的硅表面下方,并且在硅基底深处产生电子-空穴对。此深度远低于像素的收集范围,故光生载流子(photo-generatedcarriers)将自由地在所有方向上扩散。上述CMOS影像感应器在远红到红外波长范围的灵敏度降低的原因是,许多基底深处产生的载流子在基底内再结合而损失。
由此可知,该技术领域仍需要一种改良的影像感应器及其制作方法,其能够降低像素间串扰,同时能改善量子效率。
发明内容
为达上述目的,本发明于是提出一种影像感应器,包含有一半导体基材,具有一第一导电型,该基材上区分有多个感光区域,包括第一感光区域、第二感光区域及第三感光区域,分别对应于所述影像感应器的R像素、G像素及B像素;一绝缘结构,设于该半导体基材表面,分隔开该多个感光区域;一感光结构,设于各该多个感光区域内;以及一深阱结构,具有一第二导电型,其中该深阱结构仅与该第二、第三感光区域重叠,但是不重叠于该第一感光区域。
根据本发明实施例,该第一导电型为P型,该第二导电型为N型。
根据本发明实施例,该半导体基材包括一外延层。根据本发明实施例,该外延层为一P-外延硅层,成长于一P+硅基底上。
根据本发明实施例,该感光结构包含由一轻掺杂阱以及一重掺杂浅表层所构成的二极管结构。根据本发明实施例,该轻掺杂阱具有该第二导电型,而该重掺杂浅表层具有该第一导电型。
根据本发明实施例,还包含有一介电层,设于该半导体基材的表面上。根据本发明实施例,还包含有一彩色滤光膜以及一微透镜层,设于该介电层上。
为让本发明的上述目的、特征及优点能更明显易懂,下文特举优选实施方式,并配合所附的附图,作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用,并非用来对本发明加以限制者。
附图说明
图1为本发明实施例所绘示的影像感应器的剖面结构示意图;
图2为本发明实施例影像感应器的感光区域对应的R/G/B像素阵列;
图3至图6为本发明实施例所绘示的影像感应器的制作方法示意图。
符号说明
1影像感应器
10基材
11绝缘结构
12深阱结构
14轻掺杂阱
16重掺杂浅表层
21感光区域
22感光区域
23感光区域
30介电层
32金属内连线结构
40彩色滤光膜
41滤光区域
42滤光区域
43滤光区域
50微透镜层
51透镜区域
52透镜区域
53透镜区域
102光致抗蚀剂图案
104开口
120离子注入制作工艺
R红像素
G绿像素
B蓝像素
具体实施方式
在下文中,将参照附图说明细节,该些附图中的内容也构成说明书细节描述的一部分,并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人士得以具以实施。当然,也可采行其他的实施例,或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此,下文的细节描述不应被视为是限制,反之,其中所包含的实施例将由随附的权利要求来加以界定。
文中所提及的「晶片」或「基材」等名称可以是在表面上已有材料层或集成电路元件层的半导体基底,其中,基材可以被理解为包括半导体晶片。基材也可以指在制作过程中的半导体基底或晶片,其上形成有不同材料层。举例而言,晶片或基材可以包括掺杂或未掺杂半导体、在绝缘材或半导体底材上形成的外延半导体、或其它已知的半导体结构。
请参阅图1,其为依据本发明实施例所绘示的影像感应器的剖面结构示意图。如图1所示,本发明影像感应器1可以是一CMOS影像感应器,其制作于一基材10上,例如一半导体基材,其具有一第一导电型,例如,P型。根据本发明实施例,所述基材10还可以包括一外延层(图未示),例如,成长于一P+硅基底上的P-外延硅层,但不限于此。
根据本发明实施例,所述基材10上区分有多个感光区域21、22、23,且多个感光区域21、22、23分别对应于影像感应器1的R(红)像素、G(绿)像素及B(蓝)像素,并以图2中所示阵列排列。需注意,图2中所示R/G/B阵列仅为部分示意图,且本发明并不以此例示阵列为限。多个感光区域21、22、23彼此之间以绝缘结构11分隔开,例如,浅沟渠绝缘(STI)结构。
在靠近所述基材10的表面,各感光区域21、22、23内,还形成有感光结构,例如,由一轻掺杂阱14以及一重掺杂浅表层16所构成的二极管结构,其中,根据本发明实施例,所述轻掺杂阱14具有一第二导电型,而所述重掺杂浅表层16具有所述第一导电型。根据本发明实施例,所述第一导电型可以是P型,而所述第二导电型可以是N型。
熟悉该项技术者理解,本发明影像感应器1还可以包括晶体管结构,例如,选择晶体管(selecttransistor)、转移晶体管(transfertransistor)、重置晶体管(resettransistor)等等,但这些电路元件并未绘示于图中,以简化说明。
在所述基材10的表面上,形成有至少一介电层30。在所述介电层30内,还可以包含有金属内连线结构(图未示)。在所述介电层30上,则依序形成有一彩色滤光膜40以及一微透镜层50。其中,所述彩色滤光膜40同样以如图2所示的阵列方式排列,包括滤光区域41、42、43,其分别对应于感光区域21、22、23,而所述微透镜层50也是以阵列方式排列,包括透镜区域51、52、53,用以将光线分别集中于感光区域21、22、23内。由于彩色滤光膜40以及微透镜层50均为已知结构,其细节将不再详述。
本发明主要特征在于所述基材10内部,还包括一深阱结构12,其具有第二导电型,例如,N型。当从上往下看时,深阱结构12仅与感光区域22、23重叠,亦即,重叠于G(绿)像素及B(蓝)像素,但是对应于感光区域21,则没有深阱结构12与其重叠,如图2所示,深阱结构12刻意在感光区域21是打开的,此作法的优点是可以让波长较长的远红外到红外光在R(红)像素具有较深的吸收深度(adsorptiondepth),从而改善其量子效率。具有第二导电型的深阱结构12,其在操作时可以施加一正电压,例如,VCC电压,可以将引起串扰的电子排除。
请参阅图3至图6,其为依据本发明实施例所绘示的影像感应器的制作方法示意图。首先,如图3所示,提供一基材10,例如一半导体基材,其具有一第一导电型,例如,P型。根据本发明实施例,所述基材10还可以包括一外延层(图未示),例如,成长于一P+硅基底上的P-外延硅层,但不限于此。根据本发明实施例,所述基材10上区分有多个感光区域21、22、23,且多个感光区域21、22、23分别对应于影像感应器1的R(红)像素、G(绿)像素及B(蓝)像素,并以图2中所示阵列排列。
如图4所示,在基材10上形成一光致抗蚀剂图案102,其具有一开口104,显露出感光区域22、23,而遮盖住感光区域21。接着进行一离子注入制作工艺120,经由开口104将掺质,例如,N型掺质,植入到基材10内部,形成深阱结构12,其具有第二导电型,例如,N型。
如图5所示,接着在基材10上形成绝缘结构11,例如,浅沟渠绝缘(STI)结构。绝缘结构11分隔开多个感光区域21、22、23。然后,于感光区域21、22、23内形成感光结构,例如,由一轻掺杂阱14以及一重掺杂浅表层16所构成的二极管结构,其中,根据本发明实施例,所述轻掺杂阱14具有一第二导电型,例如N型,而所述重掺杂浅表层16具有所述第一导电型,例如P型。
如图6所示,接着于基材10的表面上,形成有至少一介电层30。在所述介电层30内,还可以包含有金属内连线结构32。在所述介电层30上,依序形成有一彩色滤光膜40以及一微透镜层50。其中,所述彩色滤光膜40同样以如图2所示的阵列方式排列,包括滤光区域41、42、43,其分别对应于感光区域21、22、23,而所述微透镜层50也是以阵列方式排列,包括透镜区域51、52、53,用以将光线分别集中于感光区域21、22、23内。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。
Claims (20)
1.一种影像感应器,包含有:
半导体基材,具有第一导电型,该基材上区分有多个感光区域;
绝缘结构,设于该半导体基材上,分隔开该多个感光区域;
感光结构,设于各该多个感光区域对应的该半导体基材内;以及
深阱结构,具有第二导电型,其中该深阱结构仅设于部分感光区域的该感光结构下方。
2.如权利要求1所述的影像感应器,其中该半导体基材包括一外延层。
3.如权利要求2所述的影像感应器,其中该外延层为一P_外延硅层,成长于一P+硅基底上。
4.如权利要求1所述的影像感应器,其中该第一导电型为P型,该第二导电型为N型。
5.如权利要求1所述的影像感应器,其中该感光结构包含由一轻掺杂阱以及一重掺杂浅表层所构成的二极管结构。
6.如权利要求5所述的影像感应器,其中该轻掺杂阱具有该第二导电型,而该重掺杂浅表层具有该第一导电型。
7.如权利要求1所述的影像感应器,其中还包含有介电层,设于该半导体基材的表面上。
8.如权利要求7所述的影像感应器,其中还包含有彩色滤光膜以及微透镜层,依序设于该介电层上。
9.如权利要求1所述的影像感应器,其中该多个感光区域包括第一感光区域、第二感光区域及第三感光区域,分别对应于所述影像感应器的R像素、G像素及B像素。
10.如权利要求9所述的影像感应器,其中该深阱结构仅设于该第二感光区域以及该第三感光区域的该感光结构下方。
11.一种影像感应器的制作方法,包含有:
提供一具有第一导电型的半导体基材,该基材上区分有多个感光区域;
在该半导体基材上形成一光致抗蚀剂层,该光致抗蚀剂层具有一开口以暴露部分感光区域;
进行一离子布置制作工艺,以于暴露的该部分感光区域对应的该半导体基材内形成一深阱结构,并且该深阱结构具有第二导电型;
在该半导体基材上形成多个绝缘结构,以分隔该多个感光区域;以及
在该多个感光区域对应的该半导体基材内分别形成一感光结构,其中该深阱结构设于该感光结构下方。
12.如权利要求11所述的影像感应器的制造方法,其中该半导体基材包括一外延层。
13.如权利要求12所述的影像感应器的制造方法,其中该外延层为一P_外延硅层,成长于一P+硅基底上。
14.如权利要求11所述的影像感应器的制造方法,其中该第一导电型为P型,该第二导电型为N型。
15.如权利要求11所述的影像感应器的制造方法,其中该感光结构包含由一轻掺杂阱以及一重掺杂浅表层所构成的二极管结构。
16.如权利要求15所述的影像感应器的制造方法,其中该轻掺杂阱具有该第二导电型,而该重掺杂浅表层具有该第一导电型。
17.如权利要求11所述的影像感应器的制造方法,其中于形成该感光结构之后还包含于该半导体基材的表面上形成一介电层。
18.如权利要求17所述的影像感应器的制造方法,还包含于该介电层上依序形成一彩色滤光膜以及一微透镜层。
19.如权利要求11所述的影像感应器的制造方法,其中该多个感光区域包括第一感光区域、第二感光区域及第三感光区域,分别对应于所述影像感应器的R像素、G像素及B像素。
20.如权利要求19所述的影像感应器,其中该深阱结构仅设于该第二感光区域以及该第三感光区域的该感光结构下方。
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CN111199988A (zh) * | 2018-11-16 | 2020-05-26 | 精準基因生物科技股份有限公司 | 子像素阵列以及图像传感器 |
CN111490058A (zh) * | 2019-01-28 | 2020-08-04 | 力晶科技股份有限公司 | 半导体组件及其制造方法 |
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US20050173742A1 (en) * | 2004-01-20 | 2005-08-11 | Kabushiki Kaisha Toshiba | Solid state image sensing device and method of manufacturing the same |
CN101872775A (zh) * | 2009-04-24 | 2010-10-27 | 美商豪威科技股份有限公司 | 用于减少串扰的多层图像传感器像素结构 |
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US20050173742A1 (en) * | 2004-01-20 | 2005-08-11 | Kabushiki Kaisha Toshiba | Solid state image sensing device and method of manufacturing the same |
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US20130122636A1 (en) * | 2010-10-05 | 2013-05-16 | Himax Imaging, Inc. | Method for forming an image sensing device |
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CN111199988B (zh) * | 2018-11-16 | 2022-11-25 | 精準基因生物科技股份有限公司 | 子像素阵列以及图像传感器 |
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