CN106100781B - Clock tracing method and system based on E1 passages - Google Patents
Clock tracing method and system based on E1 passages Download PDFInfo
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- CN106100781B CN106100781B CN201610345086.0A CN201610345086A CN106100781B CN 106100781 B CN106100781 B CN 106100781B CN 201610345086 A CN201610345086 A CN 201610345086A CN 106100781 B CN106100781 B CN 106100781B
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- H—ELECTRICITY
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- H04J3/00—Time-division multiplex systems
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- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0697—Synchronisation in a packet node
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Abstract
The present invention relates to a kind of clock tracing method and system based on E1 passages, the clock tracing method based on E1 passages comprises the following steps：When Synchronization Clock is completed to initialize, respectively according to default frequency source priority orders and default time source priority orders, effective frequency reference source and effective time reference source are obtained；When present clock period of supervision arrives, according to effective frequency reference source and effective time reference source, by calculating the clock jitter in acquisition Synchronization Clock between local clock and master clock；When clock jitter is more than corresponding predetermined deviation threshold value, the frequency and phase of local clock are adjusted, obtain real-time adjusted value；According to real-time adjusted value and default model fitting parameter, punctual Model Weight parameter tuning is carried out；According to the result of punctual Model Weight parameter tuning, clock tracing is carried out to local clock.The present invention can improve the reliability and precision of the whole network time synchronized.
Description
Technical field
The present invention relates to the intelligent substation of electric power system Clock Synchronization Technology field based on E1 passages, more particularly to one
Clock tracing method and system of the kind based on E1 passages.
Background technology
Intelligent substation electric power network technique is the main trend of following power network development, and it is with primary equipment intellectuality, secondary device
Networking, computer-aided traffic control etc. are essential characteristic.The collection of the next state of power system one is completed by distributed apparatus, and certain
A little secondary devices need the data of synchronization, therefore it is required that distributed apparatus synchronous work under a unified clock network
Make.
The precision and stability of time synchronized is to improve phasor and generator rotor angle dynamic monitoring, line fault ranging, unit and electricity
Network parameters verify the key factor of the degree of accuracy, are related to network stability control and accident is accurately analyzed, while are also to improve power network
The key factor of operational efficiency and reliability, it is the crucial requirement for adapting to the development such as UHV transmission, bulk power grid interconnection.Power network
Increasingly sophisticated and intelligentized continuous improvement, for being generated electricity in power network, transmit electricity, for power transformation and other all kinds of business, high accuracy,
The whole network unified time has turned into one of modernization necessary supporting method of power network.
In implementation process, inventor has found that at least there are the following problems in conventional art：Conventional art realizes power transformation
Time synchronized and its uniformly in standing, can not but realize the time unification of full electric network, cause the precision of the whole network time synchronized and reliable
Property is low.
The content of the invention
Based on this, it is necessary to the problem of can not realizing full electric network time unification for conventional art, there is provided one kind is based on E1
The clock tracing method and system of passage.
To achieve these goals, the embodiment of technical solution of the present invention is：
On the one hand, there is provided a kind of clock tracing method based on E1 passages, comprise the following steps：
When Synchronization Clock is completed to initialize, respectively according to default frequency source priority orders and default time
Source priority orders, obtain effective frequency reference source and effective time reference source；Default frequency source priority orders
Setting principle includes the highest priority of the 2MBITS frequency sources of E1 passages；The setting principle of default time source priority orders
The highest priority of PTP time sources including E1 passages；
When present clock period of supervision arrives, according to effective frequency reference source and effective time reference source, pass through
Calculate the clock jitter between local clock and master clock in acquisition Synchronization Clock；
When clock jitter is more than corresponding predetermined deviation threshold value, the frequency and phase of local clock are adjusted, obtained
To real-time adjusted value；
According to real-time adjusted value and default model fitting parameter, punctual Model Weight parameter tuning is carried out；
According to the result of punctual Model Weight parameter tuning, clock tracing is carried out to local clock.
On the other hand, there is provided a kind of clock tracing system based on E1 passages, including：
Obtain frequency reference source module, for Synchronization Clock complete initialize when, it is excellent according to default frequency source
First level order, obtains effective frequency reference source；The setting principle of default frequency source priority orders includes E1 passages
The highest priority of 2MBITS frequency sources；
Obtain time reference source module, for Synchronization Clock complete initialize when, it is excellent according to default time source
First level order, obtains effective time reference source；The setting principle of default time source priority orders includes the PTP of E1 passages
The highest priority of time source；
Deviation computing module, for when present clock period of supervision arrives, according to effective frequency reference source and effectively
Time reference source, pass through to calculate and obtain clock jitter between local clock and master clock in Synchronization Clock；
Adjusting module, for when clock jitter is more than corresponding predetermined deviation threshold value, to the frequency and phase of local clock
Position is adjusted, and obtains real-time adjusted value；
Parameter tuning module, for according to real-time adjusted value and default model fitting parameter, carrying out punctual Model Weight
Parameter tuning；
Clock tracking module, for the result according to punctual Model Weight parameter tuning, local clock is entered row clock with
Track.
Above-mentioned technical proposal has the advantages that：
Clock tracing method and system of the invention based on E1 passages, it is proposed that the reference source selecting party applied to E1 passages
The on-line study method of method and total factor parameter；By the system of selection applied to E1 passages, the group in clock external source is realized
Net configuration and reference source priority are set, it is ensured that the time consistency and frequency source precision of SDH network the whole network clockwork, are strengthened
The reliability and stability of intelligent substation；By the on-line study method of total factor parameter, during on-line operation, to temperature, fortune
The collective frequency of the factors such as row duration influences to carry out parameter tuning, improves the timekeeping performance of clock system；The invention enables intelligence
Each transformer station's clockwork in energy transformer station power network can share same set of master clock by corresponding network such as SDH network,
So as to realize the whole network time unification, pass through synchronous method proposed by the present invention, it is possible to increase the reliability of the whole network time synchronized and
Precision.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of the clock tracing embodiment of the method 1 of the invention based on E1 passages；
Fig. 2 is the synchronous overall frame of E1 channel times in the specific embodiment of clock tracing method one based on E1 passages of the invention
Frame schematic diagram；
Fig. 3 is that E1 channel time synchronization flows are shown in clock tracing method one specific embodiment of the invention based on E1 passages
It is intended to；
Fig. 4 is the structural representation of the clock tracing system embodiment 1 of the invention based on E1 passages.
Embodiment
For the ease of understanding the present invention, the present invention is described more fully below with reference to relevant drawings.In accompanying drawing
Give the preferred embodiment of the present invention.But the present invention can realize in many different forms, however it is not limited to this paper institutes
The embodiment of description.On the contrary, the purpose for providing these embodiments is made to the disclosure more thorough and comprehensive.
Unless otherwise defined, all of technologies and scientific terms used here by the article is with belonging to technical field of the invention
The implication that technical staff is generally understood that is identical.Term used in the description of the invention herein is intended merely to description tool
The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term as used herein " and/or " include one or more phases
The arbitrary and all combination of the Listed Items of pass.
Clock tracing embodiment of the method 1 of the invention based on E1 passages：
Full electric network time unification can not be realized in order to solve conventional art, causes the precision and reliability of the whole network time synchronized
The problem of low, the invention provides a kind of clock tracing embodiment of the method 1 based on E1 passages；Fig. 1 is led to for the present invention based on E1
The schematic flow sheet of the clock tracing embodiment of the method 1 in road；As shown in figure 1, it may comprise steps of：
Step S110：When Synchronization Clock is completed to initialize, respectively according to default frequency source priority orders and
Default time source priority orders, obtain effective frequency reference source and effective time reference source；Default frequency source is excellent
The setting principle of first level order includes the highest priority of the 2MBITS frequency sources of E1 passages；Default time source priority orders
Setting principle including E1 passages PTP time sources highest priority；
In a specific implementation, default frequency source priority orders can be E1 passages successively from high to low
2MBITS frequency sources, BDS frequency sources and GPS frequency source；Default time source priority orders can be E1 successively from high to low
PTP time sources, BDS time sources and the gps time source of passage；
Step S120：When present clock period of supervision arrives, joined according to effective frequency reference source and effective time
Source is examined, by calculating the clock jitter in acquisition Synchronization Clock between local clock and master clock；
In a wherein example, clock jitter can include phase deviation sequence and frequency departure；
Step S130：When clock jitter is more than corresponding predetermined deviation threshold value, the frequency and phase of local clock are entered
Row adjustment, obtains real-time adjusted value；
In a wherein example, predetermined deviation threshold value can include phase deviation queue thresholds and frequency departure threshold value；
Real-time adjusted value can include real-time frequency adjusted value and real-time phase adjusted value；
Step S140：According to real-time adjusted value and default model fitting parameter, punctual Model Weight parameter tuning is carried out；
In a specific example, it is whole that default model fitting parameter can include temperature frequency response model offline simulation
Determine parameter and aging frequency response model offline simulation setting parameter；
Step S150：According to the result of punctual Model Weight parameter tuning, clock tracing is carried out to local clock.
Specifically, the E1 passages in the present invention also refer to 30 tunnel pulse-code modulation PCM：Using synchronous time division multiplexing skill
30 voice channels and 2 control channels are compounded on 2.048Mbit/s IA High Speed Channel by art.It is (same in clock apparatus
Walk clock apparatus) after the completion of initialization, first judge the validity in frequency reference source, synchronised clock prioritizing selection comes from SDH
E1 (the 2Mbits signals, i.e., 2 megabits letters of (Synchronous Digital Hierarchy, SDH) network
Number) it is used as frequency source, frequency source priority orders：2M(E1)>BD>GPS>PTP(E1).Time source priority orders：E1 passages
Ground elapsed time signal PTP (E1) of transmission>BD>GPS, wherein BDS can refer to the Big Dipper (Chinese Beidou satellite navigation system：
BeiDou Navigation Satellite System)；GPS can refer to Global Positioning System, and (whole world is fixed
Position system)；PTP can refer to Precision Time Protocol (accurate clock synchronization protocol)；
1) the 2MBITS frequency source priority from E1 passages is arranged to highest, when being primarily due to it and coming from BITS
Clock, and BITS Clock Frequency Accuracy is higher.
2) the PTP time source priority from E1 passages is arranged to highest, primarily to ensuring the whole network clockwork
The source of time one cause property, i.e. its plastic source property.
The reference source system of selection of E1 passages in the embodiment of the present invention, precision and the more preferable reference source of stability is allowed to obtain
Higher priority, so a reference source will be preferentially chosen to be when reference source is simultaneously effective, clock is obtained more preferable benchmark,
So that phase and frequency are more accurate.Pass through the validity of the option and installment to reference source, greatly enhancing frequency reference source
And stability, and then fundamentally improve the synchronous accuracy of clock.
And in clock tames process (process for calculating clock jitter), respectively to local clock and master clock (SDH nets
Network master clock) between frequency departure and phase deviation sequence calculated；When phase deviation sequence and frequency departure are higher than pre-
During value of limiting, just enter horizontal phasing control and frequency adjustment, realize clock tracing.
In addition, it is using the purpose of total factor parameter on-line study method：Because clock individual has differences, and temperature
The frequency influence of aging action needs synthesis to adjust.In this case, using temperature-time linear weight analysis method.Transporting
During row, the frequency adjustment situation of real-time recording clock, temperature, duration, the sample space of actual frequency are established.It is punctual to start
Afterwards, that is, carry out weight parameter to adjust, and according to the temperature during punctual, duration, periodically adjust frequency values.Pass through on-line tuning
The weight of temperature, aging influence factor, the self-adaptive processing of clock individual is further completed, improve punctual reliable of clock
Property.
In a specific embodiment, step S120 can include step：
The data-signal sent to the SDH network equipment of E1 passages opposite end carries out Slicer amplitude limits and DPLL successively
(Digital Phase Locked Loop：Digital phase-locked loop) processing recover clock frequency, obtain effective clock jitter number
It is believed that number；
Low pass high-pass filtering and the processing of vector average value-based algorithm are carried out successively to the phase difference sequence of clock bias data signal,
Obtain phase deviation sequence；
According to once linear functional equation model, least square fitting is carried out to phase deviation sequence, it is inclined to obtain frequency
Difference.
Specifically, synchronised clock is in normal operating conditions, the data that E1 passages opposite end SDH network equipment is sent
Signal recovers clock jitter via after Slicer (limiter) amplitude limit by internal DPLL.When period of supervision starts, use
Least square method calculates frequency departure.I.e. during taming, after carrying out high pass, low-pass filtering treatment respectively to difference sequential value
Phase deviation sequence is asked for using vector average value filtering method；And once linear equation prototype is based on, using least square method
The slope of once linear equation is asked for, frequency departure is obtained after transformed.
In a specific embodiment, step can also be included after step S120：
Corresponding to being respectively less than in clock jitter during predetermined deviation threshold value, the data of store clock deviation；
Clock period of supervision is changed to 1.5 times of present clock period of supervision, calculating is passed back through and obtains synchronised clock
In device the step of clock jitter between local clock and master clock.
Specifically, when the frequency departure being calculated is smaller or is not enough to adjust clock crystal oscillator/rubidium clock, this week is retained
The clock bias data received in phase T, and 1.5T will be extended to the cycles, recalculate frequency departure after end cycle；It is on the contrary
Then recover period of supervision T.
During the clock based on E1 is tamed, it will usually such case occur：When clock frequency departure is smaller when in sync,
If investigated according to fixed cycle T, just occur that " previous cycle less stress, difference are accumulative；Latter cycle toning, phase shake
Swing " situation.After above-mentioned period of supervision adaptive clock frequency tracking week, taming effect can greatly be improved
Fruit.I.e. when E1 passages are normal, fixed for conventional period of supervision, cause frequency adjustment overshoot or the problem of less stress, carry out week
Phase online adaptive, self-adjusting, the limitation of fixed cycle frequency adjustment is made up, strengthen the stability of synchronised clock.
In a specific embodiment, step can also be included before step S110：
Run the temperature frequency One- place 2-th Order function response model of foundation at different temperatures according to Synchronization Clock, lead to
Cross least square method and carry out adjusting for model parameter, obtain temperature frequency response model offline simulation setting parameter；
Run the aging frequency logarithmic function curve response model of foundation at ambient temperature according to Synchronization Clock, lead to
Cross least square method and carry out adjusting for model parameter, obtain aging frequency response model offline simulation setting parameter.
Specifically, temperature-responsive test experiment method and parameter tuning method：Clock system is run at different temperatures,
The temperature frequency One- place 2-th Order function response model (parabola model) of constant-temperature crystal oscillator/rubidium clock is established, is entered using least square method
Row model parameter is adjusted.
Aging responds test experiment method and parameter tuning method：Clock system is run at ambient temperature, establishes constant temperature
The aging frequency logarithmic function curve response model of crystal oscillator/rubidium clock, adjusting for model parameter is carried out using least square method.
Above two method belongs to single factor test offline parameter setting method, it is therefore an objective to passes through temperature, operation duration single factor test
Clock frequency influences experimental method, parameter tuning method, builds temperature, the Ageing Model of clock.So that during on-line operation,
The collective frequency of temperature, operation duration can be influenceed be modeled and parameter tuning, improve the timekeeping performance of clock system.
In a specific embodiment, in the clock tracing embodiment of the method 1 of the invention based on E1 passages, synchronised clock
Device is the clock apparatus for being configured with multichannel 2MBITS interfaces；Multichannel 2MBITS interfaces include the E1 that at least 1 tunnel unidirectionally receives and connect
Mouthful；Master clock is SDH network master clock；Punctual Model Weight parameter tuning be according to default sample space establish based on
SVM (SVMs) weight parameter is adjusted.
Specifically, synchronised clock should configure multichannel 2M interfaces, wherein 1 tunnel is the E1 interfaces unidirectionally received, for obtaining
The 2Mbits frequency resources of LCN local communications network (SDH equipment).Other are two-way E1 interfaces, for ground elapsed time signal transduction chain road
Networking (reception and transmission that are used for landline time reference signal), to ensure the whole network time unification of SDH network.Should also
Configure the access of reference source GPS/BD wireless signals；
The reference source configuration and reference source system of selection of E1 passages i.e. proposed by the present invention, also referring to synchronised clock should
Multichannel 2M interfaces are configured, wherein 1 tunnel is the E1 interfaces unidirectionally received, for obtaining the 2Mbits of LCN local communications network (SDH equipment)
Frequency resource.Because reference source is directly from SDH network (reference clock is bits clocks), its frequency accuracy is higher；Further, since it is
The E1 interfaces unidirectionally received, on this one way link, SDH equipment will not factor data transmission and be adjusted, so as to ensure it
Precision, i.e., unidirectional E1 links do not transmit data, and carrier is not influenceed by transmitting, therefore the frequency essence that the frequency allocation method is brought
Degree and reliability are higher.
In the present invention, the temperature-time linear weight analysis method based on SVM can be used.In the process of running, it is real
When recording clock frequency adjustment situation, establish temperature, duration, the sample space of actual frequency.After punctual beginning, that is, carry out base
Adjusted in SVM weight parameter, and according to the temperature during punctual, duration, periodically adjust frequency values.
Clock tracing embodiment of the method 1 of the invention based on E1 passages, elaborate that the taming overall process of clock, including source are matched somebody with somebody
Put and selected with source, Frequency Synchronization/time synchronized and punctual parameter tuning method；The adaptive clock rate synchronization side of period of supervision
Method include E1 passages it is normal when, fixed for conventional period of supervision, cause frequency adjustment overshoot or the problem of less stress, carry out the cycle
Online adaptive, self-adjusting, the limitation of fixed cycle frequency adjustment is made up, strengthen the stability of synchronised clock；Single factor test is offline
Parameter tuning, total factor parameter on-line study method includes temperature, operation duration single factor test clock frequency influences experimental method, ginseng
Number setting method, build temperature, the Ageing Model of clock.During on-line operation, the collective frequency of temperature, operation duration is influenceed into
Row modeling and parameter tuning, improve the timekeeping performance of clock system；Reference source configuration and system of selection applied to E1 passages
Networking configuration and reference source priority method to set up including clock external source, it is ensured that the time of SDH network the whole network clockwork
Uniformity and frequency source precision, strengthen the reliability and stability of intelligent substation.The invention enables in intelligent substation power network
Each transformer station's clockwork same set of master clock can be shared by corresponding network such as SDH network, during so as to realize the whole network
Between it is unified, pass through synchronous method proposed by the present invention, it is possible to increase the reliability and precision of the whole network time synchronized.
Clock tracing method one specific embodiment of the invention based on E1 passages：
Based on the technical scheme of the above-mentioned clock tracing embodiment of the method 1 based on E1 passages, while in order to further detailed
The present invention is illustrated, spy illustrates technical scheme, Fig. 2 is based on for the present invention by taking SDH network master clock and E1 passages as an example
E1 channel times synchronization general frame schematic diagram in the specific embodiment of clock tracing method one of E1 passages；As shown in Figure 2：
The present invention using the clock of intelligent substation for investigation object, according in live actual motion as pair when system caused by
Clock synchronization issue, reliable solution method is proposed, provides the synchronization that intelligent substation clock system realizes the whole network time unification
Method,
Clock tracing method one specific embodiment of the invention based on E1 passages mainly may comprise steps of：
(1) the adaptive clock frequency tracking of period of supervision
Synchronised clock in normal operating conditions, by the data-signal that E1 passages opposite end SDH network equipment comes via
Clock frequency is recovered by internal DPLL after Slicer amplitude limits.When period of supervision T then, using least square method calculate frequency
Deviation.When the frequency departure being calculated is smaller or is not enough to adjust the demand of clock crystal oscillator/rubidium clock, retain in this cycle T
The data received, and 1.5T will be extended to the cycles, recalculate frequency departure after end cycle；It is on the contrary then recover period of supervision
T.After the clock frequency synchronization method of periodic time self-adapting, taming effect can be improved.
(2) single factor test offline parameter is adjusted, total factor parameter on-line study；
Temperature-responsive test experiment method and parameter tuning method：Clock system is run at different temperatures, establishes constant temperature
The temperature frequency One- place 2-th Order function response model (parabola model) of crystal oscillator/rubidium clock, model ginseng is carried out using least square method
Several adjusts.
Aging responds test experiment method and parameter tuning method：Clock system is run at ambient temperature, establishes constant temperature
The aging frequency logarithmic function curve response model of crystal oscillator/rubidium clock, adjusting for model parameter is carried out using least square method.
Total factor parameter on-line study method：Because clock individual has differences, and the frequency influence of aging at temperature factor
Synthesis is needed to adjust.In this case, using the temperature-time linear weight analysis method based on SVM.In the process of running,
The frequency adjustment situation of real-time recording clock, establishes temperature, duration, the sample space of actual frequency.After punctual beginning, that is, carry out
Weight parameter based on SVM is adjusted, and according to the temperature during punctual, duration, periodically adjusts frequency values.
(3) the reference source configuration and reference source selection of E1 passages
Synchronised clock should configure multichannel 2M interfaces, wherein 1 tunnel is the E1 interfaces unidirectionally received, for obtaining LCN local communications network
The 2Mbits frequency resources of (SDH equipment).Other are two-way E1 interfaces, (are used for for the road networking of ground elapsed time signal transduction chain
The reception and transmission of landline time reference signal), to ensure the whole network time unification of SDH network.Reference should also be configured
Source GPS/BD wireless signals access；
E1 (2M signal) of the synchronised clock prioritizing selection from SDH network is used as frequency source, frequency source priority orders：2M
(E1)>BD>GPS>PTP(E1).Time source priority orders：Ground elapsed time signal PTP (E1) of E1 channel transfers>BD>GPS；
During taming, frequency departure is carried out respectively and phase deviation sequence calculates；When phase deviation sequence is higher than some
During limit value, just enter horizontal phasing control.
Fig. 3 is that E1 channel time synchronization flows are shown in clock tracing method one specific embodiment of the invention based on E1 passages
It is intended to；As shown in figure 3, a kind of clock tracing method based on E1 passages of the present invention can comprise the steps：
(1) off-line learning, parameter tuning
1) temperature frequency response model parameter tuning；
Design temperature frequency response models prototype ft=AX2+ BX+C, the temperature frequency under different temperatures is collected in temperature control box
Rate sample data (Xi, fi), carried out curve fitting using least square method, obtain fitting parameter A, B, C.Wherein, ftRepresent temperature
The real-time frequency of response, i represent sample number, and X represents temperature, and A, B, C is fitting parameter.
2) aging frequency response model parameter tuning；
Set the aging response model prototype f of clock modulea=[a ln (bY+1)+c ln (dY+1)+1] f0；(at one
In specific example, f0Can be 10MHZ), the aging sample data (Y under different time node is collected in insulating boxi, fi), profit
Carried out curve fitting with least square method, obtain fitting parameter a, b, c, d；Wherein, f0On the basis of frequency, Y represent the time, i tables
Show sample number, a, b, c, d are fitting parameter.
(2) reference source selects；
After the completion of clock apparatus initialization, the validity in frequency reference source is first judged, and according to frequency source set in advance
Priority orders 2MBITS (E1)>BD>GPS selection frequency references source；Then according to time source priority orders set in advance
PTP(SDH)>BD>GPS selection time reference sources.
1) the 2MBITS frequency source priority of the unidirectional E1 links from E1 passages is arranged to highest, is primarily due to it
Come from BITS clocks；On the one hand, BITS Clock Frequency Accuracy is higher；On the other hand, unidirectional E1 links do not transmit data, carrier
Do not influenceed by transmitting.
2) the PTP time source priority from E1 passages is arranged to highest, primarily to ensuring the whole network clockwork
The source of time one cause property, i.e. its plastic source property.
(3) clock is tamed；
The initial tune clock cycle of constant-temperature crystal oscillator is 10S (second), rubidium clock 20S.During taming, to difference sequential value difference
Phase deviation sequence is asked for using vector average value filtering method after progress high pass, low-pass filtering treatment
Wherein,For phase deviation sequence, N is sequential value；Based on once linear equation prototype y=kx+b, (wherein x is time counting；
Y is instantaneous phase biased sequence；K is once linear function slope, has proportional relationship with frequency difference), asked using least square method
Slope k is taken, obtaining frequency departure after transformed isΔfFor frequency departure.
After clock lock, if difference hop value exceedes difference saltus step threshold valueWherein, VpvTo differ saltus step
Value,To differ saltus step threshold value；It can confirm that there occurs phase adjustment or saltus step for reference source；If now frequency source is
2MBITS (E1), then it is assumed that ΔfIt is credible, otherwise restart to count.
1) when phase deviation sequence(in a specific example, δpCan be 40ns, i.e. 40 nanoseconds；δpTo be inclined
Poor limit value), and Δf＜ δf(δfUnit is adjusted for the minimum frequency of constant-temperature crystal oscillator/rubidium clock) when, preserve phase deviation sequence Pei(i
=1,2...N), renewal period of supervision T '=1.5*T, continue the calculating of phase deviation sequence and frequency departure；
2) clock frequency Δ otherwise, is adjustedf, adjustment phase place
Preserve operation duration t, frequency adjusted value Δf, the mean temperature of the periodAs sample source data
(4) online keep time parameter tuning；
After the completion of clock is tamed, punctual parameter tuning is carried out, sample set is
WhereinFor the frequency adjusted value of ith,For the actual frequency values of ith.Clock module frequency synthesis mould
Type is：
F=ω1*ft+ω2*fa
=ω1*(AX2+BX+C)+ω2*[a ln(bY+1)+c ln(dY+1)+1]f0
After carrying out SVM study to sample set, respective weights apportioning cost ω is respectively obtained1, ω2, update ω1, ω2。
Clock source lose or without can use effective source after, according to interval time T=10min and frequency model f=ω1*ft+
ω2*faThe current frequency f in the case of not adjusting is calculated, considers and has adjusted frequencyCalculating should currently adjust
Whole frequency valuesLine frequency of going forward side by side adjusts.
Clock tracing system embodiment 1 of the invention based on E1 passages：
Full electric network time unification can not be realized in order to solve conventional art, causes the precision and reliability of the whole network time synchronized
The problem of low, while the technological thought based on the above method, present invention also offers a kind of clock tracing system based on E1 passages
System embodiment 1；Fig. 4 is the structural representation of the clock tracing system embodiment 1 of the invention based on E1 passages, as shown in figure 4, can
With including：
Frequency reference source module 410 is obtained, for when Synchronization Clock is completed to initialize, according to default frequency source
Priority orders, obtain effective frequency reference source；The setting principle of default frequency source priority orders includes E1 passages
The highest priority of 2MBITS frequency sources；
In a specific example, default frequency source priority orders can be E1 passages successively from high to low
2MBITS frequency sources, BDS frequency sources and GPS frequency source；
Time reference source module 420 is obtained, for when Synchronization Clock is completed to initialize, according to default time source
Priority orders, obtain effective time reference source；The setting principle of the default time source priority orders leads to including E1
The highest priority of the PTP time sources in road；
In a specific example, default time source priority orders can be the PTP of E1 passages successively from high to low
Time source, BDS time sources and gps time source；
Deviation computing module 430, for when present clock period of supervision arrives, according to effective frequency reference source and having
The time reference source of effect, by calculating the clock jitter in acquisition Synchronization Clock between local clock and master clock；
In a specific example, clock jitter can include phase deviation sequence and frequency departure；
Adjusting module 440, for when clock jitter is more than corresponding predetermined deviation threshold value, frequency to local clock and
Phase is adjusted, and obtains real-time adjusted value；
In a specific example, predetermined deviation threshold value can include phase deviation queue thresholds and frequency departure threshold value；
Real-time adjusted value can include real-time frequency adjusted value and real-time phase adjusted value；
Parameter tuning module 450, for according to real-time adjusted value and default model fitting parameter, carrying out punctual model power
Weight parameter tuning；
In a specific example, it is whole that default model fitting parameter can include temperature frequency response model offline simulation
Determine parameter and aging frequency response model offline simulation setting parameter；
Clock tracking module 460, for the result according to punctual Model Weight parameter tuning, row clock is entered to local clock
Tracking.
In a specific embodiment, deviation computing module 430 can include：
Data-signal module 432, the data-signal for being sent to the SDH network equipment of E1 passages opposite end enter successively
Row amplitude limit and DPLL processing, obtain clock bias data signal；
Phase deviation computing module 434, for carrying out low pass high pass successively to the phase difference sequence of clock bias data signal
Filtering and the processing of vector average value-based algorithm, obtain phase deviation sequence；
Frequency departure calculates module 436, for according to once linear functional equation model, being carried out most to phase deviation sequence
Small square law fitting, obtains frequency departure.
In a specific embodiment, the clock tracing system embodiment 1 of the invention based on E1 passages can also include：
Memory module 470, for clock jitter be respectively less than corresponding to predetermined deviation threshold value when, the number of store clock deviation
According to；
Cycle module 480 is changed, for when clock jitter is respectively less than corresponding predetermined deviation threshold value, clock to be investigated into week
Phase is changed to 1.5 times of present clock period of supervision.
In a specific embodiment, the clock tracing system embodiment 1 of the invention based on E1 passages can also include：
Temperature parameter adjusts module 490, for running the temperature frequency of foundation at different temperatures according to Synchronization Clock
Rate One- place 2-th Order function response model, adjusting for model parameter is carried out by least square method, obtains temperature frequency response model
Offline simulation setting parameter；
Ageing parameter adjusts module 492, for running the aging frequency of foundation at ambient temperature according to Synchronization Clock
Rate logarithmic function curve response model, adjusting for model parameter is carried out by least square method, obtains aging frequency response model
Offline simulation setting parameter.
In a specific embodiment, synchronised clock in the clock tracing system embodiment 1 of the invention based on E1 passages
Device is the clock apparatus for being configured with multichannel 2MBITS interfaces；Multichannel 2MBITS interfaces include the E1 that at least 1 tunnel unidirectionally receives and connect
Mouthful；Master clock is SDH network master clock；Punctual Model Weight parameter tuning be according to default sample space establish based on
SVM weight parameter is adjusted.
Clock tracing system embodiment 1 of the invention based on E1 passages, elaborate that the taming overall process of clock, including source are matched somebody with somebody
Put and selected with source, Frequency Synchronization/time synchronized and punctual parameter tuning method；The adaptive clock rate synchronization side of period of supervision
Method include E1 passages it is normal when, fixed for conventional period of supervision, cause frequency adjustment overshoot or the problem of less stress, carry out the cycle
Online adaptive, self-adjusting, the limitation of fixed cycle frequency adjustment is made up, strengthen the stability of synchronised clock；Single factor test is offline
Parameter tuning, total factor parameter on-line study method includes temperature, operation duration single factor test clock frequency influences experimental method, ginseng
Number setting method, build temperature, the Ageing Model of clock.During on-line operation, the collective frequency of temperature, operation duration is influenceed into
Row modeling and parameter tuning, improve the timekeeping performance of clock system；Reference source configuration and system of selection applied to E1 passages
Networking configuration and reference source priority method to set up including clock external source, it is ensured that the time of SDH network the whole network clockwork
Uniformity and frequency source precision, strengthen the reliability and stability of intelligent substation.The invention enables in intelligent substation power network
Each transformer station's clockwork same set of master clock can be shared by corresponding network such as SDH network, during so as to realize the whole network
Between it is unified, pass through synchronous method proposed by the present invention, it is possible to increase the reliability and precision of the whole network time synchronized.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope that this specification is recorded all is considered to be.
Embodiment described above only expresses the several embodiments of the present invention, and its description is more specific and detailed, but simultaneously
Can not therefore it be construed as limiting the scope of the patent.It should be pointed out that come for one of ordinary skill in the art
Say, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
- A kind of 1. clock tracing method based on E1 passages, it is characterised in that comprise the following steps：It is excellent according to default frequency source priority orders and default time source respectively when Synchronization Clock is completed to initialize First level order, obtains effective frequency reference source and effective time reference source；The default frequency source priority orders Setting principle includes the highest priority of the 2MBITS frequency sources of E1 passages；The setting of the default time source priority orders Principle includes the highest priority of the PTP time sources of E1 passages；When present clock period of supervision arrives, according to the effective frequency reference source and the effective time reference source, By calculating the clock jitter in the acquisition Synchronization Clock between local clock and master clock；When the clock jitter is more than corresponding predetermined deviation threshold value, the frequency and phase of the local clock are adjusted It is whole, the real-time adjusted value after being adjusted；According to adjusted value and the default model fitting parameter in real time, punctual Model Weight parameter tuning is carried out；According to the result of the punctual Model Weight parameter tuning, clock tracing is carried out to the local clock；Before the step of obtaining effective frequency reference source and effective time reference source, in addition to step：Run the temperature frequency One- place 2-th Order function response model of foundation at different temperatures according to the Synchronization Clock, lead to Cross least square method and carry out adjusting for model parameter, obtain temperature frequency response model offline simulation setting parameter；Run the aging frequency logarithmic function curve response model of foundation at ambient temperature according to the Synchronization Clock, lead to Cross least square method and carry out adjusting for model parameter, obtain aging frequency response model offline simulation setting parameter.
- 2. the clock tracing method according to claim 1 based on E1 passages, it is characterised in that investigate week in present clock When phase arrives, according to the effective frequency reference source and the effective time reference source, the synchronization is obtained by calculating Include in clock apparatus the step of clock jitter between local clock and master clock：Carry out Slicer amplitude limits successively to the data-signal that the SDH network equipment of E1 passages opposite end is sent and DPLL processing is extensive Appear again clock frequency, obtain effective clock bias data signal；Low pass high-pass filtering and the processing of vector average value-based algorithm are carried out successively to the phase difference sequence of the clock bias data signal, Obtain phase deviation sequence；According to once linear functional equation model, least square fitting is carried out to the phase deviation sequence, it is inclined to obtain frequency Difference；Wherein, the clock jitter includes the phase deviation sequence and the frequency departure；The predetermined deviation threshold value includes Phase deviation queue thresholds and frequency departure threshold value；The adjusted value in real time includes real-time frequency adjusted value and real-time phase adjusts Value.
- 3. the clock tracing method according to claim 1 based on E1 passages, it is characterised in that the clock is inclined obtaining After difference, in addition to step：When the clock jitter is less than the corresponding predetermined deviation threshold value, the data of the clock jitter are stored；Clock period of supervision is changed to 1.5 times of the present clock period of supervision, calculating is passed back through and obtains the synchronization In clock apparatus the step of clock jitter between local clock and master clock.
- 4. the clock tracing method according to claim 1 based on E1 passages, it is characterised in thatThe default model fitting parameter includes the temperature frequency response model offline simulation setting parameter and the aging Frequency response models offline simulation setting parameter.
- 5. the clock tracing method based on E1 passages according to Claims 1-4 any one, it is characterised in that described Synchronization Clock is to be configured with the clock apparatus of multichannel 2MBITS interfaces；It is single that the multichannel 2MBITS interfaces include at least 1 tunnel To the E1 interfaces of reception；The master clock is SDH network master clock；The punctual Model Weight parameter tuning is according to default The weight parameter based on SVM that sample space is established is adjusted.
- A kind of 6. clock tracing system based on E1 passages, it is characterised in that including：Obtain frequency reference source module, for Synchronization Clock complete initialize when, according to default frequency source priority Sequentially, effective frequency reference source is obtained；The setting principle of the default frequency source priority orders includes E1 passages The highest priority of 2MBITS frequency sources；Obtain time reference source module, for Synchronization Clock complete initialize when, according to default time source priority Sequentially, effective time reference source is obtained；The setting principle of the default time source priority orders includes the PTP of E1 passages The highest priority of time source；Deviation computing module, for when present clock period of supervision arrives, according to the effective frequency reference source and described Effective time reference source, the clock obtained by calculating in the Synchronization Clock between local clock and master clock are inclined Difference；Adjusting module, for when the clock jitter is more than corresponding predetermined deviation threshold value, to the frequency of the local clock It is adjusted with phase, obtains real-time adjusted value；Parameter tuning module, for according to adjusted value and the default model fitting parameter in real time, carrying out punctual Model Weight Parameter tuning；Clock tracking module, for the result according to the punctual Model Weight parameter tuning, when being carried out to the local clock Clock tracks；Also include：Temperature parameter adjusts module, for running the temperature frequency one of foundation at different temperatures according to the Synchronization Clock First quadratic function response model, adjusting for model parameter is carried out by least square method, it is offline to obtain temperature frequency response model It is fitted setting parameter；Ageing parameter adjusts module, for running the aging frequency pair of foundation at ambient temperature according to the Synchronization Clock Number function curve response model, adjusting for model parameter is carried out by least square method, it is offline to obtain aging frequency response model It is fitted setting parameter.
- 7. the clock tracing system according to claim 6 based on E1 passages, it is characterised in that the deviation computing module Including：Data-signal module, the data-signal for being sent to the SDH network equipment of E1 passages opposite end carry out amplitude limit successively With DPLL processing, clock bias data signal is obtained；Phase deviation computing module, for carrying out low pass high-pass filtering successively to the phase difference sequence of the clock bias data signal With the processing of vector average value-based algorithm, phase deviation sequence is obtained；Frequency departure calculates module, for according to once linear functional equation model, being carried out to the phase deviation sequence minimum Square law is fitted, and obtains frequency departure；Wherein, the clock jitter includes the phase deviation sequence and the frequency departure；The predetermined deviation threshold value includes Phase deviation queue thresholds and frequency departure threshold value；The adjusted value in real time includes real-time frequency adjusted value and real-time phase adjusts Value.
- 8. the clock tracing system according to claim 6 based on E1 passages, it is characterised in that also include：Memory module, for when the clock jitter is less than the corresponding predetermined deviation threshold value, storing the clock jitter Data；Cycle module is changed, for when the clock jitter is less than the corresponding predetermined deviation threshold value, clock to be investigated into week Phase is changed to 1.5 times of the present clock period of supervision.
- 9. the clock tracing system according to claim 6 based on E1 passages, it is characterised in that the default model is intended Closing parameter includes the temperature frequency response model offline simulation setting parameter and the aging frequency response model offline simulation Setting parameter.
- 10. the clock tracing system based on E1 passages according to claim 6 to 9 any one, it is characterised in that described Synchronization Clock is to be configured with the clock apparatus of multichannel 2MBITS interfaces；It is single that the multichannel 2MBITS interfaces include at least 1 tunnel To the E1 interfaces of reception；The master clock is SDH network master clock；The punctual Model Weight parameter tuning is according to default The weight parameter based on SVM that sample space is established is adjusted.
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| CN110109342B (en) * | 2018-02-01 | 2024-05-14 | 深圳市英特瑞半导体科技有限公司 | Crystal oscillator frequency time keeping method and time keeping equipment |
| CN110413042B (en) * | 2019-07-30 | 2020-08-14 | 上海东土远景工业科技有限公司 | Clock server, and time keeping frequency compensation method and device |
| CN111130676B (en) * | 2019-12-02 | 2022-06-28 | 上海赫千电子科技有限公司 | Time synchronization correction method and device applied to master clock and slave clock |
| CN112838861B (en) * | 2020-12-31 | 2022-08-26 | 广东大普通信技术股份有限公司 | Clock locking method, device, equipment and storage medium |
| CN115344008B (en) * | 2021-05-13 | 2024-05-07 | 中国科学院沈阳自动化研究所 | High-reliability time keeping method for cooperative application of multiple controllers |
| CN115102657B (en) * | 2022-06-29 | 2024-01-26 | 中国电力科学研究院有限公司 | Clock frequency synchronization method and device of metering device and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004221952A (en) * | 2003-01-15 | 2004-08-05 | Fujitsu Ltd | Transmission method and transmitter |
| CN101795214A (en) * | 2010-01-22 | 2010-08-04 | 华中科技大学 | Behavior-based P2P detection method under large traffic environment |
| CN102237941A (en) * | 2010-04-28 | 2011-11-09 | 中兴通讯股份有限公司 | Time synchronization system and method |
| CN104049525A (en) * | 2014-03-24 | 2014-09-17 | 成都可为科技发展有限公司 | Method for eliminating phase differences between multiple time input sources in clock |
| CN104375414A (en) * | 2014-11-14 | 2015-02-25 | 国家电网公司 | Time consuming device time service method and device based on multiple time sources |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103905136A (en) * | 2012-12-26 | 2014-07-02 | 中兴通讯股份有限公司 | Time synchronization processing method and device |
-
2016
- 2016-05-20 CN CN201610345086.0A patent/CN106100781B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004221952A (en) * | 2003-01-15 | 2004-08-05 | Fujitsu Ltd | Transmission method and transmitter |
| CN101795214A (en) * | 2010-01-22 | 2010-08-04 | 华中科技大学 | Behavior-based P2P detection method under large traffic environment |
| CN102237941A (en) * | 2010-04-28 | 2011-11-09 | 中兴通讯股份有限公司 | Time synchronization system and method |
| CN104049525A (en) * | 2014-03-24 | 2014-09-17 | 成都可为科技发展有限公司 | Method for eliminating phase differences between multiple time input sources in clock |
| CN104375414A (en) * | 2014-11-14 | 2015-02-25 | 国家电网公司 | Time consuming device time service method and device based on multiple time sources |
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Effective date of registration: 20210803 Address after: 510663 3 building, 3, 4, 5 and J1 building, 11 building, No. 11, Ke Xiang Road, Luogang District Science City, Guangzhou, Guangdong. Patentee after: China South Power Grid International Co.,Ltd. Patentee after: WUHAN ZHONGYUAN HUADIAN SCIENCE & TECHNOLOGY Co.,Ltd. Patentee after: ELECTRIC POWER RESEARCH INSTITUTE, GUIZHOU POWER GRID Co.,Ltd. Patentee after: ELECTRIC POWER SCIENCE & RESEARCH INSTITUTE OF GUANGXI POWER GRID Corp. Address before: 510080 water Donggang 8, Dongfeng East Road, Yuexiu District, Guangzhou, Guangdong. Patentee before: POWER GRID TECHNOLOGY RESEARCH CENTER. CHINA SOUTHERN POWER GRID Patentee before: China South Power Grid International Co.,Ltd. Patentee before: WUHAN ZHONGYUAN HUADIAN SCIENCE & TECHNOLOGY Co.,Ltd. Patentee before: ELECTRIC POWER RESEARCH INSTITUTE, GUIZHOU POWER GRID Co.,Ltd. Patentee before: ELECTRIC POWER SCIENCE & RESEARCH INSTITUTE OF GUANGXI POWER GRID Corp. |