CN104601317B - A kind of FPGA Synchronization Clock and its control method - Google Patents
A kind of FPGA Synchronization Clock and its control method Download PDFInfo
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Abstract
The present invention provides a kind of FPGA Synchronization Clock and its control method, and Synchronization Clock includes：When source unit, internal clock unit, signal output unit and Duo Shi sources sliding steps switch unit；And when source unit include the connection of reference source selecting module, the connection of reference source selecting module exports source sliding steps switch unit when at most according to the optimal time source of predetermined method choice；Internal clock unit, can for when source unit reference source selecting module reference time signal is provided, and pulse signal can also be provided for signal output unit and Duo Shi sources sliding steps switch unit；When more source sliding steps switch unit when source signal transmittance process in and/or different time source switch when, in time correction output to signal output unit signal.Can so automatically select optimal time source, and when source signal transmittance process in and/or different time source handoff procedure in, the when source signals of output unit needs can be constantly updated by correction module.
Description
Technical field
The present invention relates to the Synchronization Clock of FPGA a kind of and its control method, more particularly to it is monolithic FPGA synchronization
Clock apparatus and its control method.
Background technology
With the development of power automation technology, the precision when requirement to Synchronization Clock has not only rested on pair
On requirement on, while require that it has more preferable stability.Further improve and require, Synchronization Clock should possess and can manage
Property.Source switches and kept time in precision when stability is mainly reflected in more, generally, requires gradually to approach it when source switches when more
Adjusted value, slide the μ s/s of stepping 0.2；It is required that continuously punctual 12 hours, punctual precision is better than 1 μ s/h.
The Synchronization Clock technology of correlation is disclosed in the prior art, such as CN102540902A discloses a kind of Dan Ping
Platform multi-sensor information integration processor and experimental system, it discloses a kind of single platform multi-sensor information integration processor and reality
Check system, single platform multi-sensor information integration processor include communication module, control module, use processing module and electricity
Source module.Experimental system includes single platform multi-sensor information integration processor equipment and a computer, passes through between the two
USB data line is connected, and completes the interaction of data.The present invention can simulate the terminal guidance process of multiple control and guide ammunition, including
Small time of the target seeker for the terminal guidance being made up of the digital guiding head servo-drive system and multi-sensor information integration processor of computer
Road and the guided missile and target relative movement being made up of the comprehensive control computer of missile-borne and multi-sensor information integration processor of computer
Big loop is controlled, the algorithm of use processing can be emulated in real time, and can be by computer to result
Carry out Real time displaying.CN102593955B discloses a kind of comprehensive intelligent time frequency test system and method for testing, its
System includes GPS/ Beidou antennas receiver, the supervisor provided with database and testing results analysis management program and led to respectively
Cross communication link connection management machine realize program control time and frequency standard source and timing pulse, standard frequency, IRIG-B codes,
NTP/SNTP messages, PTP message test equipments.Provided with Intelligent time frequency signal switcher, the program control of supervisor passes through test
Analysis management program is realized, program control switching is carried out respectively by Intelligent time frequency signal switcher, during for comprehensive intelligent
Between frequency test.Can be easy and effectively tested time synchronism equipment is carried out in the case of without manual intervention
Effective intelligent comprehensive test, intellectuality, the mark of time synchronism equipment complicated business function and performance test are improved conscientiously
Standardization, systematization are horizontal, and test performance is more accurate, and testing efficiency is higher, and the testing time greatly shortens.CN203416271U is public
Optimal time sychronisation in source when having opened a kind of more, it includes at least two structure identical units, and the whole world is fixed in each unit
Position system ground receiver is connected with counter, and counter is also connected with the comparator in the unit；High stability crystal oscillator and each unit
It is directly connected between interior counter or is connected by phaselocking frequency multiplier；Comparator is respectively connected to multi-path choice in each unit
One input of device；Counter, comparator and register in each unit are connected with single-chip microcomputer respectively；Single-chip microcomputer it is defeated
Go out end also with MUX to be connected.It is relatively low with integrated cost, algorithm strong adaptability, support multipath clock source is mutually standby to seek
It is excellent, support a variety of time difference compensation strategies, can realize it is high-precision punctual, and the features such as time signal output is reliable and stable.
But above-mentioned technology clock in terms of stability it is not up to standard, its core component can not also use programmable list
Piece machine.
The content of the invention
Inventor has found that source sliding steps is cut when patent document disclosed above is not directed to more during the present invention is realized
The description of changing device and its method for operation, it is impossible to which source switching is disclosed above in addition to realize stability when preferably realizing more
Patent document does not possess log query device to realize manageability.
In order to solve the above-mentioned technical problem, the present invention provides a kind of FPGA Synchronization Clock, it is characterised in that bag
Include：When source unit, internal clock unit, signal output unit and Duo Shi sources sliding steps switch unit；And source unit bag when described
Three in parallel very first time source, the second time source and the 3rd time sources are included, three time sources in parallel select with reference source
Module connection is selected, the reference source selecting module connection exports at most according to the optimal time source of predetermined method choice
When source sliding steps switch unit；The internal clock unit, can for it is described when source unit reference source selecting module reference is provided
Time signal, and can also for the signal output unit and it is described more when source sliding steps switch unit pulse signal is provided；Institute
Sliding steps switch unit in source includes correction module when stating more, and can be by signal output to the signal output unit, the school
The pulse signal that holotype root tuber provides according to the time source and the internal clock unit that are provided from reference source selecting module is carried out
Compare, when source signal transmittance process in and/or different time source switch when, in time correction output to signal output unit letter
Number.Can so automatically select optimal time source, and when source signal transmittance process in and/or the switching of different time source
When, the when source signal that output unit needs can be constantly updated by correction module.
Preferably, sliding steps switch unit in source also includes the time difference comparison module when described more, and the time difference comparison module includes
Pulse per second (PPS) comparator and time comparator；And source sliding steps switch unit first passes around the time difference comparison module when inputting at most
And then input to the correction module.It so can accurately calculate the difference of time signal and internal reference time.
Preferably, sliding steps switch unit in source also includes filtering module when described more, and the filtering module includes fused filtering
Device and Color seperation grating device；And the signal of the correction module passes through after the filtering module, just export defeated to the signal
Go out unit.It can so adjust in handoff procedure that signal is advanced and/or lag issues in time by correction module.
Preferably, when described source unit also include three respectively with the very first time source, the second time source and the 3rd when
Between source-series formation-decoding module.Time source can be so allowed to be transmitted with a kind of more stable signal form.
Preferably, the very first time source is satellite-signal, and second time source is the IRIG- of Hot Spare synchronised clock
B signal, the 3rd time source are local IRIG-B code signals.These time sources, can allow FPGA Synchronization Clock
The time signal of plurality of stable can be selected.
Preferably, three decoder modules are in parallel respectively and then are connected with the reference source selecting module, and institute
Stating reference source selecting module includes mode bit judging submodule, priority judging submodule and Duo Shi sources judging submodule.This
From module the result of reference source selecting module can be allowed more intelligent a bit.
Preferably, times frequency module and filtering module are provided with the internal clock unit.High accuracy can so be obtained
Reference time and reference pulse, and signal is more stable.
Preferably, the Synchronization Clock of the FPGA, in addition to log unit, and set in the signal output unit
Message output module is equipped with, the message output module exports the information of the signal output unit to log unit.
Preferably, the signal of the signal of source unit and the internal clock unit also can be all inputted to the daily record when described
Unit.
, so can objectively operation shape of the recording synchronism clock apparatus within the past period using log unit
Condition, custodian is helped preferably to manage Synchronization Clock.
The present invention also provides a kind of control method of FPGA Synchronization Clocks in addition, and this method includes：When A. by inside
The signal of clock unit input to when source unit and Duo Shi sources sliding steps switch unit；B. optimal one is selected in source signal when multiple
Source signal when individual；C. the when source signal and internal clocking list selected in the sliding steps switch unit of source in set-up procedure B when described more
The difference of first signal, the pulse value of source signal when described in adjust automatically；D. when signal output unit correction is described, source is believed
Number pulse, then in turn through IRIG-B code generators and IRIG-B code transmitters, IRIG-B codes are sent to reception device.
Using above-mentioned preferred embodiment, refuse mutation in time source handoff procedure, ensure gentle transition, improve
The stability of Synchronization Clock.
Brief description of the drawings
Fig. 1 is that embodiment one is related to a kind of structured flowchart of FPGA Synchronization Clock.
Fig. 2 is the structured flowchart of internal clock unit in Fig. 1.
The structured flowchart of source sliding steps switch unit when Fig. 3 is more in Fig. 1.
Fig. 4 is the structured flowchart of signal output unit in Fig. 1.
Fig. 5 is a kind of flow chart for the Synchronization Clock control method that embodiment one is related to FPGA.
Fig. 6 is the structured flowchart that embodiment two is related to source unit when in a kind of FPGA Synchronization Clock.
Fig. 7 is that embodiment three is related to a kind of structured flowchart of FPGA Synchronization Clock.
Fig. 8 is the structured flowchart of log unit in Fig. 7.
Fig. 9 is the structured flowchart that Fig. 7 plants message signals output module.
Embodiment
The embodiment of the present invention is described in detail, it is necessary to illustrate below in conjunction with the accompanying drawings, these are specific
Explanation simply allow those of ordinary skill in the art to be more prone to, clearly understand the present invention, rather than limitation of the invention solution
Release.
Embodiment one
As shown in figure 1, when the present embodiment preferably provides a kind of FPGA (abbreviation of field programmable gate array) synchronization
Clock device, including：When source unit 1, internal clock unit 2, signal output unit 3 and Duo Shi sources sliding steps switch unit 4；And when
Source unit includes three in parallel very first time source 11, the second time source 12 and the 3rd time sources 13, three time sources in parallel
It is connected with reference source selecting module 14, reference source selecting module 14 is connected according to the optimal time source of predetermined method choice, and
And export source sliding steps switch unit 4 when at most；Wherein, internal clock unit 2, the reference source of source unit 1 selects mould when can be
Block 14 provides reference time signal, and can also be that signal output unit 3 and Duo Shi sources sliding steps switch unit 4 provide pulse letter
Number；Source sliding steps switch unit 4 includes correction module when more, and can be by signal output to signal output unit, correction module
Be compared according to the pulse signal that the time source and internal clock unit that are provided from reference source selecting module provide, when source
When in signal transduction process and/or different time source switches, the signal of correction output in time to signal output unit.So can be with
Automatically select optimal time source, and when source signal transmittance process in and/or different time source switch when, school can be passed through
Positive module constantly updates the when source signal of output unit needs.
As shown in table 1 below, the foundation in the selection Best Times of reference source selecting module 14 source is, in " source judges when more " module
In, be using it is independent when source multi-source decision logic as foundation, in the present embodiment, clock correction threshold values is preferably 20 μ s, wherein
Clock correction threshold value refers to source and following internal RTC (abbreviation of internal clock signal) during outside.
The foundation table in the reference source selecting module 14 of table 1. selection Best Times source
As shown in Fig. 2 times frequency module 21 and filtering module (not shown) are provided with internal clock unit 2；So can be with
High-precision reference time and reference pulse are obtained, and signal is more stable.Specifically, internal clock unit utilizes OCXO
(Oven Controlled Crystal Oscillator, constant-temperature crystal oscillator, be using thermostat make crystal oscillator or
The temperature of quartz-crystal unit keeps constant, oscillator output frequencies variable quantity will be cut to most as caused by changing environment temperature
Small crystal oscillator) caused by clock signal, by frequency module 21 again, export high-speed clock signal, high-speed clock signal is
The high-speed cruising of dispensing device and the temporal resolution of nanosecond provide guarantee；By time threshold caused by frequency module 21 again
When source unit 1 provides reference time and clock correction threshold value when being by impulse phase comparator 22, RTC clock 23 and clock correction threshold value 24
Between；It can also pass through divide ratio module 25 by time threshold caused by times frequency module 21 simultaneously, calculate divided signal, and
Store to memory cell, the pps pulse per second signal 26 obtained by divide ratio module 25, the coefficient of frequency device and counter storage
Can be that signal output unit 3 and Duo Shi sources sliding steps switch unit 4 provide reference respectively.
Preferably, the present embodiment exports 10Mhz clocks with OCXO, and by " frequency multiplication " module, using EP4CE15, (one kind should
With the chip of FPGA technology, the chip uses the 60-nm low-power consumption techniques by optimization, there is very big advantage in terms of power consumption.)
In the phase locked looped function that integrates, ten frequencys multiplication are carried out to OCXO, generate 100Mhz clock.
As shown in figure 3, source sliding steps switch unit 4 also includes time difference comparison module 41, time difference comparison module 41 when above-mentioned more
Including pulse per second (PPS) comparator 42 and time comparator 43；And source sliding steps switch unit 4 first passes around the time difference ratio when inputting at most
Compared with module 41 and then input to correction module, the difference of time signal and internal reference time thus can be accurately calculated
Value.Preferably, correction module is provided with divide ratio adjustment submodule 44, the advanced adder 45 of phase and delayed phase subtracter
46, the result that can be so calculated according to time difference comparison module 41, adjust automatically needs the impulse ratio corrected.Preferably, it is more
When source sliding steps switch unit also include filtering module, it is defeated that filtering module includes fused filtering device 47 and Color seperation grating device 48, pulse
Go out unit 49；And the signal of correction module passes through after filtering module, just output to signal output unit.It can so pass through
Correction module adjusts in handoff procedure that signal is advanced and/or lag issues in time.
As shown in Figure 5, it is preferable that the module of output of pulse signal module 31 produce pulse per second (PPS), sectors punching, when pulse." pulse
Signal output " module first passes through " divide ratio reading " module and reads the pulse per second (PPS) divide ratio that system-computed goes out；By " receiving
Delay modulator " module calculates the time delay for needing to compensate；Divide ratio is calculated by " divide ratio adjustment " module,
Pass through " pulse counter " module again, so far pulse per second (PPS) just generates.Sectors punching is triggered " dividing pulse counter " with pulse per second (PPS)
Module, counting often reach certain number and produce a sectors punching.When pulse generation rushed with sectors it is similar, by dividing pulse-triggered
" when pulse counter " module, counting reach pulse when certain number produces one time.IRIG-B code signals output module 32 exports
(IRIG time standards have two major classes to IRIG-B：One kind is parallel time code form, and this kind of code is due to being parallel form, transmission distance
From relatively near, and it is binary system, therefore it is extensive to can not show a candle to serial form；Another kind of is serial time code, shares six kinds of forms, i.e. A,
B、D、E、G、H；They main difference is that the frame rate of timing code is different, IRIG-B is Type B code therein) signal.First
By the date Hour Minute Second information in " date Hour Minute Second " module reading system, subsequently into " stipulations organizer " according to about
Fixed format editing message content, afterwards by as caused by " IRIG-B codes clock generator " module " stipulations generator " edit
Into IRIG-B code rule schematas, most after to reception device send IRIG-B code signals.
As shown in figure 5, in the present embodiment, it is preferable that a kind of control method of FPGA Synchronization Clocks, the party are also provided
Method includes：
S1. reference signal is obtained from internal clock unit：By the signal of internal clock unit input to when source unit and more
When source sliding steps switch unit；
Source when S2. selecting：Source signal when selecting optimal one in source signal when multiple；
S3. timing source signal：Selected in the sliding steps switch unit of source in set-up procedure B when described more when source signal with
The difference of internal clock unit signal, the pulse value of source signal when described in adjust automatically；
S4. IRIG-B codes are exported：The pulse of source signal when signal output unit correction is described, then in turn through
IRIG-B code generators and IRIG-B code transmitters, IRIG-B codes are sent to reception device.
Using the optimal technical scheme in the present embodiment, refuse mutation in time source handoff procedure, ensure gentle transition,
Improve the stability of Synchronization Clock.
Embodiment two
The technical scheme that embodiment two uses is identical with embodiment one or be substantially the same, for identical or be substantially the same
Part, herein not in repeat specification.Difference is the setting of time source, specific as follows：
As shown in Figure 6, it is preferable that when source unit 1 also include three respectively with the very first time source 11, the second time source
12 and the 3rd time source 13 connect formation-decoding module 15,16,17.Time source can so be allowed with a kind of more stable letter
Number form is transmitted.When the very first time source 11 be satellite-signal, and be the Big Dipper using a Big Dipper generation, GPS as time source, the
Two time sources 12 are the IRIG-B signals of Hot Spare synchronised clock, when the 3rd time source 13 is local IRIG-B code signals, are defended
The decoding apparatus of star signal can obtain the status information of the time source signal, time below the second, second and second information above respectively
Deng；And Hot Spare clock output signal can obtain similar time, status information with the IRIG-B codes information of local.And three
Individual decoder module 15,16,17 is in parallel respectively and then is connected with the reference source selecting module 14, and reference source selection mould
Block includes mode bit judging submodule, priority judging submodule and Duo Shi sources judging submodule, such as in conjunction with the embodiments one
In table 1 and the present embodiment in Fig. 6, when the effective criterion of satellite is, receive that star number is more than three, positional information is stable, satellite
Antenna is normal；The effective criterion of the IRIG-B signals (abbreviation IB1) of Hot Spare synchronised clock is that temporal quality is less than or equal to 4；This
The effective criterion of the IRIG-B code information (abbreviation IB2) on ground is that temporal quality is less than or equal to 4.Judge in priority " in block, same
Deng under the conditions of, when source priority be followed successively by from high to low：Satellite-signal, the IRIG-B signals of Hot Spare synchronised clock, local
IRIG-B code information..This is a little can to allow the result of reference source selecting module more intelligent from module.
Embodiment three
Apply the technical scheme of the use of example three and embodiment one, embodiment two be identical or is substantially the same, for identical or
(such as when source unit, internal clock unit and Duo Shi sources sliding steps switch unit in embodiment one, implement the part being substantially the same
When source unit in example two), herein not in repeat specification.Difference is to add log unit and message output module,
It is specific as follows：
As shown in Fig. 7~Fig. 9, the Synchronization Clock of the FPGA in the present embodiment, in addition to log unit, and signal
Message output module 33 is provided with output unit 3, message output module 33 exports the information of signal output unit 3 to daily record
Unit 5.Preferably, the signal of the signal of source unit 1 and internal clock unit 2 also can be all inputted to the log unit when.
, so can objectively operation shape of the recording synchronism clock apparatus within the past period using log unit
Condition, custodian is helped preferably to manage Synchronization Clock.
As shown in Figure 7, Figure 8, the outgoing message signal of message signals output module 33.Message signals output module 33, first
By the date Hour Minute Second information in " date Hour Minute Second " module reading system, subsequently into message organizer, according to about
Fixed format editing message content, afterwards by by (the letters of asynchronous starting conveyer of UART caused by Baud rate generator module
Claiming) stipulations generator compiles UART rule schematas, message signals are finally sent by message signals output module 33.IRIG-B codes
Signal output module exports IRIG-B signals." IRIG-B signal outputs " module, read first by " date Hour Minute Second " module
The date Hour Minute Second information in system is taken, the format editing message content subsequently into stipulations organizer according to agreement, afterwards
IRIG-B code rule schematas are compiled by the stipulations generator as caused by IRIG-B code clock generator blocks, finally by message
Signal output module 33 is by the log unit 5 of IRIG-B code signal page inputs.
As shown in figure 9, the optimal technical scheme that the present embodiment provides has log query function.Signal initially enters event
Detecting module, once meeting the trigger condition of time, case detecting module will record event result；Subsequently enter event row
Sequence module, the time of transmission is stamped into timestamp, and event classification is numbered.Event memory module is finally entered, preserves event
Time of origin and event code, it is preferable that the present embodiment shares 15 kinds of events, is followed successively by：Time source, the GPS currently selected
Signal recovers or exception, the recovery of Big Dipper signal or exception, the recovery of the IRIG-B signals of Hot Spare synchronised clock or exception, sheet
The IRIG-B code signals on ground recover or exception, gps antenna recovery or exception, Beidou antenna recovery or exception, the saltus step of Big Dipper time
Recover or exception, crystal oscillator tame recover or exception, initialization recover or exception, power module recover or exception, user log in into
Work(or failure, gps time saltus step recovery or exception, IB1 time saltus step recoveries or exception, the saltus step of Big Dipper time recovers or exception.
So time synchronism apparatus can also have log query module, to strengthen the management to the device.
Finally it should be noted that described above is only highly preferred embodiment of the present invention, not the present invention is appointed
What formal limitation.Any those skilled in the art, it is without departing from the scope of the present invention, all available
The way and technology contents of the disclosure above make many possible variations and simple replacement etc. to technical solution of the present invention, these
Belong to the scope of technical solution of the present invention protection.
Claims (10)
- A kind of 1. FPGA Synchronization Clock, it is characterised in that including：When source unit, internal clock unit, signal output list Sliding steps switch unit in source when first and more；AndSource unit includes three in parallel very first time source, the second time source and the 3rd time sources, three parallel connections when described Time source be connected with reference source selecting module, reference source selecting module connection according to predetermined method choice it is optimal when Between source, and export source sliding steps switch unit when at most；The internal clock unit, can for it is described when source unit reference source selecting module reference time signal is provided, and Can also for the signal output unit and it is described more when source sliding steps switch unit pulse signal is provided；Sliding steps switch unit in source includes correction module when described more, and can by signal output to the signal output unit, The pulse that the correction module provides according to the time source provided from reference source selecting module and the internal clock unit is believed Number be compared, when source signal transmittance process in and/or different time source switch when, adjustment output in time to signal output list The impulse ratio or phase of the signal of member.
- 2. FPGA as claimed in claim 1 Synchronization Clock, it is characterised in that source sliding steps switch unit also wraps when described more Time difference comparison module is included, the time difference comparison module includes pulse per second (PPS) comparator and time comparator；And input source when at most Sliding steps switch unit first passes around the time difference comparison module and then input to the correction module.
- 3. FPGA as claimed in claim 1 Synchronization Clock, it is characterised in that source sliding steps switch unit also wraps when described more Filtering module is included, the filtering module includes fused filtering device and Color seperation grating device；And the signal of the correction module passes through After the filtering module, just output to the signal output unit.
- 4. FPGA as claimed in claim 1 Synchronization Clock, it is characterised in that when source unit also include three respectively with The very first time source, the second time source and the 3rd time source-series formation-decoding module.
- 5. FPGA as claimed in claim 4 Synchronization Clock, it is characterised in that the very first time source is satellite-signal, Second time source is the IRIG-B signals of Hot Spare synchronised clock, and the 3rd time source is local IRIG-B codes letter Number.
- 6. FPGA as claimed in claim 4 Synchronization Clock, it is characterised in that three decoder modules difference parallel connection Afterwards, then with the reference source selecting module it is connected, and the reference source selecting module includes mode bit judging submodule, excellent First level judging submodule and Duo Shi sources judging submodule.
- 7. FPGA as claimed in claim 1 Synchronization Clock, it is characterised in that be provided with the internal clock unit again Frequency module and filtering module.
- 8. FPGA as claimed in claim 1 Synchronization Clock, it is characterised in that also including log unit, and the letter Be provided with message output module in number output unit, the message output module by the information of the signal output unit export to Log unit.
- 9. FPGA as claimed in claim 8 Synchronization Clock, it is characterised in that the signal of source unit and described interior when described The signal of portion's clock unit also can be all inputted to the log unit.
- 10. a kind of control method of FPGA Synchronization Clocks, it is characterised in that the Synchronization Clock of the FPGA is as weighed Profit requires a kind of 1~9 arbitrary Synchronization Clock, and methods described includes：A. by the signal of internal clock unit input to when source unit and Duo Shi sources sliding steps switch unit；Source signal when B. selecting optimal one in source signal when multiple；C. when described more in the sliding steps switch unit of source according to when the pulse signal that provides of source signal and internal clock unit carry out Compare, when source signal transmittance process in and/or different time source switch when, in time adjustment output to signal output unit letter Number impulse ratio or phase；D. when signal output unit correction is described source signal pulse, then in turn through IRIG-B code generators and IRIG-B code transmitters, IRIG-B codes are sent to reception device.
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| CN105119677B (en) * | 2015-09-09 | 2018-01-16 | 山东中瑞电气有限公司 | The when source of raising time service output reliability selects and switching system |
| CN106896863B (en) * | 2015-12-18 | 2019-12-06 | 南京南瑞继保电气有限公司 | Self-adaptive time synchronization method for embedded system |
| CN106411295B (en) * | 2016-09-30 | 2019-03-08 | 西电通用电气自动化有限公司 | A kind of IRIG-B keeps time clock drift compensation method and circuit |
| CN107196725A (en) * | 2017-05-09 | 2017-09-22 | 合肥移顺信息技术有限公司 | Embedded device time service method based on priority |
| CN107727926B (en) * | 2017-09-29 | 2022-04-19 | 北京无线电计量测试研究所 | Time frequency measuring method and device |
| CN111208726B (en) * | 2020-01-03 | 2021-09-24 | 中国船舶重工集团公司第七0七研究所 | Multi-source self-adaptive time service device and method |
| CN115296769B (en) * | 2022-10-08 | 2022-12-27 | 中国电子科技集团公司第五十四研究所 | High-reliability timing method and device for satellite communication system of TDMA system |
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