CN113541838A

CN113541838A - Method for determining clock and related device

Info

Publication number: CN113541838A
Application number: CN202010586995.XA
Authority: CN
Inventors: 石兴建; 何涛; 李�浩; 曾晓意
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-04-13
Filing date: 2020-06-24
Publication date: 2021-10-22

Abstract

The application provides a method for determining a clock and a related device, wherein the method comprises the following steps: under the condition that the second network equipment and the first network equipment are both synchronous to the reference clock, simulating a second virtual clock synchronous to the first virtual clock by utilizing the time delay information between the second network equipment and the first network equipment and the frequency information of the clock of the second network equipment, wherein the first virtual clock is used for simulating the clock of the first network equipment. The technical scheme can simulate the clock of the second network device so as to perform subsequent operation by using the simulated clock, for example, the simulated clock can be used for estimating the synchronization performance of the PTP message of the second network device. Therefore, before the GNSS fails, the PTP message synchronization performance of the second network equipment can be judged in advance to guide the network operation and maintenance activities.

Description

Method for determining clock and related device

The present application claims priority of chinese patent application entitled "method for evaluating network message synchronization and related device" filed by the chinese patent office at 13/04/2020, application number 202010286753.9, the entire contents of which are incorporated herein by reference.

Technical Field

The present application relates to the field of communications technologies, and in particular, to a method for determining a clock and a related apparatus.

Background

In modern communication networks, the proper functioning of most telecommunications services requires that the frequency or time differences between the network-wide devices be kept within a reasonable error level, i.e. network clock synchronization. The frequencies of different network devices must be synchronized within a certain precision, otherwise, service anomalies, such as code sliding, disconnection and the like, may occur when the access network device or the terminal device processes services. While some wireless systems require both frequency synchronization and phase synchronization.

In the fifth generation (5)^thGeneration, 5G) communication network, for example, the time error between access network devices in the 5G network needs to be less than 3 microseconds (μ s), and the synchronization accuracy between the network devices and the network clock time server needs to be less than 1.5 μ s.

The Assisted Partial Timing (APTS) function provides synchronization accuracy via a Global Navigation Satellite System (GNSS). An APTS solution is to deploy GNSS devices (e.g., Global Positioning System (GPS) receivers, beidou receivers, etc.) in network equipment. When the GNSS device is normal, the network device tracks the clock time information of the GNSS device. When the GNSS device has a problem (e.g., the GNSS device is physically out of order, a GNSS signal is interfered, deceived, or lost, etc.), switching clock Time synchronization to a ground communication network, for example, implementing frequency or phase synchronization in a Precision Time Protocol (PTP) message manner; for example, synchronizing to a clock source device upstream of the network by means of Adaptive Clock Recovery (ACR)/Adaptive Time Recovery (ATR).

The current method for evaluating the message synchronization performance comprises the steps of carrying out simulation analysis on the synchronization performance through forward and reverse delay data collected by downloading equipment, or leading the forward and reverse delay data into a test instrument for performance test. The two modes require operation and maintenance personnel or professional technical personnel and special test instruments, cannot acquire evaluation results quickly, and are high in labor, material and time costs.

Disclosure of Invention

The application provides a method and a related device for determining a clock, which can simulate the clock of a network device.

In a first aspect, an embodiment of the present application provides a method for determining a clock, including: under the condition that a second network device and a first network device are both synchronous to a reference clock, acquiring time delay information between the second network device and the first network device and frequency information of a clock of the second network device; determining a second virtual clock according to the frequency information; and adjusting the second virtual clock according to the time delay information, wherein the adjusted second virtual clock is synchronous with a first virtual clock, and the first virtual clock is used for simulating the clock of the first network equipment. The technical scheme can simulate the clock of the second network device so as to perform subsequent operation by using the simulated clock, for example, the simulated clock can be used for estimating the synchronization performance of the PTP message of the second network device. Therefore, before the GNSS fails, the PTP message synchronization performance of the second network equipment can be judged in advance to guide the network operation and maintenance activities.

In one possible design, the delay information includes N delays, where the N delays are delays from N second network devices to the first network device, or delays from N first network devices to the second network device, and N is a positive integer greater than or equal to 2; the method further comprises the following steps: acquiring N first time stamps generated by the first virtual clock; the adjusting the second virtual clock according to the delay information includes: acquiring N second timestamps generated by the second virtual clock according to the N time delays and the N first timestamps, wherein the N second timestamps correspond to the N time delays one by one; and adjusting the frequency of the second virtual clock according to the N second time stamps and the N first time stamps. By using the technical scheme, the frequency of the simulated clock of the second network device can be synchronous with the frequency of the virtual clock of the first network device.

In one possible design, obtaining N second timestamps generated by the second virtual clock according to the N delays and the N first timestamps includes: and determining that the timestamp of the second virtual clock is the nth second timestamp of the N second timestamps after the nth time delay of the N time delays by taking the nth timestamp of the N first timestamps as the starting time, wherein N is 1, … and N.

In one possible design, the delay information includes a forward delay and a reverse delay, where the forward delay is a delay from the first network device to the second network device, and the reverse delay is a delay from the second network device to the first network device, and the method further includes: acquiring a third timestamp and a sixth timestamp generated by the first virtual clock; acquiring a fourth time stamp and a fifth time stamp generated by a second virtual clock; the adjusting the second virtual clock according to the delay information includes: determining a first time delay according to the forward time delay, the third time stamp and the fourth time stamp; determining a second time delay according to the reverse time delay, the fifth time stamp and the sixth time stamp; and adjusting the phase of the second virtual clock according to the first time delay and the second time delay. By using the technical scheme, the phase of the simulated clock of the second network device can be synchronous with the phase of the virtual clock of the first network device.

In one possible design, determining the first delay based on the forward delay, the third timestamp, and the fourth timestamp includes: the first time delay is determined according to the following equation:

D₁＝D_f+(T₄-T₃)，

wherein D is₁For the first time delay, D_fFor the forward delay, T₃For the third time stamp, T₄The fourth timestamp;

determining a second time delay according to the reverse time delay, the fifth time stamp and the sixth time stamp includes: the second time delay is determined according to the following equation:

D₂＝D_b+(T₆-T₅)，

wherein D is₂For the second time delay, D_bFor the reverse time delay, T₅For the fifth time stamp, T₆Is the sixth timestamp.

In one possible design, the latency information includes a seventh timestamp, an eighth timestamp, a ninth timestamp, and a tenth timestamp; the adjusting the second virtual clock according to the delay information includes: adjusting the eighth timestamp and the ninth timestamp according to the frequency information; adjusting the phase of the second virtual clock according to the seventh timestamp, the adjusted eighth timestamp, the adjusted ninth timestamp, and the adjusted tenth timestamp. By using the technical scheme, the phase of the simulated clock of the second network device can be synchronous with the phase of the virtual clock of the first network device.

In one possible design, the method further includes: and determining clock performance evaluation information according to the first virtual clock and the adjusted second virtual clock, wherein the clock performance evaluation information is used for indicating the clock time recovery performance of the second virtual clock. According to the technical scheme, the second virtual clock can be used for obtaining the information for evaluating the clock time recovery performance of the second virtual clock, so that the clock time recovery performance of the second virtual clock can be evaluated by using the obtained information to guide network operation and maintenance activities.

In one possible design of the system, the system may be,the determining clock performance evaluation information according to the first virtual clock and the adjusted second virtual clock includes: determining the frequency F of the first virtual clock_v1And the adjusted frequency F of the second virtual clock_v2(ii) a According to F_v1And F_v2And determining the time interval error TIE. The technical scheme can obtain the frequency recovery performance of the second virtual clock.

In one possible design, the determining clock performance evaluation information based on the first virtual clock and the adjusted second virtual clock includes: determining a generation timestamp T of the first virtual clock_v1And T_v4Determining the adjusted timestamp T generated by the second virtual clock_v2And T_v3(ii) a According to T_v1、T_v2、T_v3And T_v4And determining the time error TE. The technical scheme can obtain the phase recovery performance of the second virtual clock.

In a second aspect, an embodiment of the present application provides an electronic device, which includes a unit configured to implement the first aspect or any one of the possible designs of the first aspect.

In a third aspect, an embodiment of the present application provides an electronic device, including: a processor for coupling with the memory, reading and executing instructions and/or program code in the memory, to perform a method as the first aspect or any of the possible designs of the first aspect.

In a fourth aspect, an embodiment of the present application provides a chip system, including: logic circuitry for coupling with an input/output interface through which data is transferred to perform a method as designed in the first aspect or any one of the first aspects

In a fifth aspect, the present application provides a computer-readable storage medium storing program code, which when executed on a computer causes the computer to perform the method according to the first aspect or any one of the possible designs of the first aspect.

Drawings

Fig. 1 is a schematic diagram of a system to which the present solution is applied.

Fig. 2 is a schematic diagram of the principle of message time synchronization.

Fig. 3 is a schematic diagram of a frequency synchronization process.

Fig. 4 is a schematic flow chart diagram of a method of determining a clock provided in accordance with an embodiment of the present application.

Fig. 5 is a schematic diagram of determining the frequency control word by two forward delays.

Fig. 6 is a schematic flow chart of adjusting the phase of the virtual clock T-TSC according to an embodiment of the present application.

Fig. 7 is another schematic flow chart diagram for adjusting the phase of the virtual clock T-TSC according to an embodiment of the present application.

FIG. 8 is a schematic flow chart diagram of a method of determining a clock according to the teachings of the present application.

Fig. 9 is a schematic structural block diagram of an electronic device provided according to an embodiment of the present application.

Detailed Description

The technical solution in the present application will be described below with reference to the accompanying drawings.

The technical scheme of the embodiment of the application can be applied to various communication systems, for example: a Global System for Mobile communications (GSM) System, a Code Division Multiple Access (CDMA) System, a Wideband Code Division Multiple Access (WCDMA) System, a General Packet Radio Service (GPRS), a Long Term Evolution (Long Term Evolution, LTE) System, an LTE Frequency Division Duplex (FDD) System, an LTE Time Division Duplex (TDD), a Universal Mobile Telecommunications System (UMTS), a Worldwide Interoperability for Microwave Access (WiMAX) communication System, a future fifth Generation (5G) System, or a New Radio Network (NR), etc.

In order to facilitate a better understanding of the technical solutions of the present application for those skilled in the art, a brief description will first be given of some concepts related to the technical solutions of the present application.

1, clock synchronization

Clock synchronization includes two concepts of phase synchronization and frequency synchronization.

Frequency synchronization, also referred to as clock synchronization, refers to maintaining a certain strict specific relationship in frequency or phase between signals that occur at the same average rate at their respective valid instants to maintain all devices in the communication network operating at the same rate, i.e., to maintain a constant phase difference between the signals.

Phase synchronization, also known as time synchronization, means that both the frequency and the phase between signals are kept consistent, i.e. the phase difference between the signals is constantly zero.

2，1588

1588 is defined by the Institute of Electrical and Electronics Engineers (IEEE).

The 1588v1 version was released in 2002 and is mainly applied to the fields of industrial automation and test measurement; in the field of telecommunications, with the development of Internet Protocol (IP) and third generation (3)^rdGeneration, 3G) communication technology, the demand of telecommunication networks for time synchronization is becoming stronger. The IEEE organization revises 1588v1 again. The first draft of IEEE 1588v2 was exported in 2006 and 6 months, the revision was completed in 2007, and the IEEE 1588v2 standard was officially released at the end of 2008.

1588v2 is called Precision Clock Synchronization Protocol (Precision Time Protocol, PTP) for network Measurement and Control system. 1588v2 is originally used only for high precision time synchronization between devices, but can also be used for clock synchronization or time synchronization between devices.

3，ITU-T G.8275.1

The International Telecommunication Union Telecommunication standards office (ITU-T) defines the Telecommunication-level network-wide Precision time synchronization protocol (Precision time protocol for phase/time synchronization with full time from the network).

The ITU-T g.8275.1 protocol defines three basic clock node types: a carrier master clock (T-GM), a carrier boundary clock (T-BC), and a carrier slave clock (T-TSC).

The T-GM can only be used as a master (master) device and provides a synchronous clock source.

The T-BC may have multiple clock ports, where a slave port may synchronize to the clock information of an upstream device and a master port may transmit clock information to a downstream device.

The T-TSC can only be used as a slave (slave) device to synchronize the clock information of the upstream device.

4, master clock (grandmaster), master (master) device/slave (slave) device

The time synchronization network can be regarded as a spanning tree, and the master clock is the root node of the tree, and the time of all nodes in the network is kept synchronous with the master clock.

For a pair of nodes that are time synchronized, the upstream node that sends the synchronized time is referred to as the master, and the downstream node that receives the synchronized time is referred to as the slave.

The network device referred to in this embodiment of the present application is a network device capable of providing a clock for an access network device, a baseband control unit (BBU), and a Remote Radio Unit (RRU). For example, T-GM, T-BC, T-TSC, etc. may be used.

5，1588ACR(PTP ACR)

The 1588ACR network architecture mainly comprises 3 parts: 1588ACR master (master) device, i.e. packet master clock; 1588ACR slave (slave) devices, i.e., packet slave clocks (packet slave clocks); an intermediate packet network, i.e., a packet network (packet network). The 1588ACR master device transmits a clock (frequency) signal to the 1588ACR slave device through a 1588 message through the intermediate network, and the 1588ACR slave device recovers the frequency of the 1588ACR master device according to a timestamp carried in the message. The clock source of the 1588ACR master device may be from GNSS, or from building integrated timing supply system (BITS), or even from other Synchronous Digital Hierarchy (SDH) synchronous networks or synchronous Ethernet (sync). And the 1588ACR slave equipment recovers the clock of the 1588ACR master equipment according to the 1588v2 message, and frequency synchronization between the slave equipment and the 1588ACR master equipment is realized. Since the intermediate network may bring a certain delay and delay jitter when forwarding the 1588v2 message of the 1588ACR master device, which is equivalent to that when the 1588ACR slave device receives the message, a certain noise is superimposed on the timestamp of the 1588ACR master device, so that the clock performance recovered by the 1588ACR slave device may be affected. Different network loads and different forwarding paths bring different noises, and the performance recovered by the 1588ACR slave equipment generally differs.

6，1588ATR(PTP ATR)

1588ATR is an adaptive time synchronization scheme that is mainly applied to scenarios where hop-by-hop time synchronization of 1588V2 is not supported across intermediate networks. On the premise of frequency synchronization (the frequency synchronization can be SyncE frequency synchronization or 1588ACR frequency synchronization), the 1588ATR slave device calculates the time deviation between the master and slave devices according to the timestamp carried in the message, adjusts the real-time clock (RTC) of the slave device, and realizes that the time of the slave device is synchronized with the time of the master device; the time synchronization performance is affected by Packet Delay Variation (PDV) introduced by the traffic load of the network passing through the middle, the forwarding path, and other factors.

The Access Network device in this embodiment may be a device for communicating with a terminal device, where the Access Network device may be a Base Transceiver Station (BTS) in a Global System for Mobile communications (GSM) System or a Code Division Multiple Access (CDMA) System, may also be a Base Station (NodeB, NB) in a Wideband Code Division Multiple Access (WCDMA) System, may also be an evolved node b (eNB, or eNodeB) in an LTE System, may also be a wireless controller in a Cloud Radio Access Network (CRAN) scenario, or may be a relay Station, an Access point, a vehicle-mounted device, a wearable device, a Network device in a future 5G Network, or a Network device in a future evolved PLMN Network, and the like, and the embodiment of the present application is not limited.

Fig. 1 is a schematic diagram of a system to which the present solution is applied. The system shown in FIG. 1 includes T-GM 101, T-BC 102 and T-TSC 103.

The reference clock of T-GM 101 is a Primary Reference Time Clock (PRTC) 111. In other words, T-GM 101 is synchronized with PRTC 111.

The reference clock of the T-TSC 103 is the clock acquired by the GNSS device 112. The T-TSC 103 is synchronized to the clock acquired by the GNSS device 112. T-TSC 103 may provide clocks for access network equipment 132 and RRU 133.

The reference clock of the T-BC 102 is the clock acquired by the GNSS device 113. The T-BC 102 is synchronized with the clock acquired by the GNSS device 113. The clock acquired by the T-BC 102 from the GNSS 113 is acquired via the RRU 135. The clock time information collected by the GNSS device 113 may be transmitted to the T-BC 102 via the RRU 135. The T-BC 102 can clock the BBU 134.

The clock time information received by the RRU 135 from the GNSS device 133 may be used as the clock for the access network equipment 131.

GNSS device 132 and GNSS device 133 may be based on different GNSS acquired clock time information. For example, the GNSS device 132 may be configured to acquire clock time information via Beidou, and the GNSS device 133 may be configured to acquire clock time information via GPS. For another example, the GNSS device 132 may be operable to acquire clock time information via GPS, and the GNSS device 133 may be operable to acquire clock time information via Galileo (Galileo) satellite navigation system.

Of course, the GNSS device 133 and the GNSS device 132 may also acquire clock time information based on the same GNSS. For example, both the GNSS device 132 and the GNSS device 132 may utilize the Beidou acquired clock time information. As another example, GNSS device 132 and GNSS device 133 may both utilize GPS-collected clock time information.

For ease of description, each network device in fig. 1 provides a clock for only one access network device, one BBU, or one RRU. However, each network device may provide clocks for multiple access network devices, multiple BBUs, and/or multiple RRUs.

Fig. 2 is a schematic diagram of the principle of message time synchronization. As shown in fig. 2, the master device transmits a synchronization message (Sync message) to the slave device at time t 1. The synchronization message carries a t1 time stamp.

The slave device receives the sync message at time t2 and generates a timestamp t2 locally. In other words, the slave device locally generates a timestamp t2 at the time the sync message is received. The slave device also extracts the t1 timestamp from the synchronization message.

The slave device sends a Delay Request (Delay _ Request, Delay _ Req) message to the master device at time t3, and locally generates a t3 timestamp.

The master device receives the Delay request message at time t4, locally generates a t4 timestamp, and then carries the t4 timestamp in a Delay Response (Delay _ Response, Delay _ Resp) message to send to the slave device.

After receiving the delayed response message, the slave device extracts t4 time stamp from the delayed response message.

The slave device can calculate the time offset between the slave device and the master device by using the four time stamps of t1, t2, t3 and t4, so as to adjust the time of the slave device to realize time synchronization with the master device.

Specifically, assume that the path delay of the message from the master device to the slave device is denoted as DS1, and the path delay of the message from the slave device to the master device is denoted as D_S2The time Offset between the slave and the master is denoted as Offset. Then, D_S1，D_S2Offset, t1, t2, t3 and t4 have the following relationships:

t2-t1＝D_S1+ Offset (formula 2.1)

t4-t3＝D_S2Offset, (equation 2.2)

According to the 1588V2 protocol, D can be assumed_S1＝D_S2Then Offset can be calculated by the following formula:

offset is [ (t2-t1) - (t4-t3) ]/2, (equation 2.3).

t2-t1 may be referred to as a forward delay and t4-t3 may be referred to as a reverse delay.

Fig. 3 is a schematic diagram of a frequency synchronization process. As shown in fig. 3, the master device and the slave device implement frequency synchronization through a synchronization message.

As shown in fig. 3, the master device periodically sends a synchronization message to the slave device. The synchronization packet carries a timestamp of the transmission time. And after receiving the synchronous message, the slave equipment generates a local time stamp and extracts the time stamp in the synchronous message.

For example, the master device is at time t1₀And sending a synchronous message 0 to the slave equipment. The slave device at time t2₀Receiving the synchronization message 0, generating a local timestamp t2₀And extracts the time stamp t1 from the sync message 0₀. The master device at time t1₁Synchronization message 1 is sent to the slave. The slave device at time t2₁Receiving sync message 1, generate local timestamp t2₁And extracts the time stamp t1 from the sync message 1₁And so on.

The master device periodically sends a synchronization message to the slave device, regardless of the change of the path delay, if the frequency of the slave device and the frequency of the master device are synchronized, the accumulated time offset of the master device and the slave device is the same in the same time interval, that is:

t2₁-t2₀＝t1₁-t1₀，t2₂-t2₁＝t1₂-t1₁，t2₃-t2₂＝t1₃-t1₂…, and so on, t2_n-t2₀＝t1_n-t1₀。

If t2_n-t2₀Greater than t1_n-t1₀If the frequency of the slave device is higher than that of the master device, the frequency of the slave device needs to be reduced; otherwise, the frequency of the slave equipment needs to be increased. The specific adjustment mode can be adjusted by using a proportional-integral-derivative (PID) control principle.

The frequency synchronization can also be achieved by t3 and t4, which have the same principle as t1 and t2 described herein, and therefore, for brevity, will not be described herein again.

As described above, T-GM and T-BC may act as master devices and T-BC and T-TSC may act as slave devices. For example, if the master device is a T-GM, the slave device may be a T-BC or a T-TSC. The slave may be a T-TSC if the master is a T-BC.

Fig. 4 is a schematic flow chart diagram of a method of determining a clock provided in accordance with an embodiment of the present application. The method shown in fig. 4 may be executed by a network device serving as a slave device, and may also be implemented by a device (e.g., a chip, a circuit, or the like) in the network device serving as the slave device. For convenience of description, it is assumed in the following embodiments that the T-GM is a network device as a master device and the T-TSC is a network device as a slave device. For convenience of description, the scheme of the present application is described below with T-TSC as the execution subject.

Step 401, the T-TSC obtains the time delay information between the T-TSC and the T-GM under the condition that the T-GM and the T-TSC are both synchronous to the reference clock.

And step 402, the T-TSC adjusts the virtual clock T-TSC in the T-TSC according to the collected time delay information, so that the virtual clock T-TSC is synchronous with the virtual clock T-GM. The virtual clock T-GM is a clock for simulating the T-GM.

The

above steps

401 and 402 will be described in detail.

Optionally, in some embodiments, the delay information obtained by the T-TSC may include a forward delay and a reverse delay. Specifically, the T-TSC may track 1588 messages (such as sync messages, delay request messages, and delay response messages shown in fig. 2 and 3, which may also be referred to as PTP messages) between the T-GM and the T-TSC, obtain a timestamp, and determine a forward delay (i.e., a delay from the T-GM to the T-TSC) and a reverse delay (i.e., a delay from the T-TSC to the T-GM) according to the obtained timestamp.

The delay information of the T-TSC record may include multiple sets of information, and each set of information may include one forward delay and one reverse delay. For example, table 1 shows a plurality of sets of information in the delay information collected by the T-TSC.

TABLE 1

As shown in table 1, the T-TSC performs the process shown in fig. 2N times in total, and collects N sets of information in the delay information. The first group of information in the delay information collected by the T-TSC comprises forward delay 1 and reverse delay 1, the second group of information in the delay information comprises forward delay 2 and reverse delay 2, and the like. The manner in which the T-TSC collects the forward delay and the reverse delay may refer to the process shown in fig. 2, and for brevity, will not be described herein again.

As shown in table 1, the information collected by the T-TSC includes frequency information in addition to the time delay information. The frequency information is clock frequency information of the T-TSC. The specific role of this frequency information will be described later.

Optionally, in other embodiments, the T-TSC may use the obtained timestamp as the time delay information. For example, table 2 shows a plurality of sets of information in the delay information collected by the T-TSC.

TABLE 2

As shown in table 2, the T-TSC performs the process shown in fig. 2N times in total, and collects N sets of information in the delay information. The first group of information in the time delay information collected by the T-TSC comprises T1₁，T2₁，T3₁And T4₁The second group of information in the delay information includes T1₂，T2₂，T3₂And T4₂. And so on. The manner in which the T-TSC collects the forward delay and the reverse delay may refer to the process shown in fig. 2, and for brevity, will not be described herein again.

The clock of the T-TSC is synchronized to the GNSS. In order to distinguish the virtual clocks in the T-TSC, the clocks required for the T-TSC to run are hereinafter referred to as the actual clocks. In other words, the actual clock of the T-TSC is synchronized to the GNSS. Since synchronization with GNSS is required, the T-TSC requires a frequency control word to adjust the frequency of the actual clock to make the actual clock synchronized to GNSS.

In some embodiments, the frequency information collected by the T-TSC may be a frequency control word. In other embodiments, the frequency information collected by the T-TSC may also be clock source noise. Due to the existence of clock source noise, the frequency of the actual clock needs to be adjusted by using the frequency control word so as to synchronize the actual clock with the GNSS. Thus, the frequency control word and clock source noise may be corresponding.

As shown in tables 1 and 2, a set of information collected by the T-TSC may include time delay information and frequency information. In other words, the T-TSC may collect frequency information during this time period when collecting the delay information.

There may be two virtual clocks in the T-TSC, namely a virtual clock T-TSC and a virtual clock T-GM.

The virtual clock may include a virtual Direct Digital Synthesizer (DDS) and a virtual Real Time Clock (RTC). The virtual DDS generates a clock signal, and the virtual RTC generates time information (time stamp) using the clock signal generated by the virtual DDS as an operating clock. The format of the time information generated by the virtual RTC is 48-bit (bit) seconds(s) and 32-bit nanoseconds (ns). The time information may be converted into time of year, month, day, minute and second. For convenience of description, the time information generated by the virtual RTC is hereinafter expressed in terms of time, month, day, minute and second.

As described above, the virtual clock T-GM is the actual clock for the virtual T-GM. The clock of the T-GM is synchronized to the PRTC. Therefore, the actual clock of the T-GM can be considered as an ideal clock. Therefore, the clock signal generated by the virtual clock T-GM may be an ideal clock signal.

The clock signal generated by the virtual clock T-TSC is determined based on the collected frequency information and the ideal clock signal. The clock signal generated by the virtual clock T-TSC is generated by the ideal clock signal superimposed with the clock source noise. Therefore, as described above, if the frequency information collected by the T-TSC is clock source noise, the T-TSC may directly determine a clock signal generated by the virtual clock T-TSC using the clock source noise. If the frequency information collected by the T-TSC is a frequency control word, the frequency control word needs to be converted into clock source noise, and then the clock signal generated by the virtual T-TSC is determined according to the clock source noise.

The T-TSC can adjust the virtual clock T-TSC by utilizing the collected time delay information, the timestamp generated by the virtual clock T-GM and the timestamp generated by the virtual clock T-TSC, so that the virtual clock T-TSC is synchronous with the virtual clock T-GM.

A brief description of how the frequency of the virtual clock T-TSC is adjusted is given below in connection with fig. 5.

Fig. 5 is a schematic flow chart diagram of adjusting the frequency of a virtual clock T-TSC according to an embodiment of the application.

Step 501, obtaining a timestamp T1 generated by a virtual clock T-GM₁。

Step 502, at T1₁Recording the current time stamp of the virtual clock T-TSC as T2 after the starting time passes through the forward time delay 1₁。

Step 503, obtaining the timestamp T1 generated by the virtual clock T-GM₂。

At step 504, at T1₂Recording the current time stamp of the virtual clock T-TSC as T2 after the starting time passes through the forward time delay 2₂。

Step 505, according to T1₁，T1₂，T2₁And T2₂The frequency of the virtual clock T-TSC is adjusted.

If T2₂-T2₁Greater than T1₂-T1₁The frequency of the virtual clock T-TSC is slowed down. If T2₂-T2₁Less than T1₂-T1₁The frequency of the virtual clock T-TSC is accelerated. The adjustment method for determining the frequency can be determined by means of PID control, for example, the frequency control word F can be determined by means of PID control_{2_1}The frequency control word is used to adjust the frequency of the virtual clock T-TSC. The specific process of determining the frequency control word is not described herein.

Fig. 5 is a schematic diagram of determining the frequency control word by two forward delays. In other embodiments, two may be utilizedThe reverse delay determines a frequency control word. The determination process is reversed from that shown in fig. 5. For example, a virtual clock T-TSC timestamp is obtained as T3₁Then at T3₁Recording the current time stamp of the virtual clock T-GM as T4 after the starting time passes through the reverse time delay 1₁(ii) a Obtaining virtual clock T-TSC timestamp as T3₂Then at T3₂Recording the current time stamp of the virtual clock T-GM as T4 after the reverse time delay 2 for the starting time₂(ii) a According to T3₁，T3₂，T4₁And T4₂And generating a frequency control word.

In other embodiments, the manner in which the frequency control word is determined may also be determined using more than two forward delays or more than two reverse delays. The specific determination method is similar to the determination method using two forward delays or two reverse delays, and for brevity, no further description is given here.

As described above, the delay information collected by the T-TSC may be a forward delay and a reverse delay, in which case, the collected forward delay or reverse delay may be directly used to determine the frequency control word. If one group of information in the time delay information collected by the T-TSC is four time stamps, the forward time delay or the reverse time delay can be determined according to the four collected time stamps, and then the frequency control word is determined by utilizing the determined time delay.

A brief description of how the phase of the virtual clock T-TSC is adjusted is given below in connection with fig. 6 and 7.

In step 601, timestamps T1, T2, T3, and T4 are obtained.

In some embodiments, the timestamps T1 and T4 are generated by the virtual clock T-GM and the timestamps T2 and T3 are generated by the virtual clock T-TSC. For example, a time stamp T1 generated by the virtual clock T-GM is obtained, and then after 1 packetization interval, a time stamp T2 generated by the virtual clock T-TSC is recorded. The time stamp T3 generated by the virtual clock T-TSC is recorded after a preset time interval, and then the time stamp T4 generated by the virtual clock T-GM is recorded after 1 packetization interval.

In other embodiments, the virtual clock T-GM may generate timestamps T1, T2 ', T3', and T4, and then superimpose the collected clock source noise on T2 'and T3', resulting in timestamps T2 and T3.

Step 602, determining a first time delay according to the forward time delay, the time stamp T1 and the time stamp T2; the second latency is determined from the reverse latency, timestamp T3 and timestamp T4.

The first time delay may be determined according to the following equation:

D₁＝D_f+(T₂-T₁) (equation 6.1)

Wherein D is₁Is a first time delay, D_fFor forward delay, T₁Is a time stamp T1, T₂Is a time stamp T2.

The forward and reverse delays in equations 6.1 and 6.2 may be forward and reverse delays included in the delay information. In other words, the delay information collected by the T-TSC is forward and reverse delay. In other embodiments, the forward and reverse delays in equations 6.1 and 6.2 are calculated based on the four timestamps collected by the T-TSC.

The second time delay may be determined according to the following equation:

D₂＝D_b+(T₄-T₃) (equation 6.2)

Wherein D is₂For a second time delay, D_bFor reverse time delay, T₃Is a time stamp T3, T₄Is a time stamp T4.

Step 603, adjusting the phase of the virtual clock T-TSC according to the first time delay and the second time delay.

Alternatively, the phase adjustment parameter may be determined according to the following formula:

T_Offset＝(D₁-D₂) /2, (equation 6.3)

Wherein T is_OffsetRepresents the phase adjustment parameter, D₁Representing the first time delay, D₂Representing the second time delay. After the phase adjustment parameters are determined, the phase adjustment parameters may be superimposed on the virtual clock T-TSC productThe phase of the generated clock signal.

Fig. 7 is another schematic flow chart diagram for adjusting the phase of the virtual clock T-TSC according to an embodiment of the present application. In the embodiment shown in fig. 7, it is assumed that the time delay information collected by the T-TSC is four time stamps instead of forward and backward time delays.

In step 701, timestamps T1, T2, T3 and T4 included in the time delay information are obtained.

Step 702, adjusting the timestamps T2 and T3 according to the frequency information to obtain a timestamp T2 'and a timestamp T3'.

From the frequency information, adjusting the timestamps T2 and T3 may include: clock source noise corresponding to the frequency information may be superimposed on the basis of the timestamp T2, obtaining a timestamp T2'; the clock source noise corresponding to the frequency information is superimposed on the basis of the time stamp T3, resulting in a time stamp T3'.

Step 703, determining a third time delay according to the forward time delay, the time stamp T1 and the time stamp T2'; the fourth delay is determined from the reverse delay, timestamp T3' and timestamp T4.

The third time delay may be determined according to the following equation:

D₃＝T_2’-T₁(equation 7.1)

Wherein D is₃For a third time delay, T₁Is a time stamp T1, T_2’Is a timestamp T2'.

The fourth time delay may be determined according to the following equation:

D₄＝T₄-T_3’(equation 7.2)

Wherein D is₄For a second time delay, T_3’Is a time stamp T3', T₄Is a time stamp T4.

Step 704, adjusting the phase of the virtual clock T-TSC according to the third delay and the fourth delay.

T_Offset＝(D₃-D₄) /2, (equation 7.3)

Wherein T is_OffsetRepresents the phase adjustment parameter, D₃Represents the third time delay, D₄Representing the fourth time delay. After the phase adjustment parameters are determined, the phase adjustment parameters may be superimposed on the clock signal phases generated by the virtual clock T-TSC.

In the process shown in fig. 7, it is necessary to determine the third delay and the fourth delay according to T1, T2 ', T3' and T4, and then determine the phase adjustment parameter. In other embodiments, the phase adjustment parameter may be determined directly from T1, T2 ', T3', and T4. The phase adjustment parameter may be determined, for example, according to equation 7.4:

T_Offset＝[(T_2’-T₁)-(T₄-T_3’)]/2, (equation 7.3)

Wherein T is_OffsetRepresents the phase adjustment parameter, T₁Is a time stamp T1, T_2’Is a time stamp T2', T_3’Is a time stamp T3', T₄Is a time stamp T4.

It is to be understood that the delay information for adjusting the phase in fig. 6 and 7 is a forward delay, a reverse delay, or a timestamp included in the same set of delay information.

After the virtual clock T-TSC is adjusted, clock performance evaluation information can be determined according to the virtual clock T-GM and the adjusted virtual clock T-TSC, and the clock performance evaluation information is used for indicating the clock time recovery performance of the virtual clock T-TSC.

For example, the clock performance evaluation information may include one or more of a Time Interval Error (TIE) and a Time Error (TE). The clock performance evaluation information may further include one or more of a Maximum Time Interval Error (MTIE), a Time Deviation (TDEV), a maximum time error (MaxTE), and the like.

For example, the frequency F of the virtual clock T-GM may be determined_v1And the frequency F of the adjusted virtual clock T-TSC_v2(ii) a According to F_v1And F_v2And determining the TIE.

As another example, a generation timestamp T of the virtual clock T-GM may be determined_v1And T_v4Determining the timestamp T generated by the adjusted virtual clock T-TSC_v2And T_v3(ii) a According to T_v1、T_v2、T_v3And T_v4And determining the TE.

T_v1、T_v2、T_v3And T_v4Can be obtained by the following method: obtaining a timestamp T generated by a virtual clock T-GM_v1Then after 1 packet transmission interval (1 is a positive integer greater than or equal to 1), recording a time stamp T generated by the virtual clock T-TSC_v2. Recording a time stamp T generated by a virtual clock T-TSC after a predetermined time interval has elapsed_v3Then recording the time stamp T generated by the virtual clock T-GM after 1 packet sending interval_v4。

MTIE, TEDV, and MaxTE can be determined from TE and TIE that are statistically derived over a period of time. For example, MTIE is the maximum TIE counted over a period of time, and MaxTE is the maximum TE counted over a period of time.

The determined clock performance evaluation information may be transmitted to the computer device. The administrator may obtain the clock performance evaluation information through the computer device.

The embodiment of the application can acquire the time delay information and the clock source noise of the T-TSC equipment under the condition that the reference clock works normally, and the clock of the T-TSC is simulated by utilizing the acquired time delay information and the clock source noise. The PTP message synchronization performance of the T-TSC can be estimated by utilizing the simulated clock of the T-TSC. Therefore, the PTP message synchronization performance of the T-TSC can be judged in advance before the GNSS fails, and network operation and maintenance activities are guided. By using the technical scheme of the embodiment of the application, the time delay information of a plurality of days can be collected, and the clock time recovery performance of the T-TSC can be evaluated by using the collected time delay information in a short time (for example, a plurality of minutes). The whole process can automatically output the evaluation result without exporting the acquired data, thereby reducing the participation of operation and maintenance personnel and having lower evaluation cost.

The type of clock source is not limited in the embodiments of the present application, and for example, the type of clock source may be a crystal oscillator, a rubidium clock, and other types of oscillators.

Further, the message synchronization performance evaluation of the T-TSC is realized by utilizing a virtual clock, and the generated clock signal is used for evaluating the message synchronization performance of the T-TSC, so that the normal work of the T-TSC is not influenced.

The methods shown in fig. 4 to 7 may be implemented by other computer means than a network device (e.g. T-TSC or T-BC as a slave) or a component in a network device. For example, the implementation may be realized by other computer devices (e.g., a computer device (which may be a personal computer or a server, etc.) as a management device, etc.) or components in a computer device. The method comprises the steps that network equipment of the slave equipment collects time delay information and frequency information of an actual clock of the slave equipment, the collected information is sent to computer equipment, the computer equipment determines a virtual clock T-TSC and a virtual clock T-GM according to the obtained information, and the clock time recovery performance of the slave equipment is evaluated by utilizing the determined virtual clock T-TSC.

FIG. 8 is a schematic flow chart diagram of a method of determining a clock according to the teachings of the present application. The method shown in fig. 8 may be executed by a network device or a component (e.g., a chip, a circuit, etc.) in the network device as a slave device, or may be executed by a computer device (e.g., a computer device as a management device) or a component (e.g., a chip, a circuit, etc.) in the computer device.

In the case where both the second network device and the first network device are synchronized to the reference clock, time delay information between the second network device and the first network device and frequency information of the clock of the second network device are acquired 801.

802, determining a second virtual clock according to the frequency information; and adjusting the second virtual clock according to the time delay information, wherein the adjusted second virtual clock is synchronous with a first virtual clock, and the first virtual clock is used for simulating the clock of the first network equipment.

The second network device may be a network device that performs the method shown in fig. 8.

Optionally, the delay information includes N delays, where the N delays are delays from N second network devices to the first network device, or delays from N first network devices to the second network device, and N is a positive integer greater than or equal to 2; the method further comprises the following steps: acquiring N first time stamps generated by the first virtual clock; the adjusting the second virtual clock according to the delay information includes: acquiring N second timestamps generated by the second virtual clock according to the N time delays and the N first timestamps, wherein the N second timestamps correspond to the N time delays one by one; and adjusting the frequency of the second virtual clock according to the N second time stamps and the N first time stamps.

Optionally, the delay information includes a forward delay and a reverse delay, where the forward delay is a delay from the first network device to the second network device, and the reverse delay is a delay from the second network device to the first network device, and the method further includes: acquiring a third timestamp and a sixth timestamp generated by the first virtual clock; acquiring a fourth time stamp and a fifth time stamp generated by a second virtual clock; the adjusting the second virtual clock according to the delay information includes: determining a first time delay according to the forward time delay, the third time stamp and the fourth time stamp; determining a second time delay according to the reverse time delay, the fifth time stamp and the sixth time stamp; and adjusting the phase of the second virtual clock according to the first time delay and the second time delay.

Optionally, the time delay information includes a seventh time stamp, an eighth time stamp, a ninth time stamp, and a tenth time stamp; the adjusting the second virtual clock according to the delay information includes: adjusting the eighth timestamp and the ninth timestamp according to the frequency information; adjusting the phase of the second virtual clock according to the seventh timestamp, the adjusted eighth timestamp, the adjusted ninth timestamp, and the adjusted tenth timestamp.

Optionally, the method further includes: and determining clock performance evaluation information according to the first virtual clock and the adjusted second virtual clock, wherein the clock performance evaluation information is used for indicating the clock time recovery performance of the second virtual clock.

Optionally, the determining the clock performance evaluation information according to the first virtual clock and the adjusted second virtual clock includes: determining the frequency F of the first virtual clock_v1And the adjusted frequency F of the second virtual clock_v2(ii) a According to F_v1And F_v2And determining the time interval error TIE.

Optionally, the determining the clock performance evaluation information according to the first virtual clock and the adjusted second virtual clock includes: determining a generation timestamp T of the first virtual clock_v1And T_v4Determining the adjusted timestamp T generated by the second virtual clock_v2And T_v3(ii) a According to T_v1、T_v2、T_v3And T_v4And determining the time error TE.

Fig. 9 is a schematic structural block diagram of an electronic device provided according to an embodiment of the present application. The electronic device 900 as shown in fig. 9 comprises an acquisition unit 901 and a processing unit 902. Electronic device 900 may perform the various steps of the above-described method embodiments. The electronic device 900 may be a network device or a computer device.

An obtaining unit 901, configured to obtain, when a second network device and a first network device are both synchronized to a reference clock, time delay information between the second network device and the first network device and frequency information of a clock of the second network device.

The processing unit 902 is operable to determine a second virtual clock according to the frequency information.

The processing unit 902 is further configured to adjust the second virtual clock according to the delay information, where the adjusted second virtual clock is synchronous with a first virtual clock, and the first virtual clock is used to simulate a clock of the first network device.

In some embodiments, the latency information includes N latencies, where the N latencies are latencies from N second network devices to the first network device, or latencies from N first network devices to the second network device, where N is a positive integer greater than or equal to 2; an obtaining unit 901, configured to obtain N first timestamps generated by the first virtual clock; a processing unit 902, configured to obtain, according to the N time delays and the N first time stamps, N second time stamps generated by the second virtual clock, where the N second time stamps are in one-to-one correspondence with the N time delays; and adjusting the frequency of the second virtual clock according to the N second time stamps and the N first time stamps.

In some embodiments, the delay information includes a forward delay and a reverse delay, where the forward delay is a delay from the first network device to the second network device, and the reverse delay is a delay from the second network device to the first network device, the obtaining unit 901 is further configured to obtain a third timestamp and a sixth timestamp generated by the first virtual clock; acquiring a fourth time stamp and a fifth time stamp generated by a second virtual clock; a processing unit 902, configured to determine a first time delay according to the forward time delay, the third time stamp, and the fourth time stamp; determining a second time delay according to the reverse time delay, the fifth time stamp and the sixth time stamp; and adjusting the phase of the second virtual clock according to the first time delay and the second time delay.

In some embodiments, the latency information includes a seventh timestamp, an eighth timestamp, a ninth timestamp, and a tenth timestamp; a processing unit 902, configured to adjust the eighth timestamp and the ninth timestamp according to the frequency information; adjusting the phase of the second virtual clock according to the seventh timestamp, the adjusted eighth timestamp, the adjusted ninth timestamp, and the adjusted tenth timestamp.

In some embodiments, the processing unit 902 is further configured to determine, according to the first virtual clock and the adjusted second virtual clock, clock performance evaluation information indicating a clock time recovery performance of the second virtual clock.

In some embodiments, the processing unit 902 is specifically configured to determine the frequency F of the first virtual clock_v1And the second virtual after adjustmentFrequency F of the analog clock_v2(ii) a According to F_v1And F_v2And determining the time interval error TIE.

In some embodiments, the processing unit 902 is specifically configured to determine a generation timestamp T of the first virtual clock_v1And T_v4Determining the adjusted timestamp T generated by the second virtual clock_v2And T_v3(ii) a According to T_v1、T_v2、T_v3And T_v4And determining the time error TE.

If the electronic device 900 is the second network device, the obtaining unit 901 may be a communication interface in the network device, and the processing unit 902 may be a processor of the network device.

If the electronic device 900 is a computer device, the obtaining unit 901 may be a receiver, which may be used to receive related information (e.g., time delay information, frequency information, etc.) from a second network device. The processing unit 902 may be a processor of a computer device.

It should be understood that the electronic device 900 described above may also be a chip. For example, the electronic device may be a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), a system on chip (SoC), a Central Processing Unit (CPU), a Network Processor (NP), a digital signal processing circuit (DSP), a Microcontroller (MCU), a Programmable Logic Device (PLD), other Programmable Logic Devices (PLD), a discrete gate or transistor logic device, a discrete hardware component, or other integrated chips.

If the electronic device 900 is a chip, the obtaining unit 901 may be an input/output circuit or a communication interface, and the processing unit 902 may be a processor or an integrated circuit integrated on the chip.

An embodiment of the present application further provides an electronic device, which includes a processor, coupled to a memory, for reading and executing instructions and/or program codes in the memory to perform the method described in any of the above embodiments.

An embodiment of the present application further provides a chip system, where the chip system includes a logic circuit, and the logic circuit is configured to be coupled to an input/output interface, and transmit data through the input/output interface, so as to perform the method described in any of the foregoing embodiments.

In implementation, the steps of the above method may be implemented by integrated logic circuits of hardware in a processor or instructions or program code in the form of software. The steps of a method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software modules in a processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor. To avoid repetition, it is not described in detail here.

It should be noted that the processor in the embodiments of the present application may be an integrated circuit chip having signal processing capability. In implementation, the steps of the above method embodiments may be implemented by integrated logic circuits of hardware or instructions or program code in the form of software in a processor. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.

It will be appreciated that the memory in the embodiments of the subject application can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. The non-volatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), double data rate SDRAM, enhanced SDRAM, SLDRAM, Synchronous Link DRAM (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

According to the method provided by the embodiment of the present application, the present application further provides a computer program product, which includes: computer program code which, when run on a computer, causes the computer to perform the method of any of the above embodiments.

According to the method provided by the embodiment of the present application, the present application also provides a computer readable medium, which stores program codes, and when the program codes are run on a computer, the computer is caused to execute the method of any one of the above embodiments.

According to the method provided by the embodiment of the present application, the present application further provides a system, which includes the foregoing second network device and first network device.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions or program code for causing a computer (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method of determining a clock, comprising:

under the condition that a second network device and a first network device are both synchronous to a reference clock, acquiring time delay information between the second network device and the first network device and frequency information of a clock of the second network device;

determining a second virtual clock according to the frequency information;

and adjusting the second virtual clock according to the time delay information, wherein the adjusted second virtual clock is synchronous with a first virtual clock, and the first virtual clock is used for simulating a clock of the first network equipment.

2. The method of claim 1, wherein the latency information includes N latencies, where the N latencies are latencies from N second network devices to the first network device, or latencies from N first network devices to the second network device, where N is a positive integer greater than or equal to 2;

the method further comprises the following steps: acquiring N first time stamps generated by the first virtual clock;

the adjusting the second virtual clock according to the delay information includes:

acquiring N second timestamps generated by the second virtual clock according to the N time delays and the N first timestamps, wherein the N second timestamps correspond to the N time delays one by one;

adjusting the frequency of the second virtual clock according to the N second timestamps and the N first timestamps.

3. The method of claim 1 or 2, wherein the latency information comprises a forward latency and a reverse latency, wherein the forward latency is a latency of the first network device to the second network device and the reverse latency is a latency of the second network device to the first network device,

the method further comprises the following steps:

acquiring a third timestamp and a sixth timestamp generated by the first virtual clock;

acquiring a fourth time stamp and a fifth time stamp generated by a second virtual clock;

determining a first time delay according to the forward time delay, the third time stamp and the fourth time stamp;

determining a second time delay according to the reverse time delay, the fifth time stamp and the sixth time stamp;

and adjusting the phase of the second virtual clock according to the first time delay and the second time delay.

4. The method of claim 1, wherein the latency information includes a seventh timestamp, an eighth timestamp, a ninth timestamp, and a tenth timestamp;

adjusting the eighth timestamp and the ninth timestamp according to the frequency information;

adjusting the phase of the second virtual clock according to the seventh timestamp, the adjusted eighth timestamp, the adjusted ninth timestamp, and the adjusted tenth timestamp.

5. The method of any of claims 1 to 4, further comprising: and determining clock performance evaluation information according to the first virtual clock and the adjusted second virtual clock, wherein the clock performance evaluation information is used for indicating the clock time recovery performance of the second virtual clock.

6. The method of claim 5, wherein determining clock performance evaluation information based on the first virtual clock and the adjusted second virtual clock comprises:

determining a frequency F of the first virtual clock_v1And the adjusted frequency F of the second virtual clock_v2；

According to F_v1And F_v2And determining the time interval error TIE.

7. The method of claim 5 or 6, wherein determining clock performance evaluation information from the first virtual clock and the adjusted second virtual clock comprises:

determining a generation timestamp T of the first virtual clock_v1And T_v4，

Determining an adjusted timestamp T of the second virtual clock generation_v2And T_v3；

According to T_v1、T_v2、T_v3And T_v4And determining the time error TE.

8. An electronic device, comprising:

an obtaining unit, configured to obtain, when a second network device and a first network device are both synchronized with a reference clock, time delay information between the second network device and the first network device and frequency information of a clock of the second network device;

a processing unit operable to determine a second virtual clock based on the frequency information;

the processing unit is further configured to adjust the second virtual clock according to the delay information, where the adjusted second virtual clock is synchronous with a first virtual clock, and the first virtual clock is used to simulate a clock of the first network device.

9. The electronic device of claim 8, wherein the latency information includes N latencies, where the N latencies are latencies from N second network devices to the first network device, or latencies from N first network devices to the second network device, where N is a positive integer greater than or equal to 2;

the obtaining unit is further configured to obtain N first timestamps generated by the first virtual clock;

the processing unit is specifically configured to obtain, according to the N time delays and the N first time stamps, N second time stamps generated by the second virtual clock, where the N second time stamps correspond to the N time delays one to one;

10. The electronic device of claim 8 or 9, wherein the latency information includes a forward latency and a reverse latency, wherein the forward latency is a latency of the first network device to the second network device and the reverse latency is a latency of the second network device to the first network device,

the acquiring unit is further configured to acquire a third timestamp and a sixth timestamp generated by the first virtual clock; acquiring a fourth time stamp and a fifth time stamp generated by a second virtual clock;

the processing unit is specifically configured to determine a first time delay according to the forward time delay, the third time stamp, and the fourth time stamp;

11. The electronic device of claim 8, wherein the latency information includes a seventh timestamp, an eighth timestamp, a ninth timestamp, and a tenth timestamp;

the processing unit is specifically configured to adjust the eighth timestamp and the ninth timestamp according to the frequency information;

12. The electronic device of any of claims 8-11, wherein the processing unit is further configured to determine, from the first virtual clock and the adjusted second virtual clock, clock performance evaluation information indicating a clock time recovery performance of the second virtual clock.

13. Electronic device according to claim 12, wherein the processing unit is specifically configured to determine the frequency F of the first virtual clock_v1And the adjusted frequency F of the second virtual clock_v2；

According to F_v1And F_v2And determining the time interval error TIE.

14. Electronic device according to claim 12 or 13, wherein the processing unit is specifically configured to determine a generation timestamp T of the first virtual clock_v1And T_v4，

According to T_v1、T_v2、T_v3And T_v4And determining the time error TE.

15. An electronic device, comprising: a processor for coupling with a memory, reading and executing instructions and/or program code in the memory, to perform the method of any of claims 1-7.

16. A chip system, comprising: logic circuitry for coupling with an input/output interface through which data is transferred to perform the method of any one of claims 1-7.

17. A computer-readable storage medium, characterized in that the computer-readable medium has stored program code which, when run on a computer, causes the computer to perform the method according to any one of claims 1-7.