CN105119677B - The when source of raising time service output reliability selects and switching system - Google Patents
The when source of raising time service output reliability selects and switching system Download PDFInfo
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- CN105119677B CN105119677B CN201510568304.2A CN201510568304A CN105119677B CN 105119677 B CN105119677 B CN 105119677B CN 201510568304 A CN201510568304 A CN 201510568304A CN 105119677 B CN105119677 B CN 105119677B
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Abstract
A kind of when source for improving time service output reliability of present invention offer selects and switching method, source switch method field when belonging to, including clock synchronization apparatus, source when clock synchronization apparatus is provided with multiple inputs, source processing unit when clock synchronization apparatus is provided with, when source processing unit according to it is each when source synchronous situation, source when phase difference and optimal priority selection, source when source switches to time service when will be optimal during the state change in source when each, source switching and Restoration stage of keeping time at outside, when source switching using smooth pursuit switch by the way of switch over, can ensure clock synchronization apparatus can according to it is each when source continuous change dynamic select it is optimal when source, and can continuously it track, gradually approach, avoid it is excessive between jump.
Description
Technical field
A kind of when source for improving time service output reliability of present invention offer selects and switching system, source switch method when belonging to
Field.
Background technology
Power network scale constantly expands, and power equipment and parameter are more various, and power system clock synchronization dependability is wanted
Ask also higher.
In order to improve time service output reliability, current clock synchronization apparatus, the generally use external GPS/Big Dipper,
Source when IRIG-B etc. is multiple wireless or locally wired time service source and internal high stability crystal oscillator or atomic clock are as input.And for clock
For synchronization system, the mutual standby method of generally use device.
When clock synchronization apparatus uses multiple input clock sources, the switching problem in different clocks source is certainly existed, including it is same
Switching when switching during step during outside between source and punctual outside when recovering between source and internal high stability crystal oscillator or atomic clock.It is logical
Often, CPU can to it is each when source analyze, comprehensive source when drawing optimal, will be optimal when in current time service, source is no longer optimal during source
Source when Shi Yuan switches to current time service.Now, the time in source and standard when Synchronization Clock time service output directly switches to optimal
When signal.Frequency difference and difference when this process have ignored two between source, in frequency difference or larger difference, directly switching can cause time service
It is big to export punctual signal instantaneous abrupt change.PMU equipment higher to time synchronized accuracy requirement etc. has a strong impact on generation.This hair
It is bright propose accordingly it is a kind of improve time service output reliability method, including it is more when source optimization select, and when source switch when, on time
The method of signal smoothing tracking so that tracking stepping is less than the 1us of current highest time synchronized accuracy requirement, avoids herein
During to by the harmful effect of time service equipment.
The content of the invention
Present invention aims at provide it is a kind of improve time service output reliability when source selection and switching system, it is ensured that when
Clock sychronisation can according to it is each when source continuous change dynamic select it is optimal when source, and can continuously track, gradually approach,
Avoid it is excessive between jump.
The when source of the present invention for improving time service output reliability selects and switching system, including clock synchronization apparatus,
Source when clock synchronization apparatus is provided with multiple inputs, source processing unit when clock synchronization apparatus is provided with, when source processing unit according to each
The source when synchronous situation in source when individual, phase difference and optimal priority selection, source when will be optimal during the state change in source when each
Source when switching to time service, at outside source switching and Restoration stage of keeping time, when source switching using smooth pursuit switch by the way of enter
Row switching.
The when source selection and switching system of described raising time service output reliability, the punctual meaning are when not outside
During the synchronization of source, when source processing unit using it is local when source carry out time service, when having the outside for reaching requirement again during the synchronization of source, Shi Yuan
Source time service when processing unit switches in source during local outside first place；By when source processing unit according to synchronization, phase difference and excellent
Source when the real-time dynamic select of priority selecting sequence of first level is optimal, source is awarded when making in real time to be received by time service equipment optimal time service
When, when switching time service during source, during due to two time services the time of source output phase difference be present, the present invention is using smooth pursuit
Mode switches, and without using the mode directly switched, but phase difference is divided into several pieces, then cycle accumulor, source when making original
Source is close when gradually to target, realize switching, avoid it is excessive between jump.
The when source selection and switching system of described raising time service output reliability, when source processing unit include FPGA and 32
Bit processor, FPGA and 32 bit processors are communicated by data/address bus and address bus.
The when source of described raising time service output reliability selects and switching system, 32 bit processors select synchronous first
Shi Yuan, when source of the phase difference within the standard difference time two-by-two then is selected in source when synchronous, will finally choose
Shi Yuan sets priority according to client and is ranked up, source when selecting the first.
The when source of described raising time service output reliability selects and switching system, and source processing unit carried out initial same at that time
During step, when the selection of source processing unit it is outside when source between phase difference source when being located at the outside within the standard difference time, according to
Setting priority selection in family is to carry out time service with source during outside the first in priority.
The when source of described raising time service output reliability selects and switching system, the source step-out when the outside just in time service
When, when source processing unit source when phase difference is located at the outside within the standard difference time between source when reselecting outside.Then
Set priority according to user, selection wherein priority high outside when source carry out time service.
The when source of described raising time service output reliability selects and switching system, when outside during source whole step-out, Shi Yuan
Source carries out time service when processing unit will select local, i.e., punctual；Under punctual state, when there is outside during the synchronization of source, and it is outside when
Source with it is local when source phase difference be located within the standard difference time when, source progress time service during from outside, when meeting above-mentioned condition
Outside when source when being more than or equal to two, set priority according to user and be ranked up, source carries out time service when selection is the first outside.
The when source of described raising time service output reliability selects and switching system, standard difference time are 3 μ s-7 μ s.
The when source selection and switching system of described raising time service output reliability, user set priority as user according to
Need to it is each when source setting use priority, in the case of other conditions all same select highest priority when source,
And source when source priority is higher than local when outside, the synchronizing signal in source when 32 bit processors can detect each, and select
Synchronous when source, and when source of the difference within the standard difference time between any two is selected in source when synchronous, select it
The when source of middle highest priority, it ensure that source when dynamic selects optimal；Shi Yuan selection is present in initial synchronisation, in synchronizing process
When outside in the case of source switching, punctual and punctual four kinds of recovery, the choice phase in source when initial synchronization stage is to outside, when outer
During portion source it is synchronous and two-by-two between difference within the standard difference time when, according to priority select time service in source at the outside of synchronization
Shi Yuan, when outside in synchronizing process source switching whether synchronous be first according to, whether phase difference is located at standard between source when then outside
Within the difference time, finally according to priority selected, entering the punctual stage when all outside during the step-out of source uses local
When source time service, when again have outside when source synchronization when, be first according to whether with source phase difference during local be located at the standard difference time it
It is interior, then according to priority selected.
The when source of described raising time service output reliability selects and switching system, when smooth pursuit switching includes deviation
Between, the deviation standard time and tracking the time, when FPGA test constantlies are to be changed source and it is former when source deviation time, carry out when source cut
When changing, 32 bit processors of triggering perform circulation tracking, and 32 bit processors increase by the secondary tracking time in each circulation, until inclined
The poor time is less than the deviation standard time, and circulation tracking stops, the time in source when FPGA directly exports to be changed.
The when source of described raising time service output reliability selects and switching system, deviation standard time are 0.1 μ s-1 μ s.
The when source of described raising time service output reliability selects and switching system, tracking time are 0.1 μ s-0.5 μ s.
The when source selection and switching system of described raising time service output reliability, using cumulative mode come realize with
Track, due to being provided with the cycle period of time in 32 bit processors, then the mode of a secondary tracking time is added to come gradually in each cycle
Close to it is to be switched when source, and when often increasing by the secondary tracking time, will not bring it is excessive between jump, can receive time service equipment,
Realize smooth tracking.
The present invention has the beneficial effect that compared with prior art：
The when source selection and switching system of described raising time service output reliability, by when source processing unit according to same
Source when step, the real-time dynamic select of the priority selecting sequence of phase difference and priority are optimal, make by time service equipment in real time to be received most preferably
Time service equipment time service, when switching time service equipment, because the time of two time service equipments output has the time difference, the present invention uses
The mode of smooth pursuit switches, and without using the mode directly switched, but phase difference is divided into several pieces, and then circulation is tired
Add, when making original source gradually to target when source it is close, realize switching, avoid it is excessive between jump.
Brief description of the drawings
Fig. 1 is schematic structural view of the invention；
Fig. 2 is handoff procedure functional block diagram.
In figure：1、FPGA；2nd, 32 bit processor.
Embodiment
The embodiment of the present invention is described further with reference to the present invention：
Embodiment 1：As shown in figure 1, the when source of the present invention for improving time service output reliability selects and switching system,
Including clock synchronization apparatus, source when clock synchronization apparatus is provided with multiple inputs, source processing unit when clock synchronization apparatus is provided with, when
Source processing unit according to it is each when the synchronous situation in source, phase difference and source during optimal priority selection, state in source when each
Source when source switches to time service when will be optimal during change, when source switch when, switched over by the way of smooth pursuit.
Embodiment 2：On the architecture basics described in embodiment 1, when source processing unit include FPGA1 and 32 bit processors 2,
FPGA1 and 32 bit processors 2 are communicated by data/address bus and address bus, source when 32 bit processors 2 select synchronous first, so
Select when source of the phase difference within the standard difference time two-by-two in source when synchronous afterwards, finally by choose when source according to
Client set priority be ranked up, source when selecting the first, when source include it is outside when source and it is local when source, the standard difference time note
It is 3 μ s-7 μ s for P_th, its specifically chosen logic is：Source when subscript " 0 " represents local, source when subscript " 1-5 " represents outside,
Source when subscript " x ", " y " represent any and different outside, example " | Δ TS01| " when being local source and first it is outside when source
Phase difference,
(1) when initializing, at least outside any 2 tunnel when source synchronization when, if | Δ TSxy|≤P_th, then according to default preferential
Source is synchronous when level is chosen；
(2) during punctual recovery, when source is recovered when arbitrarily outside all the way, if | Δ TS0x|≤P_th, then judge source when this is outside
Effectively；
(3) keep time when recovering, source (being assumed to be TS1, TS3) while when recovering when outside any two-way, if 1. | Δ TS01|≤
P_th and | Δ TS03|≤P_th, then source when according to priority selecting；If 2. | Δ TS01| >=P_th and | Δ TS03|≤P_th or | Δ
TS01|≤P_th and | Δ TS03| >=P_th, then choose the small when source of phase difference；If 3. | Δ TS01| >=P_th and | Δ TS03|≥
P_th, and | Δ TS13|≤P_th, then source when according to priority choosing；
(4) keep time when recovering, when outside any three tunnel source (being assumed to be TS1, TS2, TS4) while when recovering, if 1. | Δ
TS01|≤P_th and | Δ TS02|≤P_th and | Δ TS04|≤P_th, then source when according to priority choosing；If 2. | Δ TS01|≤P_
Th and | Δ TS02|≤P_th and | Δ TS04| >=P_th or | Δ TS01|≤P_th and | Δ TS02| >=P_th and | Δ TS04|≤P_
Th or | Δ TS01|≤P_th and | Δ TS02|≤P_th and | Δ TS04| >=P_th, then source when according to priority choosing；If | Δ TS01|
>=P_th and | Δ TS02| >=P_th and | Δ TS04| >=P_th, but | Δ TS12|≤P_th and | Δ TS14|≤P_th and | Δ TS24
|≤P_th, then source when according to priority choosing.
Embodiment 3：On the architecture basics described in embodiment 2, as shown in Fig. 2 smooth pursuit switching include deviation time,
The deviation standard time and tracking the time, when FPGA1 test constantlies are to be changed source and it is former when source deviation time, carry out when source switching
When, 32 bit processors 2 of triggering perform circulation tracking, and 32 bit processors 2 increase by the secondary tracking time in each circulation, until inclined
The poor time is less than the deviation standard time, and circulation tracking stops, the time in source when FPGA1 directly exports to be changed, the deviation standard time
For 0.1 μ s-1 μ s, the tracking time is 0.1 μ s-0.5 μ s.
Claims (4)
1. a kind of when source for improving time service output reliability selects and switching system, including clock synchronization apparatus, clock synchronously fill
Source when having installed multiple inputs, it is characterised in that source processing unit when clock synchronization apparatus is provided with, when source processing unit according to each
The source when synchronous situation in source when individual, phase difference and optimal priority selection, source when will be optimal during the state change in source when each
Source when switching to time service；
When source processing unit include FPGA (1) and 32 bit processors (2), FPGA (1) and 32 bit processors (2) pass through data/address bus
Communicated with address bus；
When Shi Yuan includes outside source and it is local when source, the standard difference time is designated as P_th, is 3 μ s-7 μ s, its specifically chosen logic
For：Source when subscript " 0 " represents local, source when subscript " 1-5 " represents outside, subscript " x ", " y " represent any and different outside
Shi Yuan, " | Δ TS01| " when being local source and first it is outside when source phase difference；
Source when 32 bit processors (2) select synchronous first, when then any outside all the way source with other it is outside when source enter respectively
Row contrast, if all comparing results meet | Δ TSxy|≤P_th, then selected, finally by select institute sometimes source according to
Client sets priority and is ranked up, source when selecting the first；
(1) when initializing, at least outside any 2 tunnel when source synchronization when, when arbitrarily outside all the way source with other it is outside when source distinguish
Contrasted, if all comparing results meet | Δ TSxy|≤P_th, then selected, the institute's source root sometimes that will finally select
Source is synchronous when being chosen according to pre-set priority；
(2) during punctual recovery, when source is recovered when arbitrarily outside all the way, if | Δ TS0x|≤P_th, then judge there there is source when this is outside
Effect；
(3) keep time when recovering, source when outside any two-way, it is assumed that when recovering for TS1, TS3 simultaneously, if 1. | Δ TS01|≤P_th
And | Δ TS03|≤P_th, then source when according to priority selecting；If 2. | Δ TS01| >=P_th and | Δ TS03|≤P_th or | Δ TS01|
≤ P_th and | Δ TS03| >=P_th, then choose the small when source of phase difference；If 3. | Δ TS01| >=P_th and | Δ TS03| >=P_th,
And | Δ TS13|≤P_th, then source when according to priority choosing；
(4) keep time when recovering, when outside any three tunnel source, it is assumed that when recovering for TS1, TS2, TS4 simultaneously, if 1. | Δ
TS01|≤P_th and | Δ TS02|≤P_th and | Δ TS04|≤P_th, then source when according to priority choosing；If 2. | Δ TS01|≤P_
Th and | Δ TS02|≤P_th and | Δ TS04| >=P_th or | Δ TS01|≤P_th and | Δ TS02| >=P_th and | Δ TS04|≤P_
Th or | Δ TS01|≤P_th and | Δ TS02|≤P_th and | Δ TS04| >=P_th, then source when according to priority choosing；If 3. | Δ
TS01| >=P_th and | Δ TS02| >=P_th and | Δ TS04| >=P_th, but | Δ TS12|≤P_th and | Δ TS14|≤P_th and |
ΔTS24|≤P_th, then source when according to priority choosing.
2. the when source according to claim 1 for improving time service output reliability selects and switching system, it is characterised in that awards
Constantly the switching in source be related to deviation time, the deviation standard time and tracking the time, when FPGA (1) test constantly is to be changed source and it is former when
The deviation time in source, when when carrying out, source switches, 32 bit processors of triggering (2) perform circulation tracking, and 32 bit processors (2) are every
Increase by the secondary tracking time in secondary circulation, until deviation time is less than the deviation standard time, circulation tracking stops, and FPGA (1) is straight
Connect the time in source when exporting to be changed.
3. the when source according to claim 2 for improving time service output reliability selects and switching system, it is characterised in that partially
The poor standard time is 0.1 μ s-1 μ s.
4. the when source according to claim 2 for improving time service output reliability selects and switching system, it is characterised in that with
The track time is 0.1 μ s-0.5 μ s.
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| CN110868268A (en) * | 2019-11-01 | 2020-03-06 | 南方电网数字电网研究院有限公司 | Local time timing method, device, timing equipment and storage medium |
| CN111427074B (en) * | 2020-06-10 | 2020-10-09 | 天津七一二通信广播股份有限公司 | GBAS-based high-reliability time system service equipment |
| CN114585074A (en) * | 2020-11-30 | 2022-06-03 | 中兴通讯股份有限公司 | Air interface time service method of mobile terminal, mobile terminal and readable storage medium |
| CN112886951B (en) * | 2021-01-15 | 2023-08-04 | 西安微电子技术研究所 | Multi-clock source seamless switching circuit and method of high-precision time keeping equipment |
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| CN101079630A (en) * | 2006-05-23 | 2007-11-28 | 中兴通讯股份有限公司 | A digital phase lock loop device for smooth switching of clock phase and its method |
| CN101860365A (en) * | 2010-06-12 | 2010-10-13 | 中兴通讯股份有限公司 | Reference clock source switching method and device |
| CN104601317A (en) * | 2014-12-31 | 2015-05-06 | 南京大全自动化科技有限公司 | Synchronous clock device of FPGA and control method thereof |
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2015
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Patent Citations (4)
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| EP0228685A2 (en) * | 1985-12-30 | 1987-07-15 | AT&T Corp. | Phase adjustment system |
| CN101079630A (en) * | 2006-05-23 | 2007-11-28 | 中兴通讯股份有限公司 | A digital phase lock loop device for smooth switching of clock phase and its method |
| CN101860365A (en) * | 2010-06-12 | 2010-10-13 | 中兴通讯股份有限公司 | Reference clock source switching method and device |
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