CN106098612A - Based on the manufacture method of wafer scale uniaxial strain Ge on the silicon nitride stress film SiN enterree with scale effect - Google Patents
Based on the manufacture method of wafer scale uniaxial strain Ge on the silicon nitride stress film SiN enterree with scale effect Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 229910052581 Si3N4 Inorganic materials 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 title claims abstract description 10
- 230000000694 effects Effects 0.000 title claims abstract description 9
- 239000012528 membrane Substances 0.000 claims abstract description 33
- 239000010409 thin film Substances 0.000 claims abstract description 25
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- 238000001259 photo etching Methods 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 7
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
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- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
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- 230000000873 masking effect Effects 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 229910052682 stishovite Inorganic materials 0.000 claims description 5
- 229910052905 tridymite Inorganic materials 0.000 claims description 5
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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Abstract
The invention discloses the manufacture method of wafer scale uniaxial strain Ge on a kind of SiN enterree based on silicon nitride stress film with scale effect, implementation step is: be carried out GeOI wafer, and carries out He ion implanting;Deposit the compressive stress SiN thin film of more than 1.1GPa or the tensile stress SiN thin film of more than 1.1GPa on GeOI wafer top layer Ge layer after ion implantation, and etch SiN thin film and be in strip array;GeOI wafer with SiN membrane array is annealed;SiN membrane array on erosion removal GeOI crystal column surface, obtains wafer scale uniaxial strain GeOI material.The present invention utilizes SiN enterree uniaxial tension under bar shaped SiN membrane array effect or uniaxial compression plastic deformation to introduce strain at top layer Ge layer, can make the GeOI wafer needed for ultrahigh speed, low-power consumption, radio-resisting semiconductor device and chip.
Description
Technical field
The invention belongs to microelectronics technology, relate to semiconductor substrate materials Manufacturing Techniques, specifically one
The manufacture method of wafer scale uniaxial strain Ge material on kind of SiN enterree, can make for ultrahigh speed, low-power consumption, radioprotective,
GeOI wafer needed for high power integrated semiconductor device and chip.
Background technology
The most known, the electronics of quasiconductor Ge and hole mobility are 2.8 times and 4.2 times of Si respectively, its hole migration
Rate is the highest in all quasiconductors.The strain Ge technology of Ge device and integrated circuit that introduced by strain gauge technique is to carrier mobility
Rate promotes substantially, and the such as hole mobility of buried channel strain Ge can improve 6-8 times.Therefore, Ge and strain Ge will be 16 nanometers and
Following technique Si based CMOS devices and the optimal channel material of integrated circuit.Ge also has the photo electric being much better than Si, in detection
Device, manipulator, fiber waveguide, optical transmitting set, solaode etc. have extremely wide application.
Owing to energy gap only has 0.67eV, cause Ge device bigger with the electric leakage of the substrate of circuit.And GeOI is just
Solve substrate leakage currents and develop, be widely used to the manufacture of semiconductor device and integrated circuit at present.GeOI wafer
Generally " Ge/ insulating barrier/Si " three-decker.The enterree of GeOI wafer is typically SiO2, its thermal conductivity is only the hundred of silicon
/ mono-, hinder GeOI in high temperature, the application of high-power aspect;Its dielectric constant is only 3.9, is easily caused signal transmission and loses
Lose, also counteracts that GeOI application in high density, high power integrated circuit.And replace SiO with SiN2GeOI have more preferably
Insulating properties and thermal diffusivity, have been widely used in high temperature, big power consumption, high power integrated circuit.
Combine germanium GeOI on the strain insulating barrier of strain Ge and GeOI advantage be the novel ultrahigh speed of research and development, low-power consumption,
Radioprotective, high integration silicon-based devices and chip provide a kind of new solution, are electrically integrated at light, the aspect such as system level chip
There is important application prospect.
Traditional strain GeOI, the most on the insulating layer direct epitaxial growing strain Ge in silicon SOI wafer, or first brilliant at SOI
The SiGe layer of circle Epitaxial growth Ge content gradually variational makees empty substrate, then the strained ge layer needed for this SiGe layer Epitaxial growth.
The major defect of tradition strain GeOI is that dislocation density is high, can only be Biaxial Compressive to be strained, mobility promotes the highest, the empty substrate of SiGe
Add hot expense and cost of manufacture, SiGe void substrate have had a strong impact on device and the heat radiation of circuit, strained ge layer critical thickness
Limited by Ge component, under High-Field the lifting of hole mobility can degenerate.
Relative to biaxial strain GeOI, the lifting of carrier mobility is not degenerated by uniaxial strain with the rising of electric field,
And under identical dependent variable, carrier mobility is promoted higher than biaxial strain carrier mobility by uniaxial strain
Promote.
The a kind of of Xian Electronics Science and Technology University's acquisition in 2011 uses mechanical bend the making SiN that anneals in the bent state
The new method patent (CN201110361530.5) of enterree wafer level uniaxial strain GeOI material, buries absolutely in order to make SiN
Edge layer wafer scale overall situation uniaxial strain GeOI material, its main technique is as it is shown in figure 1, step is as follows:
1, GeOI wafer top layer Ge layer is upwards placed on arc-shaped bend platform, its bending direction and<110>or<100>side
To parallel.
2, two cylindrical horizontal depression bars in bending are individually positioned in GeOI wafer two ends, use cylindrical horizontal pressure
Bar makes GeOI wafer fit completely with arc-shaped table board.
3, anneal 1.5 hours to 10 hours in the annealing furnace of temperature 200 DEG C to 1250 DEG C, make SiN enterree at this
During occur plastic deformation.
4, after unloading the reinstatement of GeOI wafer, due to the plastic deformation of SiN enterree, forming top layer overall situation single shaft should
Become Ge layer.
But there is following shortcoming in the method: 1) poor from traditional integrated circuit processing compatibility: different in order to obtain
The GeOI of dependent variable, the method needs the extra bending making corresponding different curvature radius, and made bending needs
Want compatible existing annealing device.2) reliability is poor: this process need to use depression bar applying mechanical external force to make GeOI wafer curved
Song, can introduce defect in top layer Ge;If GeOI wafer bow is excessive, disk fragmentation can be caused.3) owing to worrying that GeOI is brilliant
Circle fragmentation, so mechanical bent flexibility can not be excessive, which limits the size of the dependent variable introduced in top layer Ge, institute
The dependent variable that can realize is less.
Summary of the invention
Present invention aims to above-mentioned the deficiencies in the prior art, propose a kind of based on silicon nitride stress film and chi
The manufacture method of wafer scale uniaxial strain Ge on the SiN enterree of degree effect, to reduce the processing technology of strain GeOI wafer
Complexity and cost, improve the dependent variable of uniaxial strain GeOI, strengthens electron mobility and the hole mobility of GeOI wafer,
Meet the electrical and optical performance requirement of GeOI device and integrated circuit.
For achieving the above object, technical scheme includes the following:
(1) being carried out GeOI wafer, this GeOI wafer includes top layer Ge layer, SiN enterree and Si substrate three layers
Structure;
(2) cleaned GeOI wafer is carried out He ion implanting, will He ion implanting bury absolutely to the SiN of GeOI wafer
At edge layer and Si substrate interface;
(3) pressure using technique more than the deposit-1.1GPa such as PECVD on GeOI wafer top layer Ge after ion implantation should
The tensile stress SiN thin film of power SiN thin film or more than 1.1GPa;
(4) utilize semiconductor lithography and etching technics, SiN thin film is carried out bar pattern, form bar width and spacing is equal
It is the bar shaped SiN membrane array of 0.13 μm~0.19 μm, in order to eliminate the stress of width, obtains only length direction stress
Silicon nitride compressive stress bar or tensile stress bar, make top layer Ge layer and SiN enterree that overall uniaxial tensile deformation or list to occur
Axle compressive deformation, and then cause GeOI wafer to be changed into the uniaxial strain GeOI of wafer scale;
(5) the GeOI wafer that top layer Ge surface is formed bar shaped SiN membrane array is annealed, and makes the stress of SiN thin film
Further enhance, and make SiN enterree generation plastic deformation, it is ensured that after SiN thin film is removed, top layer Ge ply stress does not disappears;
(6) remove the bar shaped SiN membrane array on GeOI crystal column surface by wet etching, finally give wafer scale single shaft
Tensile strain GeOI or single shaft compressive strain GeOI material.
Present invention have the advantage that
1 is completely compatible with existing integrated circuit technology: the making of the wafer scale uniaxial strain SOI of the present invention, can pass through
The existing conventional Si process such as pecvd process deposit, figure photoetching, etching realize, and technique is simple, it is not necessary to additional customized technique
Equipment needed thereby.
2, reliability is high: the present invention is by introducing wafer scale uniaxial strain by heavily stressed SiN stripe array, it is not necessary to right
GeOI applies mechanical external force, thus prevent disk to bend, it is to avoid the defect in top layer Ge produces and disk fragmentation, carries
High yield rate.
3, low cost: due to the fact that the heavily stressed SiN stripe array of employing, the uniaxial strain of wafer scale can be introduced directly into,
Therefore common SiN enterree GeOI wafer can be used to strain GeOI material to make the single shaft overall situation, rather than biaxial strain GeOI is brilliant
Circle, reduces process costs.
4, dependent variable is big: the present invention makes top layer Ge layer and SiN enterree by the simple stress of bar shaped SiN stripe array
Occur overall uniaxial tensile deformation or uniaxial compression deformation to introduce strain, can increase by adjusting SiN film deposition art
Big dependent variable.
5, flatness is high: the present invention does not use mechanical external force to make GeOI wafer bow, is not result in GeOI wafer bow, from
And make GeOI crystal column surface smooth.
6, suppression parasitic reaction: use SiO2Easily and germanium produces unnecessary reaction to do enterree, generates GeO, uses
SiN does enterree and can substantially suppress this to react.
Accompanying drawing explanation
Fig. 1 is the process chart of existing wafer scale uniaxial strain GeOI wafer.
Fig. 2 is wafer scale uniaxial strain Ge process chart on the SiN enterree of the present invention.
Fig. 3 is the top view of the bar shaped SiN membrane array being deposited in the present invention on top layer Ge layer.
Detailed description of the invention
The know-why of the present invention is as follows:
The present invention is according to ion implantation technology principle, by the interface of He ion implanting to SiN enterree Yu substrate Si layer
Place, can cause the interface cohesion of SiN enterree and substrate Si layer to become loose, so that SiN enterree and top layer thereon
Ge layer is susceptible to strain accordingly after depositing heavily stressed SiN thin film.Again according to the scale effect principle of the mechanics of materials, pass through
Semiconductor process technique making width and spacing are the bar shaped SiN membrane array of 130nm~190nm so that strip width side
To Stress Release, and do not change, so that bar shaped SiN membrane array has list along the stress intensity in bar length direction
Axial compression stress or single shaft tensile stress, to introduce single shaft tensile strain or single shaft compressive strain in top layer Ge layer and SiN enterree.?
In annealing process, the stress of bar shaped SiN membrane array can further enhance, and also result in SiN enterree produce stretching or
The plastic deformation of compression, and top layer Si is still in elastic deformation.After removing bar shaped SiN membrane array, due to SiN enterree
Stretching or the plastic deformation effect of compression, cause top layer Si generation single shaft tensile strain or single shaft compressive strain, ultimately forms to have and answers
Become the wafer scale uniaxial strain SOI of top layer Ge layer.
SiN enterree GeOI wafer includes 3 inches, 4 inches, 5 inches, 6 inches, 8 inches, the different rule of 12 inches
Lattice, its top layer Ge layer thickness is 100~500nm.
With reference to Fig. 2, the present invention provides wafer scale list on SiN enterree based on silicon nitride stress film and scale effect
Three embodiments of the manufacture method of axial strain Ge, i.e. prepare 4 inches, 8 inches, the SiN enterree uniaxial strain of 12 inches
GeOI wafer material, the SiN enterree GeOI wafer of different size all includes three-decker: Si substrate 3, SiN enterree 2
With top layer Ge layer 1, as shown in Figure 2 a.Wherein:
4 inches of SiN enterree GeOI wafers, the thickness of its Si substrate is 600 μm, and the thickness of SiN enterree is
500nm, the thickness of top layer Ge layer is 150nm;
8 inches of SiN enterree GeOI wafers, the thickness of its Si substrate is 600 μm, and the thickness of SiN enterree is
500nm, the thickness of top layer Ge layer is 250nm;
12 inches of SiN enterree GeOI wafers, the thickness of its Si substrate is 600 μm, and the thickness of SiN enterree is
500nm, the thickness of top layer Ge layer is 350nm.
Embodiment 1, prepares 4 inches of SiN enterree single shaft tensile strain GeOI wafer materials.
Step 1: clean SiN enterree GeOI wafer, to remove surface contaminant.
(1.1) use acetone and isopropanol are to GeOI wafer alternately ultrasonic waves for cleaning, organic to remove substrate surface
Thing pollutes;
(1.2) the configuration ammonia of 1:1:3, hydrogen peroxide, the mixed solution of deionized water, and it is heated to 120 DEG C, GeOI is brilliant
Circle is placed in this mixed solution immersion 12 minutes, uses a large amount of deionized water rinsing after taking-up, inorganic to remove GeOI crystal column surface
Pollutant;
(1.3) GeOI wafer HF acid buffer is soaked 2 minutes, remove the oxide layer on surface.
Step 2: ion implanting.
The GeOI wafer cleaned is carried out ion implanting, so that loosening in Si substrate 3 and SiN enterree 2 interface 4, as
Shown in Fig. 2 b.
The process conditions of ion implanting are: the ion of injection is He ion, and implantation dosage is 1.1E14cm-2, Implantation Energy
70Kev。
Step 3: deposit SiN thin film.
Use PECVD plasma-reinforced chemical vapor deposition process, at the top layer of the GeOI wafer completing ion implanting
The surface deposition thickness of Ge layer 1 is 1.0 μm, and stress is the compressive stress SiN thin film 5 of-1.1GPa, as shown in Figure 2 c.
The process conditions of deposit are: high frequency HF power is 0.22KW, and low frequency LF power is 0.82KW, high-purity Si H4Flow is
0.41slm, high-purity N H3Flow is 2.2slm, and high pure nitrogen flow is 2.2slm, reative cell pressure 2.8Torr, reaction chamber temperature
It it is 400 DEG C.
Step 4: utilize semiconductor lithography and lithographic technique, etches compressive stress SiN thin film 5, forms bar shaped SiN membrane array
6, as shown in Figure 2 d.
(4.1) in compressive stress SiN layer 5, it is coated with positive photoetching rubber, photoresist is dried, utilize and there is strip width and be spaced all
Being that the photolithography plate of 0.19 μm is exposed, the region of exposure is the strip array that width and interval are 0.19 μm, uses developer solution
Get rid of exposure area and be soluble in the positive photoetching rubber of developer solution, SiN layer is formed strip photoresist masking membrane array;
(4.2) using reactive ion etching RIE technique, be 4Pa at reaction chamber pressure, reaction chamber temperature is 40 DEG C, substrate
Temperature is 5 DEG C, and 13.56MHz HFRF power is 400W, etching gas CHF4Flow is 30sccm, O2Gas flow is
Under conditions of 3sccm, performing etching the compressive stress SiN thin film 5 being deposited on GeOI wafer top layer Ge layer, forming width is
The bar shaped SiN membrane array 6 of 0.19 μm, in order to eliminate the stress of width, obtains the silicon nitride of only length direction stress
Stress bar, the GeOI wafer top view with SiN membrane array 6 obtained is as shown in Figure 3;
(4.3) photoresist in bar shaped SiN membrane array is removed.
Step 5: annealing.
The GeOI wafer that top layer Ge layer 1 surface is formed bar shaped SiN membrane array 6 is annealed, and as shown in Figure 2 e, i.e. exists
Heating rate is 4 DEG C/min, and temperature is annealed 3.2 hours under conditions of being 310 DEG C in noble gas He, then with 4 DEG C/min's
Speed is lowered the temperature.In annealing process, the stress of bar shaped SiN membrane array 6 can further enhance, and causes SiN enterree 2 to produce
The plastic deformation of stretching.
Step 6: remove the bar shaped SiN membrane array 6 on GeOI wafer top layer Ge layer 1 surface, as shown in figure 2f.
The GeOI wafer that deposited bar shaped SiN membrane array 6 is put in the phosphoric acid solution that volume fraction is 85% 150
DEG C carry out the wet etching of 6 minutes, finally give the single shaft tensile strain GeOI wafer material with strain top layer Ge layer 7.
Embodiment 2, prepares 8 inches of SiN enterree single shaft compressive strain GeOI wafer materials.
Step one: clean SiN enterree GeOI wafer, to remove surface contaminant.
The realization of this step is identical with the step 1 of embodiment 1.
Step 2: be 1.1E15cm to the GeOI wafer implantation dosage cleaned-2, the He ion of energy 110Kev, so that
Loosen, as shown in Figure 2 b in Si substrate 3 and SiN enterree 2 interface 4.
Step 3: use PECVD plasma-reinforced chemical vapor deposition process, complete the GeOI wafer of ion implanting
Top layer Ge layer 1 surface deposition thickness be 1.1 μm, stress is the tensile stress SiN thin film 5 of 1.2GPa, as shown in Figure 2 c.
The process conditions of deposit are: high frequency HF power is 1.3KW, and low frequency LF power is 0.31KW, high-purity Si H4Flow is
0.31slm, high-purity N H3Flow is 1.9slm, and high pure nitrogen flow is 1.1slm, and reative cell pressure is 3.1Torr, reacts room temperature
Degree is 400 DEG C.
Step 4: utilize semiconductor lithography and lithographic technique, etches tensile stress SiN thin film 5, forms bar shaped SiN thin film battle array
Row 6, as shown in Figure 2 d.
(4a) in tensile stress SiN layer 5, it is coated with positive photoetching rubber, photoresist is dried, utilize and there is strip width and be spaced all
Being that the photolithography plate of 0.17 μm is exposed, the region of exposure is the strip array that width and interval are 0.17 μm, uses developer solution
Get rid of exposure area and be soluble in the positive photoetching rubber of developer solution, SiN layer is formed strip photoresist masking membrane array;
(4b) reactive ion etching RIE technique is used, to the tensile stress SiN thin film being deposited on GeOI wafer top layer Ge layer
5 perform etching the bar shaped SiN membrane array 6 that formation width is 0.17 μm, in order to eliminate the stress of width, the longest
The silicon nitride stress bar of degree direction stress, the GeOI wafer top view with SiN membrane array 6 obtained is as it is shown on figure 3, react
Ion etching RIE process conditions are identical with the step (4.1) in embodiment 1;
(4c) photoresist in bar shaped SiN membrane array 6 is removed.
Step 5: the GeOI wafer that top layer Ge layer 1 surface is formed bar shaped SiN membrane array 6 is annealed, such as Fig. 2 e institute
Showing, be i.e. 4 DEG C/min at heating rate, temperature is annealed 2.7 hours under conditions of being 360 DEG C in noble gas He, then with 4
DEG C/cooling of the speed of min.In annealing process, the stress of bar shaped SiN membrane array 6 can further enhance, and causes SiN to bury absolutely
Edge layer 2 produces the plastic deformation of compression.
Step 6: remove the bar shaped SiN membrane array 6 on GeOI wafer top layer Ge layer 1 surface, as shown in figure 2f.
The GeOI wafer that deposited bar shaped SiN membrane array 6 is put in the phosphoric acid solution that volume fraction is 85% 170
DEG C carry out the wet etching of 9 minutes, finally give the single shaft compressive strain GeOI wafer material with strain top layer Ge layer 7.
Embodiment 3, prepares 12 inches of SiN enterree single shaft tensile strain GeOI wafer materials.
Step A: clean SiN enterree GeOI wafer, to remove surface contaminant.
The realization of this step is identical with the step 1 of embodiment 1.
Step B: the GeOI wafer cleaned is carried out ion implanting, so that Si substrate 3 and SiN enterree 2 interface 4 is dredged
Pine, as shown in Figure 2 b.
The technique of ion implanting is: the ion of injection is He ion, and implantation dosage is 1.1E16cm-2, Implantation Energy
150Kev。
Step C: deposit high pressure stress SiN thin film.
Using PECVD plasma-reinforced chemical vapor deposition process, be 0.41KW at high frequency HF power, low frequency LF power is
0.61KW, high-purity Si H4Flow is 0.21slm, high-purity N H3Flow is 2.4slm, and high pure nitrogen flow is 2.6slm, reacts chamber pressure
Strong is 3.0Torr, under conditions of reaction chamber temperature is 400 DEG C, and top layer Ge layer 1 table of the GeOI wafer after completing ion implanting
Face deposition thickness is 1.2 μm, and stress intensity is the compressive stress SiN thin film 5 of-1.3GPa, as shown in Figure 2 c.
Step D: etching compressive stress SiN thin film.
(D1) utilize semiconductor lithography and lithographic technique to be coated with positive photoetching rubber in compressive stress SiN layer 5, photoresist dried,
Utilizing and have strip width and be spaced and be the photolithography plate of 0.13 μm and be exposed, the region of exposure is width and interval is
The strip array of 0.13 μm, gets rid of exposure area with developer solution and is soluble in the positive photoetching rubber of developer solution, forms bar in SiN layer
Shape photoresist masking membrane array;
(D2) reactive ion etching RIE technique is used, to the compressive stress SiN thin film being deposited on GeOI wafer top layer Ge layer
5 perform etching, and form the bar shaped SiN membrane array 6 that width is 0.13 μm, as shown in Figure 2 d.In order to eliminate answering of width
Power, obtains the silicon nitride stress bar of only length direction stress, the GeOI wafer top view with SiN membrane array 6 obtained
As it is shown on figure 3, reactive ion etching RIE process conditions are identical with the step of embodiment 1 (4.1);
(D3) photoresist in bar shaped SiN membrane array 6 is removed.
Step E: ion implanting.
The GeOI wafer that top layer Ge layer 1 surface is formed bar shaped SiN membrane array 6 is annealed, and as shown in Figure 2 e, i.e. exists
Heating rate is 4 DEG C/min, and temperature is annealed 2.2 hours under conditions of being 410 DEG C in noble gas He, then with 4 DEG C/min's
Speed is lowered the temperature.In annealing process, the stress of bar shaped SiN membrane array 6 can further enhance, and causes SiN enterree 2 to produce
The plastic deformation of stretching.
Step F: remove the bar shaped SiN membrane array 6 on GeOI wafer top layer Ge layer 1 surface, as shown in figure 2f.
The GeOI wafer that deposited bar shaped SiN membrane array 6 is put in the phosphoric acid solution that volume fraction is 85% 190
DEG C carry out the wet etching of 12 minutes, finally give the single shaft tensile strain GeOI wafer material with strain top layer Ge layer 7.
Claims (9)
1. the manufacture method of wafer scale uniaxial strain Ge on SiN enterree based on silicon nitride stress film and scale effect,
Comprise the steps:
(1) being carried out GeOI wafer, this GeOI wafer includes top layer Ge layer, SiO2Enterree and Si substrate three-decker;
(2) cleaned GeOI wafer is carried out He ion implanting, will He ion implanting to the SiO of GeOI wafer2Enterree
At Si substrate interface;
(3) compressive stress of technique more than the deposit-1.1GPa such as PECVD is used on GeOI wafer top layer Ge after ion implantation
The tensile stress SiN thin film of SiN thin film or more than 1.1GPa;
(4) utilize semiconductor lithography and dry etch process, SiN thin film is carried out bar pattern, form bar width and spacing is equal
It is the bar shaped SiN membrane array of 0.13 μm~0.19 μm, in order to eliminate the stress of width, obtains only length direction stress
Silicon nitride compressive stress bar or tensile stress bar, make top layer Ge layer and SiO2There is overall uniaxial tensile deformation or list in enterree
Axle compressive deformation, and then cause GeOI wafer to be changed into the uniaxial strain GeOI of wafer scale;
(5) the GeOI wafer that top layer Ge surface is formed bar shaped SiN membrane array is annealed, and makes the stress of SiN thin film enter one
Step strengthens, and makes SiO2Enterree generation plastic deformation, it is ensured that after SiN thin film is removed, top layer Ge ply stress does not disappears;
(6) being removed the bar shaped SiN membrane array on GeOI crystal column surface by wet etching, finally giving that wafer scale single shaft opens should
Become GeOI or single shaft compressive strain GeOI material.
Method the most according to claim 1, wherein the GeOI wafer in step (1), it includes 3 inches, 4 inches, 5 English
Very little, 6 inches, 8 inches, the different size of 12 inches, its top layer Ge layer thickness is 100~500nm.
Method the most according to claim 1, is wherein carried out GeOI wafer in step (1), and its step is as follows:
(1a) use acetone and isopropanol are to GeOI wafer alternately ultrasonic waves for cleaning, dirty to remove substrate surface Organic substance
Dye;
(1b) the configuration ammonia of 1:1:3, hydrogen peroxide, the mixed solution of deionized water, and it is heated to 120 DEG C, GeOI wafer is put
Soak 12 minutes in this mixed solution, use a large amount of deionized water rinsing after taking-up, to remove GeOI crystal column surface inorganic pollution
Thing;
(1c) GeOI wafer HF acid buffer is soaked 2 minutes, remove the oxide layer on surface.
Method the most according to claim 1, the wherein ion implanting in step (2), use He ion, its implantation dosage from
1.1E14cm-2~1.1E16cm-2Change, Implantation Energy changes from 70Kev~150Kev according to the difference of top layer Ge layer thickness.
Method the most according to claim 1, wherein step (3) deposits the technique of compressive stress SiN layer on top layer Ge, uses
Plasma chemical vapor deposition pecvd process, its parameter is as follows:
High frequency power HF is 0.21KW~0.41KW;
Low frequency power LF is from 0.61KW~0.81KW;
High-purity Si H4Flow 0.21slm~0.41slm, high-purity N H3Flow 2.2slm~2.4slm, high pure nitrogen flow 2.2slm
~2.6slm;
Reative cell pressure 2.8Torr~3.0Torr;
Reaction chamber temperature 400 DEG C;
Deposition thickness 1.0 μm~1.2 μm.
Method the most according to claim 1, wherein step (3) deposits the technique of tensile stress SiN layer on top layer Ge, uses
Plasma chemical vapor deposition pecvd process, its parameter is as follows:
High frequency power HF is 1.2KW~1.4KW;
Low frequency power LF is from 0.21KW~0.41KW;
High-purity Si H4Flow 0.21slm~0.41slm, high-purity N H3Flow 1.8slm~2.0slm, high pure nitrogen flow 0.9slm
~1.3slm;
Reative cell pressure 3.0Torr~3.2Torr;
Reaction chamber temperature 400 DEG C;
Deposition thickness 0.9 μm~1.1 μm.
Method the most according to claim 1, it is characterised in that use photoetching and reactive ion etching RIE work in step (4)
SiN layer is etched into strip array by process, carries out as follows:
(4a) in SiN layer, be coated with positive photoetching rubber, photoresist dried, utilize there is strip width and interval be 0.13 μm~
The photolithography plate of 0.19 μm is exposed, and the region of exposure is the strip array that width and interval are 0.13 μm~0.19 μm, uses
Developer solution is got rid of exposure area and is soluble in the positive photoetching rubber of developer solution, forms strip photoresist masking membrane array in SiN layer;
(4b) use reactive ion etching RIE technique to etch away the unglazed photoresist being deposited on GeOI wafer top layer Ge and shelter film district
SiN under territory, i.e. exposure area, leaves the SiN under strip photoresist masking film, obtain width and spacing be 0.13 μm~
The SiN strip array of 0.19 μm;
(4c) remove strip photoresist masking film, only leave SiN strip array.
Method the most according to claim 1, the wherein annealing in step (5), its process conditions are: temperature: 310 DEG C~
410 DEG C, the time: 2.2~3.2 hours, environment: He, Ne, Ar or their mixture.
Method the most according to claim 1, wherein the wet etching in step (6) removes SiN thin film, is to use volume integral
Number is the phosphoric acid solution of 85%, carries out the etching of 5~20 minutes at temperature is 150 DEG C~200 DEG C.
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