CN106098608B - The production method of wafer scale uniaxial strain SiGe on SiN enterree based on silicon nitride stress film and scale effect - Google Patents
The production method of wafer scale uniaxial strain SiGe on SiN enterree based on silicon nitride stress film and scale effect Download PDFInfo
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Abstract
The invention discloses the production method of wafer scale uniaxial strain SiGe on SiN enterree based on silicon nitride stress film and scale effect a kind of, implementation step is：SiGe SGOI wafer on insulating layer is cleaned, and carries out He ion implanting；The compression SiN film of deposit -1.2GPa or more or the tensile stress SiN film of 1.2GPa or more are deposited in SGOI wafer top layer SiGe layer after ion implantation, and are etched SiN film and be in strip array；It anneals to the SGOI wafer with SiN membrane array；SiN membrane array on erosion removal SGOI crystal column surface obtains wafer scale uniaxial strain SGOI material.The present invention is strained using SiN enterree being uniaxially stretched under the effect of bar shaped SiN membrane array or uniaxial compression plastic deformation in Ge layers of introducing of top layer, can be made for SGOI wafer needed for high temperature, high power, radiation hardened integrated circuit.
Description
Technical field
The invention belongs to microelectronics technologies, are related to semiconductor substrate materials Manufacturing Techniques, specifically one
The production method of wafer scale uniaxial strain sige material on kind of SiN enterree, can make for high temperature, big power consumption, high power,
SGOI wafer needed for radiation hardened integrated circuit.
Background technique
It is known in the industry, the advantages of SiGe has both Si and Ge, with the working frequency of its device and circuit height, small power consumption, ratio
Many advantages, such as GaAs is inexpensive, compatible with Si CMOS technology, at low cost produces in microwave device, mobile communication, high-frequency circuit etc.
Industry field has a wide range of applications and competitive advantage.SiGe still extremely excellent photoelectric material, detector, modulator,
Optical waveguide, optical transmitting set, solar cell, photoelectricity are integrated etc. to have a wide range of applications.It is similar to strain Si, strain SiGe
With the high characteristic of carrier mobility.
Compared with body Si, SOI device has low in energy consumption, strong antijamming capability with circuit, integration density height, speed height, posts
Raw capacitor is small, simple process, Radiation hardness are strong and the advantages that can thoroughly eliminating the latch-up of Bulk CMOS, at a high speed, it is low
The devices such as power consumption, Flouride-resistani acid phesphatase and circuit field are widely used, and are the developing direction of 21 century Si integrated circuit technique.
Strained SiGe SSGOI combines the advantages of strain SiGe and SOI on insulating layer, to research and develop novel ultrahigh speed, low
Power consumption, anti-radiation, high integration silicon-based devices and chip provide a kind of new solution, photoelectricity is integrated, system level chip
Etc. also have important application prospect.SGOI wafer is generally " SiGe/ insulating layer/Si " three-decker.SGOI wafer
Enterree is usually SiO2, thermal conductivity is only 1 the percent of silicon, hinders SGOI and answers at high temperature, high-power aspect
With；Its dielectric constant is only 3.9, easily leads to signal transmission and loses, and also counteracts SGOI material in high density, the integrated electricity of high power
Application in road.And replace SiO with SiN2SGOI there is better insulating properties and thermal diffusivity, have been widely used in high temperature, big
In power-consumption integrated circuit.
Traditional strain SGOI is the twin shaft compressive strain based on SOI wafer, i.e., the direct growth strain in SOI wafer
SiGe, or the empty substrate of SiGe layer work of Ge content gradually variational is first grown in SOI wafer, then in the SiGe layer needed for epitaxial growth
Strained sige layer.The major defect of tradition strain SGOI is that dislocation density is high, can only be twin shaft compressive strain, mobility is promoted not
High, SiGe void substrate increases hot expense and cost of manufacture, SiGe void substrate have seriously affected the heat dissipation of device and circuit, strain
SiGe layer critical thickness is limited by Ge component, the promotion of hole mobility can degenerate under High-Field.Relative to biaxial strain SGOI,
Uniaxial strain does not degenerate to the promotion of carrier mobility with the raising of electric field, and under identical dependent variable, single shaft is answered
Become and promotion of the biaxial strain to carrier mobility is higher than to the promotion of carrier mobility.
The a kind of of Xian Electronics Science and Technology University's acquisition in 2011 uses mechanical bend and in the bent state annealing production SiN
The new method patent (CN201110361514.6) of enterree wafer level uniaxial strain SGOI material, is buried absolutely to make SiN
Edge layer wafer scale overall situation uniaxial strain SGOI material, main technique is as shown in Figure 1, steps are as follows：
1, SiN enterree SGOI wafer top layer SiGe layer is placed on upwards on arc-shaped bend platform, bending direction with<
110>Or<100>Direction is parallel.
2, two cylindrical horizontal compression bars in bending are individually positioned in SGOI wafer both ends, with cylindrical horizontal pressure
Bar is bonded SGOI wafer completely with arc-shaped table board.
3, it anneals 1.5 hours to 10 hours in 200 DEG C to 1250 DEG C of temperature of annealing furnace, makes SiN enterree herein
Plastic deformation occurs in the process.
4, it after unloading the reinstatement of SGOI wafer, due to the plastic deformation of SiN enterree, forms top layer overall situation single shaft and answers
Become SiGe layer.
But there are following disadvantages for this method：1) poor with traditional integrated circuit processing compatibility：In order to obtain difference
The SGOI of dependent variable, this method needs additionally to make the bending of corresponding different curvature radius, and made bending needs
It is compatible with existing annealing device.2) reliability is poor：The process, which need to use compression bar to apply mechanical external force, keeps SGOI wafer curved
Song can introduce defect in top layer Si Ge；If SGOI wafer bow is excessive, disk fragmentation will cause.3) due to worrying SGOI
Wafer fragmentation, so mechanical bent curvature cannot be excessive, which limits the big of the dependent variable introduced in top layer Si Ge
Small, achieved dependent variable is smaller.
Summary of the invention
It is a kind of based on silicon nitride stress film and ruler it is an object of the invention in view of the above shortcomings of the prior art, propose
The production method that the SiN of degree effect buries insulating top layers wafer scale uniaxial strain SiGe, to reduce the production work of strain SGOI wafer
Skill complexity and cost improve the dependent variable of uniaxial strain SGOI, enhance the electron mobility and hole migration of SGOI wafer
Rate meets the electrical and optical performance requirement of SGOI device and integrated circuit.
To achieve the above object, technical solution of the present invention includes as follows：
(1) SiGe SGOI wafer on insulating layer is cleaned, which includes that top layer SiGe layer, SiN bury insulation
Layer and Si substrate three-decker；
(2) He ion implanting is carried out to the SGOI wafer cleaned, i.e., buried the SiN of He ion implanting to SGOI wafer absolutely
At edge layer and Si substrate interface；
(3) using the pressure of the techniques deposit -1.2GPa or more such as PECVD on SGOI wafer top layer Si Ge after ion implantation
The tensile stress SiN film of stress SiN film or 1.2GPa or more；
(4) utilize semiconductor lithography and dry etch process, to SiN film carry out bar pattern, formed item it is wide and
Only length direction is obtained to eliminate the stress of width direction away from the bar shaped SiN membrane array for being 0.12 μm~0.14 μm
The silicon nitride compression item or tensile stress item of stress make top layer SiGe layer and SiN enterree occur whole to be uniaxially stretched shape
Become or uniaxial compression deformation, so cause SGOI wafer be changed into wafer scale uniaxial tensile strain SGOI or uniaxial compressive strain
SGOI；
(5) the SGOI wafer for forming bar shaped SiN membrane array to the surface top layer Si Ge is annealed, and makes answering for SiN film
Power further enhances, and makes SiN enterree that plastic deformation occur, and top layer Si Ge ply stress does not disappear after guaranteeing the removal of SiN film
It loses；
(6) the bar shaped SiN membrane array on SGOI crystal column surface is removed by wet etching, finally obtains wafer scale single shaft
Tensile strain SGOI or uniaxial compressive strain SGOI material.
The invention has the advantages that：
1, completely compatible with existing integrated circuit technology：The production of wafer scale uniaxial strain SOI of the present invention, can pass through
The existing conventional Si process such as pecvd process deposit, figure photoetching, etching realizes that simple process does not need additional customized technique
Required equipment.
2, high reliablity：The present invention is not needed pair by the way that high stress SiN stripe array is introduced wafer scale uniaxial strain
SGOI applies mechanical external force and avoids the defects of top layer Si Ge generation and disk fragmentation so that disk be prevented to bend,
Improve yield rate.
3, at low cost：The present invention can be introduced directly into the uniaxial strain of wafer scale due to use high stress SiN stripe array,
Therefore common SGOI wafer can be used to make uniaxial global strain SGOI material, rather than biaxial strain SGOI wafer, reduce work
Skill cost.
4, dependent variable is big：The present invention makes top layer SiGe layer and SiN bury insulation by the simple stress of bar shaped SiN stripe array
Layer occurs whole uniaxial tensile deformation or uniaxial compression deformation and strains to introduce, can be by adjusting SiN film deposition art
Increase dependent variable.
5, inhibit parasitic reaction：Traditional SiO2Enterree, can be very well using SiN enterree easily with Ge component reaction
Inhibition parasitic reaction generation.
Detailed description of the invention
Fig. 1 is the process flow chart of existing wafer scale uniaxial strain SGOI wafer.
Fig. 2 is wafer scale uniaxial strain SiGe process flow chart on SiN enterree of the invention.
Fig. 3 is the top view for the bar shaped SiN membrane array being deposited in top layer SiGe layer in the present invention.
Specific embodiment
Technical principle of the invention is as follows：
The present invention is according to ion implantation technology principle, by He ion implanting to the interface of SiN enterree and substrate Si layer
Place, the interface cohesion that will lead to SiN enterree and substrate Si layer becomes loose, so that SiN enterree and top layer thereon
Si layers are easy to happen corresponding strain after depositing high stress SiN film.Again according to the scale effect principle of the mechanics of materials, pass through
Semiconductor process technique production width and spacing are the bar shaped SiN membrane array of 120nm~140nm, so that strip width side
To stress release, and do not change along the stress intensity in bar length direction, so that bar shaped SiN membrane array be made to possess list
Axis compression or uniaxial tensile stress, to introduce uniaxial tensile strain or uniaxial compressive strain in top layer SiGe layer and SiN enterree.
In annealing process, the stress of bar shaped SiN membrane array can be further enhanced, and also resulted in SiN enterree and generated stretching
Or the plastic deformation of compression, and top layer Si Ge is still in elastic deformation.After removing bar shaped SiN membrane array, since SiN is buried absolutely
Edge layer stretches or the plastic deformation of compression effect, causes top layer Si Ge that uniaxial tensile strain or uniaxial compressive strain occurs, ultimately forms
Possess the wafer scale uniaxial strain SOI of strain top layer SiGe layer.
SiN enterree SGOI wafer includes 3 inches, 4 inches, 5 inches, 6 inches, 8 inches, 12 inches of different rule
Lattice, Ge layers of top layer Si with a thickness of 100~500nm.
Referring to Fig. 2, the present invention provides wafer scale list on the SiN enterree based on silicon nitride stress film and scale effect
Three embodiments of the production method of axial strain SiGe, that is, prepare 5 inches, 8 inches, 12 inches of SiN enterree single shaft answers
Become SGOI wafer material, the SiN enterree SGOI wafer of different size includes three-decker：Si substrate 3, SiN bury insulation
Layer 2 and top layer SiGe layer 1, as shown in Figure 2 a.Wherein：
5 inches of SiN enterree SGOI wafers, Si substrate with a thickness of 550 μm, SiN enterree with a thickness of
500nm, top layer SiGe layer with a thickness of 100nm；
8 inches of SiN enterree SGOI wafers, Si substrate with a thickness of 550 μm, SiN enterree with a thickness of
500nm, top layer SiGe layer with a thickness of 300nm；
12 inches of SiN enterree SGOI wafers, Si substrate with a thickness of 550 μm, SiN enterree with a thickness of
500nm, top layer SiGe layer with a thickness of 500nm.
Embodiment 1 prepares 5 inches of SiN enterree single shaft tensile strain SGOI wafer materials.
Step 1：SiN enterree SGOI wafer is cleaned, to remove surface contaminant.
(1.1) organic to remove substrate surface using acetone and isopropanol to SGOI wafer alternately ultrasonic cleaning
Object pollution；
(1.2) 1 is configured：1：3 ammonium hydroxide, hydrogen peroxide, deionized water mixed solution, and 120 DEG C are heated to, by SGOI crystalline substance
Circle, which is placed in this mixed solution, to be impregnated 12 minutes, is rinsed after taking-up with a large amount of deionized waters, inorganic to remove SGOI crystal column surface
Pollutant；
(1.3) SGOI wafer HF acid buffer is impregnated 2 minutes, removes the oxide layer on surface.
Step 2：Ion implanting.
It is 1E14cm to the SGOI wafer implantation dosage cleaned-2, the He ion of energy 50Kev, with loose Si substrate 3 with
Interface 4 between SiN enterree 2, as shown in Figure 2 b.
Step 3：Deposit SiN film.
(3.1) the SGOI wafer after injecting ions into takes out, and is placed in plasma enhanced CVD PECVD reaction
In room, first start vacuum pump, reaction chamber is evacuated to 2.7Torr, restarts heater for the temperature of reaction chamber and rise to 400 DEG C
And keep constant temperature；
(3.2) the high-purity Si H of 0.36slm is successively passed through into reaction chamber4, the high-purity N H of 2.0slm3, 2.0slm's is high-purity
N2；
(3.3) high frequency HF power is set as 0.32KW, and low frequency LF power is 0.76KW, and deposition thickness is on SGOI wafer
0.7 μm, stress is the SiN compressive stress film 5 of -1.2GPa, as shown in Figure 2 c；
(3.4) reaction chamber is vacuumized after the completion of depositing, then after reaction chamber temperature is cooled to room temperature, taking-up be deposited
The SGOI wafer of SiN compressive stress film.
Step 4：Using semiconductor lithography and lithographic technique, compression SiN film 5 is etched, forms bar shaped SiN membrane array
6, as shown in Figure 2 d.
(4.1) positive photoetching rubber is applied in compression SiN layer 5, photoresist is dried, using equal with strip width and interval
Photolithography plate for 0.14 μm is exposed, and the region of exposure is width and interval is 0.14 μm of strip array, uses developer solution
The positive photoetching rubber that exposure area is soluble in developer solution is got rid of, forms strip photoresist masking membrane array in SiN layer；
(4.2) reactive ion etching RIE technique is used, is 4Pa in reaction chamber pressure, reaction chamber temperature is 40 DEG C, substrate
Temperature is 5 DEG C, and 13.56MHz HFRF power is 400W, etching gas CHF4Flow is 30sccm, O2Gas flow is
Under conditions of 3sccm, the compression SiN film 5 being deposited on SGOI wafer top layer Si layer is performed etching, formation width is
0.14 μm of bar shaped SiN membrane array 6 obtains the silicon nitride of only length direction stress to eliminate the stress of width direction
Stress item, the obtained SGOI wafer top view with SiN membrane array 6 are as shown in Figure 3；
(4.3) photoresist in bar shaped SiN membrane array is removed.
Step 5：Annealing.
The SGOI wafer for forming bar shaped SiN membrane array 6 to 1 surface of top layer SiGe layer is annealed, as shown in Figure 2 e, i.e.,
It is 4 DEG C/min in heating rate, temperature is annealed 3.5 hours in inert gas He under conditions of being 310 DEG C, then with 4 DEG C/min
Rate be cooled to room temperature.In annealing process, the stress of bar shaped SiN membrane array 6 can be further enhanced, and SiN is caused to bury absolutely
Edge layer 2 generates the plastic deformation stretched.
Step 6：Remove bar shaped SiN film.
The SOI wafer that deposited bar shaped SiN membrane array 6 is put into the phosphoric acid solution that volume fraction is 85%, 150
The wet etching that 5 minutes are carried out at DEG C finally obtains the uniaxial tensile strain SOI wafer material with strain top layer Si layer 7, such as schemes
Shown in 2f.
Embodiment 2 prepares 8 inches of SiN enterree single shaft compressive strain SGOI wafer materials.
Step 1：SiN enterree SGOI wafer is cleaned, to remove surface contaminant.
The realization of this step is identical as the step 1 of embodiment 1.
Step 2：It is 1E15cm to the SGOI wafer implantation dosage cleaned-2, the He ion of energy 85Kev, so that Si is served as a contrast
Interface 4 between bottom 3 and SiN enterree 2 obtain it is loose, as shown in Figure 2 b.
Step 3：The top layer SiGe layer 1 for the SGOI wafer that ion implanting is completed surface deposition with a thickness of 0.7 μm,
Stress is the tensile stress SiN film 5 of 1.2GPa, as shown in Figure 2 c.
The realization process of this step is identical as the step 3 of embodiment 1, and technological parameter is as follows：
Reaction chamber temperature is 400 DEG C, and reaction chamber pressure is 3.1Torr, and high frequency HF power is 1.3KW, and low frequency LF power is
0.31KW, SiH4Flow is 0.31slm, NH3Flow is 1.9slm, and high pure nitrogen flow is 1.1slm.
Step 4：Using semiconductor lithography and lithographic technique, tensile stress SiN film 5 is etched, forms bar shaped SiN film battle array
Column 6, as shown in Figure 2 d.
(4a) applies positive photoetching rubber in tensile stress SiN layer 5, and photoresist is dried, using equal with strip width and interval
Photolithography plate for 0.13 μm is exposed, and the region of exposure is width and interval is 0.13 μm of strip array, uses developer solution
The positive photoetching rubber that exposure area is soluble in developer solution is got rid of, forms strip photoresist masking membrane array in SiN layer；
(4b) uses reactive ion etching RIE technique, to the tensile stress SiN film being deposited on SGOI wafer top layer Si layer
5 perform etching, and the bar shaped SiN membrane array 6 that formation width is 0.13 μm to eliminate the stress of width direction, is only had
The silicon nitride stress item of length direction stress, the obtained SGOI wafer top view with SiN membrane array 6 is as shown in figure 3, anti-
Answer ion etching RIE process conditions identical as step (4.1) in embodiment 1；
(4c) removes the photoresist in bar shaped SiN membrane array 6.
Step 5：The SGOI wafer for forming bar shaped SiN membrane array 6 to 1 surface of top layer SiGe layer is annealed, such as Fig. 2 e
It is shown, i.e., it is 4 DEG C/min in heating rate, temperature is annealed 3 hours in inert gas Ne under conditions of being 360 DEG C, then with 4
DEG C/rate of min is cooled to room temperature.In annealing process, the stress of bar shaped SiN membrane array 6 can be further enhanced, and be caused
SiN enterree 2 generates the plastic deformation of compression.
Step 6：The bar shaped SiN membrane array 6 on 1 surface of SGOI wafer top layer SiGe layer is removed, as shown in figure 2f.
The SOI wafer that deposited bar shaped SiN membrane array 6 is put into the phosphoric acid solution that volume fraction is 85%, 160
The wet etching that 9 minutes are carried out at DEG C finally obtains the uniaxial compressive strain SOI wafer material with strain top layer Si layer 7.
Embodiment 3 prepares 12 inches of SiN enterree single shaft tensile strain SGOI wafer materials.
Step A：SiN enterree SGOI wafer is cleaned, to remove surface contaminant.
The realization of this step is identical as the step 1 of embodiment 1.
Step B：Ion implanting is carried out to the SGOI wafer cleaned, so that Si substrate 3 and 2 interface 4 of SiN enterree are dredged
Pine, as shown in Figure 2 b.
The technique of ion implanting is：The ion of injection is He ion, implantation dosage 1E16cm-2, Implantation Energy 120Kev.
Step C：Deposit SiN film.
The top layer SiGe layer 1 for the SGOI wafer that ion implanting is completed surface deposition with a thickness of 0.9 μm, stress is-
The compression SiN film 5 of 1.3GPa, as shown in Figure 2 c；
The realization process of this step is identical as the step 3 of embodiment 1, and technological parameter is as follows：
Reaction chamber temperature is 400 DEG C, and reaction chamber pressure is 2.9Torr, and high frequency HF power is 0.40KW, and low frequency LF power is
0.65KW, SiH4Flow is 0.26slm, NH3Flow is 2.2slm, and high pure nitrogen flow is 2.4slm.
Step D：Using semiconductor lithography and lithographic technique, compression SiN film 5 is etched, forms bar shaped SiN membrane array
6, as shown in Figure 2 d.
(D1) positive photoetching rubber is applied in compression SiN layer 5, photoresist is dried, using equal with strip width and interval
Photolithography plate for 0.12 μm is exposed, and the region of exposure is width and interval is 0.12 μm of strip array, uses developer solution
The positive photoetching rubber that exposure area is soluble in developer solution is got rid of, forms strip photoresist masking membrane array in SiN layer；
(D2) reactive ion etching RIE technique is used, to the compression SiN film being deposited on SGOI wafer top layer Si layer
5 perform etching, and the bar shaped SiN membrane array 6 that formation width is 0.12 μm to eliminate the stress of width direction, is only had
The silicon nitride stress item of length direction stress obtains the SGOI wafer with SiN membrane array 6, top view as shown in figure 3,
Reactive ion etching RIE process conditions are identical as (4.1) the step of embodiment 1；
(D3) photoresist in bar shaped SiN membrane array 6 is removed.
Step E：Annealing.
The SGOI wafer for forming bar shaped SiN membrane array 6 to 1 surface of top layer SiGe layer is annealed, as shown in Figure 2 e, i.e.,
It is 4 DEG C/min in heating rate, temperature is annealed 2.5 hours in inert gas Ar under conditions of being 410 DEG C, then with 4 DEG C/min
Rate be cooled to room temperature.In annealing process, the stress of bar shaped SiN membrane array 6 can be further enhanced, and SiN is caused to bury absolutely
Edge layer 2 generates the plastic deformation stretched.
Step F：Remove bar shaped SiN membrane array.
The SOI wafer that deposited bar shaped SiN membrane array 6 is put into the phosphoric acid solution that volume fraction is 85%, 200
The wet etching that 8 minutes are carried out at DEG C finally obtains the uniaxial tensile strain SOI wafer material with strain top layer Si layer 7, such as schemes
Shown in 2f.
Claims (9)
1. the production side of wafer scale uniaxial strain SiGe on the SiN enterree based on silicon nitride stress film and scale effect
Method includes the following steps：
(1) SiGe SGOI wafer on insulating layer is cleaned, the SGOI wafer include top layer SiGe layer, SiN enterree and
Si substrate three-decker；
(2) He ion implanting is carried out to the SGOI wafer cleaned, i.e., by the SiN enterree of He ion implanting to SGOI wafer
At Si substrate interface；
(3) compression of pecvd process deposit -1.2GPa or more is used on SGOI wafer top layer Si Ge after ion implantation
The tensile stress SiN film of SiN film or 1.2GPa or more；
(4) semiconductor lithography and dry etch process are utilized, bar pattern is carried out to SiN film, it is wide equal with spacing to form item
Only length direction stress is obtained to eliminate the stress of width direction for 0.12 μm~0.14 μm of bar shaped SiN membrane array
Silicon nitride compression item or tensile stress item, make top layer SiGe layer and SiN enterree occur whole uniaxial tensile deformation or
Uniaxial compression deformation, and then SGOI wafer is caused to be changed into the uniaxial tensile strain SGOI or uniaxial compressive strain SGOI of wafer scale；
(5) to the surface top layer Si Ge formed bar shaped SiN membrane array SGOI wafer anneal, make the stress of SiN film into
The enhancing of one step, and make SiN enterree that plastic deformation occur, top layer Si Ge ply stress does not disappear after guaranteeing the removal of SiN film；
(6) the bar shaped SiN membrane array on SGOI crystal column surface is removed by wet etching, finally obtains wafer scale single shaft and answers
Become SGOI or uniaxial compressive strain SGOI material.
2. according to the method described in claim 1, the wherein SGOI wafer in step (1) comprising 3 inches, 4 inches, 5 English
Very little, 6 inches, 8 inches, 12 inches of different size, Ge layers of top layer Si with a thickness of 100~500nm.
3. its step are as follows according to the method described in claim 1, wherein cleaning in step (1) to SGOI wafer：
(1a) uses acetone and isopropanol to SGOI wafer alternately ultrasonic cleaning, dirty to remove substrate surface organic matter
Dye；
(1b) configuration 1：1：3 ammonium hydroxide, hydrogen peroxide, deionized water mixed solution, and be heated to 120 DEG C, SGOI wafer set
It impregnates 12 minutes, is rinsed after taking-up with a large amount of deionized waters, to remove SGOI crystal column surface inorganic pollution in this mixed solution
Object；
(1c) impregnates SGOI wafer HF acid buffer 2 minutes, removes the oxide layer on surface.
4. according to the method described in claim 1, the wherein ion implanting in step (2), using He ion, implantation dosage from
1E14cm-2~1E16cm-2Variation, Implantation Energy change according to the different of top layer Si Ge thickness degree from 50Kev~120Kev.
5. being adopted according to the method described in claim 1, wherein step (3) deposits the technique of compression SiN layer on top layer Si Ge
With plasma chemical vapor deposition pecvd process, parameter is as follows：
High frequency power HF is 0.32KW~0.40KW；
Low frequency power LF is from 0.66KW~0.76KW；
High-purity Si H4Flow 0.26slm~0.36slm, high-purity N H3Flow 2.0slm~2.2slm, high pure nitrogen flow 2.0slm
~2.4slm；
React chamber pressure 2.7Torr~2.9Torr；
400 DEG C of reaction chamber temperature；
0.7 μm~0.9 μm of deposition thickness.
6. being used according to the method described in claim 1, wherein step (3) deposits the technique of tensile stress SiN layer in top layer Si
Plasma chemical vapor deposition pecvd process, parameter are as follows：
High frequency power HF is 1.2KW~1.4KW；
Low frequency power LF is from 0.21KW~0.41KW；
High-purity Si H4Flow 0.21slm~0.41slm, high-purity N H3Flow 1.8slm~2.0slm, high pure nitrogen flow 0.9slm
~1.3slm；
React chamber pressure 3.0Torr~3.2Torr；
400 DEG C of reaction chamber temperature；
0.9 μm~1.3 μm of deposition thickness.
7. according to the method described in claim 1, it is characterized in that using photoetching and reactive ion etching RIE work in step (4)
SiN layer is etched array into strips by process, is carried out as follows：
(4a) applies positive photoetching rubber in SiN layer, and photoresist is dried, using be 0.12 μm with strip width and interval~
0.14 μm of photolithography plate is exposed, and the region of exposure is width and interval is 0.12 μm~0.14 μm of strip array, is used
Developer solution gets rid of the positive photoetching rubber that exposure area is soluble in developer solution, and strip photoresist masking membrane array is formed in SiN layer；
(4b) etches away the unglazed photoresist masking film being deposited on SGOI wafer top layer Si Ge using reactive ion etching RIE technique
Region, i.e. SiN under exposure area leave the SiN under strip photoresist masking film, obtain width and spacing be 0.12 μm~
0.14 μm of SiN strip array；
(4c) removes strip photoresist masking film, only leaves SiN strip array.
8. according to the method described in claim 1, wherein the annealing in step (5), process conditions are：Temperature：310 DEG C~
410 DEG C, the time：2.5~3.5 hours, environment：He, Ne, Ar or their mixture.
9. being using volume point according to the method described in claim 1, wherein wet etching in step (6) removes SiN film
The phosphoric acid solution that number is 85% carries out 5~20 minutes etchings at being 150 DEG C~200 DEG C in temperature.
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| CN101454894A (en) * | 2006-05-30 | 2009-06-10 | 飞思卡尔半导体公司 | Engineering strain in thick strained-soi substrates |
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| CN101454894A (en) * | 2006-05-30 | 2009-06-10 | 飞思卡尔半导体公司 | Engineering strain in thick strained-soi substrates |
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