CN106098613B - Production method based on wafer scale uniaxial strain SiGe on the decrystallized AlN enterree with scale effect - Google Patents

Production method based on wafer scale uniaxial strain SiGe on the decrystallized AlN enterree with scale effect Download PDF

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CN106098613B
CN106098613B CN201610446253.0A CN201610446253A CN106098613B CN 106098613 B CN106098613 B CN 106098613B CN 201610446253 A CN201610446253 A CN 201610446253A CN 106098613 B CN106098613 B CN 106098613B
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layer
sige
sin
wafer
aln
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CN106098613A (en
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过润秋
戴显英
冯兰胜
梁彬
盛喆
苗东铭
焦帅
祁林林
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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Abstract

The invention discloses a kind of production methods based on wafer scale uniaxial strain SiGe on the decrystallized AlN enterree with scale effect.Implementation step is: depositing SiO in SiGe wafer top layer SiGe layer on AlN enterree after cleaning2Layer；Ion implanting is carried out to top layer SiGe layer and forms decrystallized layer, and removes the SiO on decrystallized layer2Layer；It is deposited in top layer SiGe layer and SiN film is etched into uniaxial tensile stress SiN strip array or uniaxial compressive stress SiN strip array after tensile stress SiN film or compression SiN film, and it anneals to the wafer, decrystallized layer is recrystallized, makes AlN enterree that plastic deformation occur；SiN strip array is etched away, wafer scale uniaxial strain SiGe on AlN enterree is obtained.Dependent variable of the present invention is big, can be used for making wafer scale uniaxial strain sige material on AlN enterree.

Description

Based on wafer scale uniaxial strain on the decrystallized AlN enterree with scale effect The production method of SiGe
Technical field
The invention belongs to microelectronics technologies, are related to semi-conducting material manufacturing technology, and especially a kind of AlN is buried absolutely The production method of wafer scale uniaxial strain SiGe in edge layer can be used for making the integrated electricity of ultrahigh speed, high temperature, big power consumption, high power High-performance SGOI wafer needed for road, integrated optoelectronic circuit.
Background technique
The carrier mobility of traditional body Si material is difficult meet the needs of following high-performance semiconductor device and circuit.
Strain SiGe device and circuit have many advantages, such as working frequency height, small power consumption, with Si process compatible, at low cost, The industrial fields such as microwave device, mobile communication, high-frequency circuit have a wide range of applications.SiGe still extremely excellent photoelectricity material Material, has a wide range of applications in terms of detector, modulator, optical waveguide, optical transmitting set, solar cell, photoelectricity.
SGOI, i.e., germanium silicon on insulating layer are a kind of Si base semiconductors with " SiGe/ enterree/Si " three-decker Substrate material, the enterree of SGOI wafer are usually SiO2, thermal conductivity is only 1 the percent of silicon, hinders SGOI in height The application of warm, high-power aspect；Its dielectric constant is only 3.9, easily leads to signal transmission and loses, also counteracts SGOI highly dense Application in degree, high power integrated circuit.And it is SiO that AlN, which has thermal conductivity,2200 times, resistivity 320W/mK, breakdown The excellent properties such as field strength is high, chemical and thermal stability energy is good, thermal expansion coefficient and Si are close are a kind of excellent dielectrics and insulation Material.Replace SiO with AlN2SGOI have better insulating properties and thermal diffusivity, high temperature, big power consumption, height can be widely used in In power integrated circuit.
Strain gauge technique can the larger carrier mobility for promoting SiGe, the strain for combining strain gauge technique and SGOI advantage is exhausted Germanium silicon SSGOI provides one kind to research and develop novel ultrahigh speed, low-power consumption, anti-radiation, highly integrated device and chip on edge body New solution, photoelectricity it is integrated, in terms of have important application prospect.
Traditional strain SGOI is the direct growth strain SiGe in SOI wafer, or Ge component is first grown in SOI wafer The SiGe layer of gradual change makees empty substrate, then the strained sige layer needed for epitaxial growth in the SiGe layer, major defect are dislocations Density is high, can only be biaxial strain, mobility promotes not high, the empty substrate of SiGe and increases hot expense and cost of manufacture, SiGe void Substrate has seriously affected the heat dissipation of device and circuit, strained sige layer critical thickness is limited by Ge component, the hole under High-Field is moved The promotion of shifting rate can degenerate.
The a kind of of Xian Electronics Science and Technology University's acquisition in 2011 uses mechanical bend and in the bent state annealing production AlN The new method patent (CN201110361521) of wafer scale uniaxial strain sige material, is buried absolutely to make AlN on enterree Wafer scale uniaxial strain sige material in edge layer, main technique is as shown in Figure 1, steps are as follows:
SiGe wafer top layer Si Ge level is placed on upward or downward on arc-shaped bend platform on 1.AlN enterree；
2. two stainless steel columns of cylinder lie in a horizontal plane in SiGe wafer both ends on AlN enterree respectively, buried away from AlN SiGe crystal round fringes 1cm on insulating layer；
3. the nut of slow turn connection compression bar, make on AlN enterree that arcuately table top is gradually curved SiGe wafer, directly SiGe wafer is bonded with arc-shaped table board completely on to AlN enterree；
4. the arc-shaped bend platform placement for being loaded with SiGe wafer on AlN enterree is annealed in the lehr, annealing temperature Degree can be selected arbitrarily within the scope of 300 DEG C to 1250 DEG C.
5. slow cooling takes out the arc-shaped bend platform for being loaded with SiGe wafer on AlN enterree to room temperature after annealing；
6. turn connects the nut of compression bar, compression bar is slowly promoted, until SiGe wafer is extensive on curved AlN enterree Restore shape.
There are following disadvantages for this method: 1) poor with traditional integrated circuit processing compatibility: differently strained in order to obtain SiGe wafer on the AlN enterree of amount, needs additionally to make the bending of corresponding different curvature radius, and made Bending needs to be compatible with existing annealing device.2) reliability is poor: the process, which need to use compression bar to apply mechanical external force, makes AlN SiGe wafer bow on enterree can introduce defect in top layer germanium silicon；If SiGe wafer bow is spent on AlN enterree Greatly, it will cause wafer fragmentation.3) due to worrying SiGe wafer fragmentation on AlN enterree, so mechanical bent curvature is not Can be excessive, which limits the size of the dependent variable introduced in top layer germanium silicon, achieved dependent variable is smaller.
Summary of the invention
It is a kind of based on decrystallized and scale effect it is an object of the invention in view of the above shortcomings of the prior art, propose The production method of wafer scale uniaxial strain SiGe on AlN enterree, to reduce wafer scale uniaxial strain on AlN enterree The cost of manufacture of SiGe increases dependent variable, improves high-power, high power consumption, the electric property of highly integrated circuit and optical property.
The technical scheme of the present invention is realized as follows:
One, technical principle:
There is bi-axial tensile strain or twin shaft compression by the deposit of plasma enhanced CVD pecvd process SiN film.When SiN film is etched to the strip that width is submicron order, due to the influence of " scale effect ", SiN item is wide The stress in degree direction can discharge, and SiN length direction is that macro-scale stress is retained, and can obtain that there is uniaxial to be answered The SiN strip array of power or uniaxial compressive stress applies uniaxial to the decrystallized layer in top layer SiGe layer along length direction Stress or uniaxial compressive stress.It anneals at 530 DEG C~550 DEG C, decrystallized layer can be made to recrystallize, it is decrystallized due to top layer SiGe layer The simple stress that layer is applied by SiN strip array always in annealing process, thus in annealing process as caused by stress Uniaxial strain is carried over into top layer SiGe layer, finally obtains the top layer SiGe layer of wafer scale uniaxial strain after annealing, meanwhile, Annealing makes AlN enterree that plastic deformation occur, and the AlN enterree of the plastic deformation, which has top layer SiGe layer, pulls and supports work With, with ensure remove high stress SiN film after uniaxial strain top layer SiGe layer in stress do not disappear, finally obtained AlN Wafer scale uniaxial strain sige material on enterree.
Two, realize step
According to above-mentioned principle, steps are as follows for realization of the invention:
1) it chooses SiGe wafer on AlN enterree to be cleaned, SiGe wafer includes top layer on the AlN enterree SiGe layer, AlN enterree and Si substrate；
2) in top layer SiGe layer by plasma enhanced CVD pecvd process deposition thickness be 20nm~ The SiO of 22nm2Layer, to eliminate the channelling effect of subsequent ion injection technology；
3) ion implanting is carried out to top layer SiGe layer, to form decrystallized layer inside top layer SiGe layer；
4) SiO on decrystallized layer is removed2Layer；
5) using plasma enhances chemical vapor deposition pecvd process deposit -1GPa or more in top layer SiGe layer The tensile stress SiN film of compression SiN film or 1GPa or more；
6) tensile stress SiN film or compression SiN film are etched into photoetching and reactive ion etching RIE process Width and spacing are that 0.16 μm~0.18 μm of SiN strip array obtains single shaft to eliminate the stress of SiN width direction Tensile stress SiN strip array or uniaxial compressive stress SiN strip array；
7) it anneals to SiGe wafer on the AlN enterree with SiN strip array, further enhances SiN strip Array stress, and recrystallize decrystallized layer, while making AlN enterree that plastic deformation occur, guarantee the removal of SiN strip array The stress of top layer SiGe layer does not disappear afterwards；
8) SiN strip array is got rid of with wet etching, obtains wafer scale uniaxial strain SiGe material on AlN enterree Material.
The present invention has following excellent compared with wafer scale uniaxial strain SiGe manufacturing technology on existing AlN enterree Point:
1. the present invention is compatible with existing semiconductor fabrication process, at low cost without customizing other instruments.
2. the present invention introduces wafer scale uniaxial strain using tensile stress SiN strip array or compression SiN strip array, keep away Exempt to move back SiGe wafer bow on AlN enterree in wafer scale uniaxial strain SiGe method on mechanical cause AlN enterree The lower problem of SiGe wafer flatness on AlN enterree after fire.
3. the present invention introduces wafer scale uniaxial strain using tensile stress SiN strip array or compression SiN strip array, and Plastic deformation occurs after the annealing of AlN enterree to top layer SiGe layer with effect is pulled and supported, increases top layer Si Ge ply strain amount, It is obviously improved so that carrier mobility has.
Detailed description of the invention
Fig. 1 is the process flow chart of wafer scale uniaxial strain SiGe on existing AlN enterree；
Fig. 2 is the process flow chart of wafer scale uniaxial strain SiGe on AlN enterree of the present invention；
Fig. 3 is the top view for the SiN strip array being deposited in top layer SiGe layer in the present invention.
Specific embodiment
SiGe wafer on AlN enterree, size include 3 inches, 4 inches, 5 inches, 6 inches, 8 inches, 12 inches With 16 inches of different size, and Ge layers of top layer Si with a thickness of 0.3 μm~0.32 μm.
Referring to Fig. 2, the present invention is provided based on wafer scale uniaxial strain on the decrystallized AlN enterree with scale effect Three embodiments of the production method of SiGe make wafer scale single shaft tensile strain sige material on 6 inches of AlN enterrees； Make wafer scale single shaft tensile strain sige material on 8 inches of AlN enterrees；Make wafer scale on 12 inches of AlN enterrees Uniaxial compressive strain sige material.SiGe wafer all has three-decker, i.e. top layer SiGe layer 1, AlN on above-mentioned AlN enterree Enterree 2, Si substrate 3, as shown in Fig. 2 (a).Wherein:
SiGe wafer on 6 inches of AlN enterrees, top layer SiGe layer 1 with a thickness of 0.3 μm, the thickness of AlN enterree 2 Degree be 0.5 μm, Si substrate 3 with a thickness of 525 μm.
SiGe wafer on 8 inches of AlN enterrees, top layer SiGe layer 1 with a thickness of 0.31 μm, the thickness of AlN enterree 2 Degree be 0.5 μm, Si substrate 3 with a thickness of 675 μm.
SiGe wafer on 12 inches of AlN enterrees, top layer SiGe layer 1 with a thickness of 0.32 μm, AlN enterree 2 With a thickness of 0.5 μm, Si substrate 3 with a thickness of 725 μm.
Embodiment 1 makes wafer scale single shaft tensile strain sige material on 6 inches of AlN enterrees.
Step 1: selecting SiGe wafer on 6 inches of AlN enterrees, and it is cleaned.
(1a) using acetone and isopropanol to SiGe wafer alternately ultrasonic cleaning on selected AlN enterree, with Remove substrate surface organic pollution；
(1b) by ammonium hydroxide, hydrogen peroxide, deionized water according to the proportional arrangement of 1:1:3 at mixed solution, and be heated to 120 DEG C, SiGe wafer on AlN enterree is placed in this mixed solution and impregnates 12min, is rinsed after taking-up with a large amount of deionized waters, To remove SiGe crystal column surface inorganic pollution on AlN enterree；
The HF buffer of SiGe wafer on AlN enterree is impregnated 2min by (1c), removes the oxide layer on surface.
Step 2: deposit SiO2Layer 4, as shown in Fig. 2 (b).
(2a) takes out SiGe wafer on the AlN enterree after cleaning, is placed in plasma enhanced CVD In PECVD reaction chamber, starts vacuum pump, reaction chamber is evacuated to 600mTorr, restarts temperature of the heater by reaction chamber It rises to 300 DEG C and keeps constant temperature；
(2b) is successively passed through the SiH of 45sccm into reaction chamber4, the N of 164sccm2The N of O, 800sccm2；
(2c) sets low frequency LF power as 60W, the deposition thickness in SiGe wafer top layer SiGe layer 1 on AlN enterree For the SiO of 20nm2Layer 4；
Reaction chamber is vacuumized after the completion of (2d) deposit, then after reaction chamber temperature is cooled to room temperature, taking-up be deposited SiO2SiGe wafer on the AlN enterree of layer 4.
Step 3: decrystallized layer 5 is formed, as shown in Fig. 2 (c).
SiO will be deposited2SiGe wafer is put into ion implantation apparatus on AlN enterree after layer 4, selects C ion, setting note Entering dosage is 3E16cm-2, Implantation Energy 95keV, to the progress ion implanting of top layer SiGe layer 1, inside top layer SiGe layer 1 Form decrystallized layer 5；
Step 4: removal SiO2Layer 4, as shown in Fig. 2 (d).
At room temperature, SiO will be had2SiGe wafer impregnates 80s in BHF solution on the AlN enterree of layer 4, removes SiO on decrystallized layer 52Layer 4.
Step 5: compression SiN film 6 is deposited on decrystallized layer, as shown in Fig. 2 (e).
(5a) will remove SiO2SiGe wafer takes out on AlN enterree after layer 4, is placed in plasma enhanced chemical gas Mutually in deposit PECVD reaction chamber, first start vacuum pump, restarts heater and the temperature of reaction chamber is risen to 400 DEG C and keeps permanent Temperature；
(5b) is successively passed through the high-purity Si H of 0.37slm into reaction chamber4, the high-purity N H of 2.3slm3, 2.2slm's is high-purity N2, react chamber pressure 3.1Torr；
(5c) sets high frequency HF power as 0.27kW, and low frequency LF power is 0.73kW, and SiGe wafer is non-on AlN enterree It is -1.2GPa that stress intensity is deposited on crystallization layer 5, with a thickness of 0.3 μm of compression SiN film 6；
Reaction chamber is vacuumized after the completion of (5d) deposit, then after reaction chamber temperature is cooled to room temperature, taking-up deposited pressure SiGe wafer on the AlN enterree of stress SiN film 6.
Step 6: compression SiN film 6 being etched into uniaxial compressive stress SiN strip array 7, as shown in Fig. 2 (f).
(6a) applies positive photoetching rubber on SiN stress film 6 using semiconductor lithography process, and photoresist is dried, using having Strip width and interval are that 0.16 μm of photolithography plate is exposed, and the region of exposure is width and interval is 0.16 μm of item Shape array, then the positive photoetching rubber that exposure area is soluble in developer solution is got rid of with developer solution, it is formed on compression SiN film 6 Strip photoresist masking membrane array；
(6b) is etched away using reactive ion etching RIE technique and is deposited on SiGe wafer top layer Si Ge on AlN enterree Unglazed photoresist on layer 1 shelters diaphragm area, i.e., the compression SiN film 6 under exposure area leaves under strip photoresist masking film Compression SiN film 6, obtain width and spacing be 0.16 μm of SiN strip array 7, to eliminate SiN width direction Stress retains the stress of SiN length direction, uniaxial compressive stress SiN strip array 7 is obtained, as shown in Fig. 2 (f)；
(6c) removes strip photoresist masking film, only leaves SiN strip array 7, should bury with the AlN of SiN strip array The top view of SiGe wafer is as shown in Figure 3 on insulating layer.
Step 7: annealing to SiGe wafer on the AlN enterree with SiN strip array 7, as shown in Fig. 2 (g).
(7a) in the lehr, first temperature is promoted to 530 DEG C by room temperature according to the heating rate of 4 DEG C/min after, by band There is on the AlN enterree of SiN strip array 7 SiGe wafer anneal at inert gas He 6h；
Annealing furnace temperature is down to room temperature according to the rate of temperature fall of 4 DEG C/min by (7b), SiGe on AlN enterree after annealing Wafer top layer SiGe layer 1 becomes uniaxial strain top layer SiGe layer 8；
(7c) SiN strip array stress in annealing process further enhances, and recrystallizes decrystallized layer 5, while making AlN Plastic deformation occurs for enterree 2, becomes plastic deformation AlN enterree 9, to guarantee after the removal of SiN strip array thereon The stress of strain top layer SiGe layer 8 does not disappear.
Step 8: the SiN strip array on removal AlN enterree on SiGe wafer, as shown in Fig. 2 (h).
155 DEG C of configuration, the hot phosphoric acid solution that volume fraction is 85% will have the AlN enterree of SiN strip array 7 Upper SiGe wafer impregnates 3min in hot phosphoric acid solution, gets rid of SiN strip array 7, obtains brilliant on 6 inches of AlN enterrees Circle grade single shaft tensile strain sige material.
Embodiment 2 makes wafer scale single shaft tensile strain sige material on 8 inches of AlN enterrees.
Step 1: SiGe wafer wafer on 8 inches of AlN enterrees is selected, and it is cleaned.
The realization of this step is identical as the step 1 of embodiment 1.
Step 2: SiGe wafer on the AlN enterree after cleaning is taken out, in its top layer SiGe layer 1 by it is equal from Daughter enhances chemical vapor deposition pecvd process and deposits SiO2Layer 4, as shown in Fig. 2 (b).
Depositing step is identical as the step 2 of embodiment 1,
The technological parameter of use: SiH4Flow is 45sccm, N2O flow is 164sccm, N2Flow is 800sccm, air pressure For 600mTorr, power 60W, deposition temperature is 300 DEG C, deposition thickness 21nm.
Step 3: being 3.5E16cm to implantation dosage in top layer SiGe layer 1 by ion implantation apparatus-2, energy 96keV, Si ion, to form decrystallized layer 5 inside top layer SiGe layer 1, as shown in Fig. 2 (c).
Step 4: SiO will be had2Layer 4 AlN enterree on SiGe wafer impregnate 80s in BHF solution, go unless SiO on crystallization layer 52Layer 4, as shown in Fig. 2 (d).
Step 5: using plasma enhances chemical vapor deposition pecvd process, and it is big that stress is deposited on decrystallized layer 5 Small is -1.3GPa, with a thickness of 0.35 μm of compression SiN film 6, as shown in Fig. 2 (e).
Depositing step is identical as the step 5 of embodiment 1；
Deposition process parameters: high frequency HF power is 0.28kW, and low frequency LF power is 0.72kW, high-purity Si H4Flow is 0.38slm, high-purity N H3Flow is 2.4slm, and high pure nitrogen flow is 2.3slm, and reaction chamber pressure is 3.2Torr, reacts room temperature Degree is 400 DEG C.
Step 6: utilizing semiconductor lithography and lithographic technique, and compression SiN film 6 is etched array into strips, to eliminate The stress of SiN width direction retains the stress of SiN length direction, obtains uniaxial compressive stress SiN strip array 7.
(6.1) positive photoetching rubber is applied on compression SiN film 6, photoresist is dried, using with strip width and interval It is that 0.17 μm of photolithography plate is exposed, the region of exposure is width and interval is 0.17 μm of strip array, with development Liquid gets rid of the positive photoetching rubber that exposure area is soluble in developer solution, and strip photoresist masking film is formed on compression SiN film 6 Array；
(6.2) it is etched away with reactive ion etching RIE technique and is deposited on SiGe wafer top layer SiGe layer on AlN enterree The compression SiN film 6 of unglazed photoresist masking film protection on 1, leaves the compression SiN film under strip photoresist masking film 6, it obtains width and spacing is 0.17 μm of SiN strip array 7, as shown in Fig. 2 (f)；
(6.3) strip photoresist masking film is removed, SiN strip array 7 is only left, should be buried with the AlN of SiN strip array SiGe wafer top view is as shown in Figure 3 on insulating layer.
Step 7: in the lehr, will after temperature is first promoted to 540 DEG C by room temperature according to the heating rate of 4 DEG C/min SiGe wafer is annealed 6.1h at inert gas Ne on AlN enterree with SiN strip array 7, to further enhance SiN Strip array stress, and recrystallize decrystallized layer, while making AlN enterree 2 that plastic deformation occur, become plastic deformation AlN enterree 9, to guarantee that the stress of top layer SiGe layer after SiN strip array removes does not disappear；According still further to the drop of 4 DEG C/min Annealing furnace temperature is down to room temperature by warm rate.Top layer SiGe layer 1 becomes uniaxial strain top layer SiGe layer 8 after annealing, such as Fig. 2 (g) It is shown.
Step 8: configuration temperature is 158 DEG C, and the hot phosphoric acid solution that volume fraction is 86% will have SiN strip array 7 AlN enterree on SiGe wafer 4min is impregnated in hot phosphoric acid solution, get rid of SiN strip array 7, obtain 8 inches of AlN Wafer scale single shaft tensile strain sige material on enterree, as shown in Fig. 2 (h).
Embodiment 3 makes wafer scale single shaft compressive strain sige material on 12 inches of AlN enterrees.
Step A: SiGe wafer on 12 inches of AlN enterrees is selected, and it is cleaned.
The realization of this step is identical as the step 1 of embodiment 1.
Step B: deposit SiO2Layer 4, as shown in Fig. 2 (b).
SiGe wafer on AlN enterree after cleaning is taken out, passes through plasma enhancing in its top layer SiGe layer 1 Chemical vapor deposition pecvd process deposition thickness is the SiO of 22nm2Layer 4, as shown in Fig. 2 (b).
Setting deposits following parameter, and is deposited according to the step identical as 1 step 2 of embodiment:
SiH4Flow is 45sccm, N2O flow is 164sccm, N2Flow is 800sccm, air pressure 600mTorr, power For 60W, deposition temperature is 300 DEG C.
Step C: decrystallized layer 5 is formed, as shown in Fig. 2 (c).
Form SiO2After layer 4, carrying out dosage to top layer SiGe layer 1 by ion implantation apparatus is 4E16cm-2, energy is The Ge ion implanting of 97keV, to form decrystallized layer 5 inside top layer SiGe layer 1.
Step D: removal SiO2Layer 4, as shown in Fig. 2 (d).
SiO will be had2SiGe wafer impregnates 90s in BHF solution on the AlN enterree of layer 4, removes decrystallized layer 5 On SiO2Layer 4, in order to avoid hinder its stress transfer to decrystallized layer 5 after depositing SiN stress film 6, as shown in Fig. 2 (d).
Step E: tensile stress SiN film 6 is deposited on decrystallized layer, as shown in Fig. 2 (e).
Using plasma enhances chemical vapor deposition pecvd process, and stress intensity is deposited on decrystallized layer 5 and is 1.2GPa, with a thickness of 0.4 μm of tensile stress SiN film 6, as shown in Fig. 2 (e).
Setting deposits following parameter, and is deposited according to the step identical as 1 step 5 of embodiment:
High frequency HF power is 1.4kW, and low frequency LF power is 0.5kW, high-purity Si H4Flow is 0.2slm, high-purity N H3Flow is 1.8slm, high pure nitrogen flow are 0.9slm, and reaction chamber pressure is 3.2Torr, and reaction chamber temperature is 400 DEG C；
Step F: tensile stress SiN film 6 is etched into SiN strip array 7, as shown in Fig. 2 (f).
(F1) positive photoetching rubber is applied on tensile stress SiN film 6 using semiconductor lithography process, photoresist is dried, utilized It is exposed with the photolithography plate that strip width and interval are 0.18 μm, the region of exposure is width and interval is 0.18 μm Strip array, get rid of the positive photoetching rubber that exposure area is soluble in developer solution with developer solution, the shape on tensile stress SiN film 6 Photoresist masking membrane array into strips；
(F2) it is etched away using reactive ion etching RIE technique and is deposited on SiGe wafer top layer Si Ge on AlN enterree The tensile stress SiN film 6 of unglazed photoresist masking film protection on layer, the tensile stress SiN left under strip photoresist masking film are thin Film 6, obtains width and spacing is 0.18 μm of uniaxial tensile stress SiN strip array 7, to eliminate answering for SiN width direction Power retains the stress of SiN length direction, as shown in Fig. 2 (f)；
(F3) strip photoresist masking film is removed, SiN strip array 7 is only left, should be buried with the AlN of SiN strip array The top view of SiGe wafer is as shown in Figure 3 on insulating layer.
Step G: it anneals to SiGe wafer on the AlN enterree with SiN strip array 7.
G1 it) will anneal after furnace temperature is promoted to 550 DEG C by room temperature according to the heating rate of 4 DEG C/min, SiN strip will be had SiGe wafer is annealed 6.2h at inert gas Ar on the AlN enterree of array 7, further enhances SiN strip array stress, And recrystallize decrystallized layer, while making AlN enterree 2 that plastic deformation occur, become plastic deformation AlN enterree 9, protects The stress of top layer SiGe layer does not disappear after card SiN strip array removal；
G2 annealing furnace temperature) is down to room temperature according to the rate of temperature fall of 4 DEG C/min, top layer SiGe layer becomes uniaxial after annealing Top layer SiGe layer 8 is strained, as shown in Fig. 2 (g).
Step H: the SiN strip array on removal AlN enterree on SiGe wafer.
160 DEG C of configuration, the hot phosphoric acid solution that volume fraction is 87% will be on the AlN enterree with SiN strip array SiGe wafer impregnates 5min in hot phosphoric acid solution, gets rid of SiN strip array 7, obtains wafer on 12 inches of AlN enterrees The uniaxial compressive strain sige material of grade, as shown in Fig. 2 (h).

Claims (9)

1. based on the production method of wafer scale uniaxial strain SiGe on the decrystallized AlN enterree with scale effect, including such as Lower step:
1) it chooses SiGe wafer on AlN enterree to be cleaned, SiGe wafer includes top layer Si Ge on the AlN enterree Layer, AlN enterree and Si substrate；
It 2) is 20nm~22nm by plasma enhanced CVD pecvd process deposition thickness in top layer SiGe layer SiO2Layer, to eliminate the channelling effect of subsequent ion injection technology；
3) ion implanting is carried out to top layer SiGe layer, to form decrystallized layer inside top layer SiGe layer；
4) SiO on decrystallized layer is removed2Layer；
5) pressure of using plasma enhancing chemical vapor deposition pecvd process deposit -1GPa or more is answered in top layer SiGe layer The tensile stress SiN film of power SiN film or 1GPa or more；
6) tensile stress SiN film or compression SiN film are etched into width with photoetching and reactive ion etching RIE process It is 0.16 μm~0.18 μm of SiN strip array with spacing, to eliminate the stress of SiN width direction, obtains uniaxial and answer Power SiN strip array or uniaxial compressive stress SiN strip array；
7) it anneals to SiGe wafer on the AlN enterree with SiN strip array, further enhances SiN strip array Stress, and recrystallize decrystallized layer, while making AlN enterree that plastic deformation occur, it is pushed up after guaranteeing the removal of SiN strip array The stress of layer SiGe layer does not disappear；
8) SiN strip array is got rid of with wet etching, obtains wafer scale uniaxial strain sige material on AlN enterree.
2. according to the method described in claim 1, it is characterized in that SiGe wafer, size include 3 English on AlN enterree Very little, 4 inches, 5 inches, 6 inches, 8 inches, the different sizes of 12 inches and 16 inches；Ge layers of top layer Si with a thickness of 0.3 μm~ 0.32μm。
3. according to the method described in claim 1, it is characterized in that the work of ion implanting is carried out in step 3) to top layer SiGe layer Skill condition is:
Inject ion: C or Si or Ge or their any combination；
Implantation dosage: 3E16cm-2~4E16cm-2；
Implantation Energy: 95keV~97keV.
4. the method according to claim 1, wherein removing the SiO on decrystallized layer in step 4)2Layer, be by With SiO2SiGe wafer impregnates 80s~90s in BHF solution on the AlN enterree of layer, to remove on decrystallized layer SiO2Layer.
5. the method according to claim 1, wherein 1GPa or more are deposited in step 5) in top layer SiGe layer The CVD technique of stress SiN film, using plasma enhance chemical vapor deposition pecvd process, wherein deposit tensile stress SiN Thin film parameter is as follows:
400 DEG C of reaction chamber temperature；
High frequency HF power is 1.0kW~1.4kW；
Low frequency LF power is 0.2kW~0.5kW；
High-purity Si H4Flow 0.2slm~0.5slm, high-purity N H3Flow 1.8slm~2.1slm, high pure nitrogen flow 0.9slm~ 1.2slm；
Reaction chamber pressure is 2.7Torr~3.2Torr；
Deposition thickness is 0.3 μm~0.4 μm.
6. the method according to claim 1, wherein in step 5) in top layer SiGe layer deposit -1GPa or more The CVD technique of compression SiN film, using plasma enhance chemical vapor deposition pecvd process, and deposit compression SiN is thin Film parameters are as follows:
400 DEG C of reaction chamber temperature；
High frequency HF power is 0.27kW~0.29kW；
Low frequency LF power is 0.71kW~0.73kW；
High-purity Si H4Flow 0.37slm~0.39slm, high-purity N H3Flow 2.3slm~2.5slm, high pure nitrogen flow 2.2slm ~2.4slm；
Reaction chamber pressure is 3.1Torr~3.3Torr；
Deposition thickness is 0.3 μm~0.4 μm.
7. according to the method described in claim 1, it is characterized in that using photoetching and reactive ion etching RIE technique in step 6) SiN film is etched array into strips by method, is carried out as follows:
(7a) applies positive photoetching rubber on SiN film, and photoresist is dried, using be 0.16 μm with strip width and interval~ 0.18 μm of photolithography plate is exposed, and the region of exposure is width and interval is 0.16 μm~0.18 μm of strip array, is used Developer solution gets rid of the positive photoetching rubber that exposure area is soluble in developer solution, and strip photoresist masking film battle array is formed on SiN film Column；
(7b) is etched away using reactive ion etching RIE technique and is deposited on AlN enterree in SiGe wafer top layer SiGe layer Unglazed photoresist masking film protection SiN film, leave the SiN film under strip photoresist masking film, obtain width and spacing It is 0.16 μm~0.18 μm of simple stress SiN strip array；
(7c) removes strip photoresist masking film, only leaves SiN strip array.
8. the method according to claim 1, wherein burying insulation to the AlN with SiN strip array in step 7) SiGe wafer is annealed on layer, and process conditions are as follows:
Temperature: 530 DEG C~550 DEG C；
Time: 6h~6.2h；
Environment: He, Ne, Ar or their mixture.
9. the method according to claim 1, wherein getting rid of SiN strip battle array using wet etching in step 8) Column, are 150 DEG C~200 DEG C, and the hot phosphoric acid solution that volume fraction is 85%~88% buries the AlN with SiN strip array absolutely SiGe wafer impregnates 3min~5min in hot phosphoric acid solution in edge layer, gets rid of SiN strip array, obtains AlN enterree Upper wafer scale uniaxial strain sige material.
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CN102569163A (en) * 2011-11-16 2012-07-11 西安电子科技大学 Manufacturing method of wafer-level uniaxial strain SOI (Silicon On Insulator) wafer based on AIN (Advanced Intelligent Network) buried insulating layer
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