CN106098612B - Manufacturing method of wafer-level uniaxial strain Ge on SiN buried insulating layer based on silicon nitride stress film and scale effect - Google Patents
Manufacturing method of wafer-level uniaxial strain Ge on SiN buried insulating layer based on silicon nitride stress film and scale effect Download PDFInfo
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- H01—ELECTRIC ELEMENTS
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
The invention discloses a method for manufacturing wafer-level uniaxial strain Ge on an SiN buried insulating layer based on a silicon nitride stress film and a scale effect, which comprises the steps of cleaning a GeOI wafer, implanting He ions, depositing a compressive stress SiN film of more than-1.1 GPa or a tensile stress SiN film of more than 1.1GPa on a top Ge layer of the ion-implanted GeOI wafer, etching the SiN film to form a strip array, annealing the GeOI wafer with the SiN film array, and removing the SiN film array on the surface of the GeOI wafer by corrosion to obtain a wafer-level uniaxial strain GeOI material.
Description
Technical Field
The invention belongs to the technical field of microelectronics, relates to a manufacturing process technology of a semiconductor substrate material, in particular to a manufacturing method of wafer-level uniaxial strain Ge materials on an SiN buried insulating layer, and can be used for manufacturing GeOI wafers required by ultra-high-speed, low-power-consumption, anti-radiation and high-power integration semiconductor devices and chips.
Background
It is known in the art that the electron and hole mobility of semiconductor Ge is 2.8 and 4.2 times that of Si, respectively, and the hole mobility is the highest among all semiconductors, strain Ge technology introducing strain technology into Ge devices and integrated circuits has a significant improvement in carrier mobility, for example, the hole mobility of buried strain Ge can be improved by 6-8 times.
GeOI, which has been developed to address substrate leakage current and is currently used in fabrication of semiconductor devices and integrated circuits, GeOI wafer is typically a "Ge/insulator/Si" tri-layer structure2The thermal conductivity of the GeOI is only percent of that of silicon, which hinders the application of the GeOI in high temperature and high power, the dielectric constant of the GeOI is only 3.9, which easily causes signal transmission loss, and the application of the GeOI in high density and high power integrated circuits is also hindered2The GeOI has better insulation and heat dissipation, and has already been widely applied to high-temperature, high-power-consumption and high-power integrated circuits.
The germanium GeOI on the strain insulating layer combined with the advantages of the strain Ge and the GeOI provides new solutions for developing novel silicon-based devices and chips with ultrahigh speed, low power consumption, radiation resistance and high integration level, and has important application prospects in the aspects of photoelectric integration, system-level chips and the like.
In the traditional strain GeOI, strain Ge is directly epitaxially grown on a silicon SOI wafer on an insulating layer, or a SiGe layer with gradually changed Ge components is epitaxially grown on the SOI wafer to serve as a virtual substrate, and then a required strain Ge layer is epitaxially grown on the SiGe layer. The main defects of the traditional strain GeOI are high dislocation density, biaxial compressive strain, low mobility improvement, increased thermal overhead and manufacturing cost of a SiGe virtual substrate, serious influence on heat dissipation of a device and a circuit caused by the SiGe virtual substrate, limitation of Ge component on critical thickness of a strain Ge layer, degradation caused by improvement of hole mobility under a high field and the like.
Compared with biaxial strain GeOI, the improvement of the carrier mobility by the uniaxial strain is not degraded along with the increase of an electric field, and under the same strain amount, the improvement of the carrier mobility by the uniaxial strain is higher than that by the biaxial strain.
2011 new method patents (CN201110361530.5) of , obtained by the university of sienna electronics and technology in west ampere, for manufacturing a SiN buried insulating layer wafer-level uniaxial strain GeOI material by mechanical bending and annealing in a bent state, are used for manufacturing a SiN buried insulating layer wafer-level global uniaxial strain GeOI material, and the main processes are as shown in fig. 1 and include the following steps:
1. the Ge layer on the top layer of the GeOI wafer is placed upwards on an arc-shaped bending table with the bending direction parallel to the <110> or <100> direction.
2. Two cylindrical horizontal pressing rods on the bending table are respectively placed at two ends of the GeOI wafer, and the GeOI wafer is completely attached to the arc-shaped table top by the cylindrical horizontal pressing rods.
3. And annealing the SiN buried insulating layer in an annealing furnace at the temperature of 200-1250 ℃ for 1.5-10 hours to enable the SiN buried insulating layer to be subjected to plastic deformation in the process.
4. After the GeOI wafer is unloaded and recovered, the top layer global uniaxial strain Ge layer is formed due to the plastic deformation of the SiN buried insulating layer.
However, this method has several disadvantages: 1) poor process compatibility with conventional integrated circuits: in order to obtain GeOI with different strain amounts, the method needs to additionally manufacture bending tables with corresponding different curvature radii, and the manufactured bending tables need to be compatible with the existing annealing equipment. 2) The reliability is poor: according to the process method, a compression bar is used for applying mechanical external force to bend the GeOI wafer, so that defects are introduced into the top layer Ge; if the curvature of the GeOI wafer is too large, the wafer may be cracked. 3) The mechanical bending cannot be too curved due to the fear of cracking of the GeOI wafer, which limits the amount of strain introduced in the top layer Ge, which can be achieved to a small extent.
Disclosure of Invention
The invention aims to provide methods for manufacturing wafer-level uniaxial strain Ge on an SiN buried insulating layer based on a silicon nitride stress film and a scale effect aiming at the defects of the prior art, so as to reduce the complexity and cost of the manufacturing process of a strain GeOI wafer, improve the strain capacity of the uniaxial strain GeOI, enhance the electron mobility and the hole mobility of the GeOI wafer, and meet the requirements of electrical and optical properties of GeOI devices and integrated circuits.
In order to achieve the purpose, the technical scheme of the invention comprises the following steps:
(1) cleaning a GeOI wafer, wherein the GeOI wafer comprises a top Ge layer, an SiN buried insulating layer and a Si substrate;
(2) carrying out He ion implantation on the cleaned GeOI wafer, namely implanting He ions into the interface of the SiN buried insulating layer and the Si substrate of the GeOI wafer;
(3) depositing a compressive stress SiN film with the thickness of more than-1.1 GPa or a tensile stress SiN film with the thickness of more than 1.1GPa on the Ge layer of the GeOI wafer after ion implantation by adopting the processes of PECVD and the like;
(4) carrying out strip-shaped patterning on the SiN film by utilizing a semiconductor photoetching and etching process to form a strip-shaped SiN film array with the strip width and the spacing of 0.13-0.19 mu m, wherein the strip-shaped SiN film array is used for eliminating stress in the width direction to obtain silicon nitride compressive stress strips or tensile stress strips with only stress in the length direction, so that the top Ge layer and the SiN buried insulating layer are subjected to integral uniaxial tensile deformation or uniaxial compressive deformation, and further the GeOI wafer is converted into a wafer-level uniaxial strain GeOI;
(5) annealing the GeOI wafer with the strip-shaped SiN film array formed on the surface of the top Ge layer to further -step increase the stress of the SiN film and plastically deform the SiN buried insulating layer to ensure that the top Ge layer stress does not disappear after the SiN film is removed;
(6) and removing the strip-shaped SiN film array on the surface of the GeOI wafer through wet etching to finally obtain the wafer-level uniaxial tensile strain GeOI or uniaxial compressive strain GeOI material.
The invention has the following advantages:
1. the method is completely compatible with the existing integrated circuit process: the wafer-level uniaxial strain SOI can be manufactured by the conventional Si process such as PECVD process deposition, pattern photoetching, etching and the like, and the process is simple and does not need additional equipment required by the customized process.
2. The reliability is high: according to the invention, the high-stress SiN strip array is introduced into the wafer-level uniaxial strain, and no mechanical external force is required to be applied to the GeOI, so that the wafer is prevented from being bent, defects in the top Ge layer and wafer fracture are avoided, and the yield is improved.
3. The cost is low: because the high-stress SiN strip array is adopted, the wafer-level uniaxial strain can be directly introduced, so that a common SiN buried insulating layer GeOI wafer can be adopted to manufacture the uniaxial global strain GeOI material instead of the biaxial strain GeOI wafer, and the process cost is reduced.
4. Large strain capacity: according to the method, strain is introduced by enabling the top Ge layer and the SiN buried insulating layer to generate integral uniaxial tensile deformation or uniaxial compressive deformation through uniaxial stress of the strip-shaped SiN strip array, and the strain amount can be increased by adjusting a SiN film deposition process.
5. The flatness is high: according to the invention, the GeOI wafer is not bent by adopting a mechanical external force, so that the GeOI wafer is not bent, and the surface of the GeOI wafer is smooth.
6. And (3) parasitic reaction inhibition: by means of SiO2As the buried insulating layer, unnecessary reaction with germanium is easily generated to generate GeO, and the reaction can be obviously inhibited by adopting SiN as the buried insulating layer.
Drawings
Fig. 1 is a process flow diagram of a conventional wafer-level uniaxially strained GeOI wafer.
FIG. 2 is a process flow diagram of the wafer level uniaxial strained Ge process on SiN buried insulating layers in accordance with the present invention.
FIG. 3 is a top view of an array of striped SiN films deposited on a top Ge layer in accordance with the present invention.
Detailed Description
The technical principle of the invention is as follows:
according to the principle of an ion implantation process, He ions are implanted into the interface between the SiN buried insulating layer and the substrate Si layer to cause the interface combination of the SiN buried insulating layer and the substrate Si layer to become loose, so that the SiN buried insulating layer and a top layer Ge layer on the SiN buried insulating layer are easy to generate corresponding strain after a high-stress SiN film is deposited, and according to the principle of a material mechanics scale effect, a strip-shaped SiN film array with the width and the spacing of 130 nm-190 nm is manufactured through a semiconductor process technology, so that stress in the strip width direction is released, stress along the strip length direction is not changed, the strip-shaped SiN film array has uniaxial compressive stress or uniaxial tensile stress, uniaxial tensile strain or uniaxial compressive strain is introduced into the top layer Ge layer and the SiN buried insulating layer, in the annealing process, the stress of the strip-shaped SiN film array is enhanced in step, the SiN buried insulating layer is simultaneously caused to generate tensile or compressive plastic deformation, the top layer Si is still in elastic deformation, and the SiN buried insulating layer finally has uniaxial compressive strain to form an SOI wafer.
The SiN buried insulating layer GeOI wafer comprises 3 inches, 4 inches, 5 inches, 6 inches, 8 inches and 12 inches of different specifications, and the thickness of a top Ge layer is 100-500 nm.
Referring to fig. 2, the invention provides three embodiments of a method for manufacturing wafer-level uniaxial strain Ge on an SiN buried insulating layer based on a silicon nitride stress film and a scale effect, namely, 4-inch, 8-inch and 12-inch SiN buried insulating layer uniaxial strain GeOI wafer materials are prepared, and SiN buried insulating layer GeOI wafers with different specifications all comprise three-layer structures: a Si substrate 3, a buried insulating layer 2 of SiN and a top Ge layer 1 as shown in fig. 2 a. Wherein:
the thickness of a Si substrate of the 4-inch SiN buried insulating layer GeOI wafer is 600 microns, the thickness of the SiN buried insulating layer is 500nm, and the thickness of a top Ge layer is 150 nm;
the thickness of a Si substrate of the 8-inch SiN buried insulating layer GeOI wafer is 600 microns, the thickness of the SiN buried insulating layer is 500nm, and the thickness of a top Ge layer is 250 nm;
the thickness of a Si substrate of the 12-inch GeOI wafer with the SiN buried insulating layer is 600 mu m, the thickness of the SiN buried insulating layer is 500nm, and the thickness of a top Ge layer is 350 nm.
Example 1a 4 inch SiN buried insulator layer uniaxial tensile strained GeOI wafer material was prepared.
Step 1: and cleaning the SiN buried insulating layer GeOI wafer to remove surface pollutants.
(1.1) alternately carrying out ultrasonic cleaning on the GeOI wafer by using acetone and isopropanol to remove organic matter pollution on the surface of the substrate;
(1.2) configuration 1: 1: 3, heating the mixed solution of ammonia water, hydrogen peroxide and deionized water to 120 ℃, soaking the GeOI wafer in the mixed solution for 12 minutes, taking out the GeOI wafer, and washing the GeOI wafer by using a large amount of deionized water to remove inorganic pollutants on the surface of the GeOI wafer;
and (1.3) soaking the GeOI wafer in an HF acid buffer solution for 2 minutes to remove the oxide layer on the surface.
Step 2: and (5) ion implantation.
The cleaned GeOI wafer is ion implanted to loosen the Si substrate 3 and SiN buried insulator layer 2 interface 4 as shown in fig. 2 b.
The process conditions of the ion implantation are as follows: the implanted ions are He ions, and the implantation dose is 1.1E14cm-2And an implant energy of 70 Kev.
And step 3: and depositing a SiN film.
By adopting a PECVD plasma enhanced chemical vapor deposition process, a compressive stress SiN film 5 with the thickness of 1.0 μm and the stress of-1.1 GPa is deposited on the surface of the top Ge layer 1 of the GeOI wafer after ion implantation is finished, as shown in FIG. 2 c.
The deposition process conditions are as follows: high-frequency HF power is 0.22KW, low-frequency LF power is 0.82KW, and high-purity SiH4Flow 0.41slm, high purity NH3The flow was 2.2slm, the flow of high purity nitrogen was 2.2slm, the pressure in the reaction chamber was 2.8Torr, and the temperature in the reaction chamber was 400 ℃.
And 4, step 4: the compressive stress SiN film 5 is etched using semiconductor lithography and etching techniques to form a strip-shaped SiN film array 6, as shown in fig. 2 d.
(4.1) coating positive photoresist on the compressive stress SiN layer 5, drying the photoresist, exposing by using a photoetching plate with the strip width and the interval of 0.19 mu m, wherein the exposed area is a strip array with the width and the interval of 0.19 mu m, removing the positive photoresist of which the exposure area is easily dissolved in a developing solution by using a developing solution, and forming a strip photoresist mask film array on the SiN layer;
(4.2) adopting a reactive ion etching RIE process, wherein in the reaction chamber, the pressure is 4Pa, the temperature of the reaction chamber is 40 ℃, the temperature of the substrate is 5 ℃, the high-frequency radio frequency power of 13.56MHz is 400W, and the etching gas CHF is4Flow rate of 30sccm, O2The pressure deposited on the Ge layer on the top layer of the GeOI wafer is pressed under the condition that the gas flow is 3sccmEtching the stress SiN film 5 to form a strip-shaped SiN film array 6 with the width of 0.19 mu m, so as to eliminate the stress in the width direction and obtain a silicon nitride stress strip with the stress in the length direction only, wherein the top view of the obtained GeOI wafer with the SiN film array 6 is shown in FIG. 3;
and (4.3) removing the photoresist on the strip-shaped SiN film array.
And 5: and (6) annealing.
And annealing the GeOI wafer with the strip-shaped SiN film arrays 6 formed on the surface of the top Ge layer 1, as shown in FIG. 2e, namely annealing in inert gas He for 3.2 hours at the temperature of 310 ℃ at the temperature rising rate of 4 ℃/min, and then cooling at the temperature falling rate of 4 ℃/min, wherein in the annealing process, the stress of the strip-shaped SiN film arrays 6 is further increased by steps, so that the SiN buried insulating layer 2 is subjected to tensile plastic deformation.
Step 6: the strip-shaped SiN film array 6 on the surface of the Ge layer 1 on the top layer of the GeOI wafer is removed as shown in fig. 2 f.
And putting the GeOI wafer deposited with the strip-shaped SiN film array 6 into a phosphoric acid solution with the volume fraction of 85% for wet etching at 150 ℃ for 6 minutes to finally obtain the uniaxial tensile strain GeOI wafer material with the strain top Ge layer 7.
Example 2 an 8 inch SiN buried insulator layer uniaxial compressive strain GeOI wafer material was prepared.
In step , the buried SiN insulator GeOI wafer is cleaned to remove surface contaminants.
This step was carried out in the same manner as in step 1 of example 1.
Step two: the implantation dose of the cleaned GeOI wafer is 1.1E15cm-2He ions of energy 110Kev to loosen the interface 4 of the Si substrate 3 and the SiN buried insulating layer 2 as shown in fig. 2 b.
Step three: by adopting a PECVD plasma enhanced chemical vapor deposition process, a tensile stress SiN film 5 with the thickness of 1.1 mu m and the stress of 1.2GPa is deposited on the surface of the top Ge layer 1 of the GeOI wafer after ion implantation is finished, as shown in FIG. 2 c.
The deposition process conditions are as follows: high-frequency HF power is 1.3KW, low-frequency LF power is 0.31KW, and high-purity SiH4Flow 0.31slm, high purity NH3The flow was 1.9slm, the flow of high purity nitrogen was 1.1slm, the reaction chamber pressure was 3.1Torr, and the reaction chamber temperature was 400 ℃.
Step four: the tensile stressed SiN film 5 is etched using semiconductor lithography and etching techniques to form a strip-shaped SiN film array 6, as shown in fig. 2 d.
(4a) Coating positive photoresist on the tensile stress SiN layer 5, drying the photoresist, exposing by using a photoetching plate with strip width and interval of 0.17 μm, wherein the exposed area is a strip array with width and interval of 0.17 μm, removing the positive photoresist with exposing area easily soluble in developing solution by using developing solution, and forming a strip photoresist mask film array on the SiN layer;
(4b) etching the tensile stress SiN film 5 deposited on the top Ge layer of the GeOI wafer by adopting a reactive ion etching RIE process to form a strip-shaped SiN film array 6 with the width of 0.17 mu m, so as to eliminate the stress in the width direction and obtain a silicon nitride stress strip with the stress in the length direction only, wherein the top view of the obtained GeOI wafer with the SiN film array 6 is shown in FIG. 3, and the conditions of the reactive ion etching RIE process are the same as those of the step (4.1) in the embodiment 1;
(4c) the photoresist on the strip-shaped SiN thin film array 6 is removed.
And step five, annealing the GeOI wafer with the strip-shaped SiN film array 6 formed on the surface of the top Ge layer 1, as shown in figure 2e, namely annealing in inert gas He for 2.7 hours under the conditions that the heating rate is 4 ℃/min and the temperature is 360 ℃, and then cooling at the rate of 4 ℃/min, wherein in the annealing process, the stress of the strip-shaped SiN film array 6 is further -step enhanced, so that the SiN buried insulating layer 2 generates compressive plastic deformation.
Step six: the strip-shaped SiN film array 6 on the surface of the Ge layer 1 on the top layer of the GeOI wafer is removed as shown in fig. 2 f.
And putting the GeOI wafer deposited with the strip-shaped SiN film array 6 into a phosphoric acid solution with the volume fraction of 85% for wet etching at 170 ℃ for 9 minutes to finally obtain the uniaxial compressive strain GeOI wafer material with the strain top Ge layer 7.
Example 3 a 12 inch SiN buried insulator layer uniaxial tensile strained GeOI wafer material was prepared.
Step A: and cleaning the SiN buried insulating layer GeOI wafer to remove surface pollutants.
This step was carried out in the same manner as in step 1 of example 1.
And B: the cleaned GeOI wafer is ion implanted to loosen the Si substrate 3 and SiN buried insulator layer 2 interface 4 as shown in fig. 2 b.
The ion implantation process comprises the following steps: the implanted ions are He ions, and the implantation dose is 1.1E16cm-2And an implant energy of 150 Kev.
And C: and depositing a high-pressure stress SiN film.
Adopting PECVD plasma enhanced chemical vapor deposition process, and performing high-purity SiH at high-frequency HF power of 0.41KW and low-frequency LF power of 0.61KW4Flow 0.21slm, high purity NH3Under the conditions of a flow of 2.4slm, a flow of high-purity nitrogen of 2.6slm, a pressure of the reaction chamber of 3.0Torr and a temperature of the reaction chamber of 400 ℃, a compressive stress SiN film 5 with a thickness of 1.2 μm and a stress of-1.3 GPa is deposited on the surface of the top Ge layer 1 of the GeOI wafer after ion implantation, as shown in fig. 2 c.
Step D: and etching the compressive stress SiN film.
(D1) Coating positive photoresist on the compressive stress SiN layer 5 by using semiconductor photoetching and etching technology, drying the photoresist, exposing by using a photoetching plate with strip width and interval of 0.13 mu m, wherein the exposed area is a strip array with width and interval of 0.13 mu m, removing the positive photoresist of which the exposure area is easily dissolved in developing solution by using developing solution, and forming a strip photoresist mask film array on the SiN layer;
(D2) the compressively stressed SiN film 5 deposited on the top Ge layer of the GeOI wafer is etched by a reactive ion etching RIE process to form a strip-shaped SiN film array 6 with a width of 0.13 μm, as shown in fig. 2 d. The top view of the obtained GeOI wafer with the SiN film array 6 is shown in fig. 3, and the conditions of the reactive ion etching RIE process are the same as those of the step (4.1) of the embodiment 1;
(D3) the photoresist on the strip-shaped SiN thin film array 6 is removed.
Step E: and (5) ion implantation.
And annealing the GeOI wafer with the strip-shaped SiN film arrays 6 formed on the surface of the top Ge layer 1, as shown in FIG. 2e, namely annealing in inert gas He for 2.2 hours at the temperature of 410 ℃ at the temperature rising rate of 4 ℃/min, and then cooling at the rate of 4 ℃/min, wherein in the annealing process, the stress of the strip-shaped SiN film arrays 6 is further increased , so that the SiN buried insulating layer 2 is subjected to tensile plastic deformation.
Step F: the strip-shaped SiN film array 6 on the surface of the Ge layer 1 on the top layer of the GeOI wafer is removed as shown in fig. 2 f.
And putting the GeOI wafer deposited with the strip-shaped SiN film array 6 into a phosphoric acid solution with the volume fraction of 85% for wet etching at 190 ℃ for 12 minutes to finally obtain the uniaxial tensile strain GeOI wafer material with the strain top Ge layer 7.
Claims (9)
1. The manufacturing method of the wafer-level uniaxial strain Ge on the SiN buried insulating layer based on the silicon nitride stress film and the scale effect comprises the following steps of:
(1) cleaning a GeOI wafer of germanium on an insulating layer, wherein the GeOI wafer comprises a top Ge layer, an SiN buried insulating layer and a Si substrate;
(2) carrying out He ion implantation on the cleaned GeOI wafer, namely implanting He ions into the interface of the SiN buried insulating layer and the Si substrate of the GeOI wafer;
(3) depositing a compressive stress SiN film with the thickness of more than-1.1 GPa or a tensile stress SiN film with the thickness of more than 1.1GPa on the Ge layer of the GeOI wafer after ion implantation by adopting a PECVD process;
(4) carrying out strip-shaped patterning on the SiN film by utilizing a semiconductor photoetching and dry etching process to form a strip-shaped SiN film array with the strip width and the spacing of 0.13-0.19 mu m, wherein the strip-shaped SiN film array is used for eliminating stress in the width direction to obtain silicon nitride compressive stress strips or tensile stress strips with only stress in the length direction, so that the top Ge layer and the SiN buried insulating layer are subjected to integral uniaxial tensile deformation or uniaxial compressive deformation, and further a GeOI wafer is converted into a wafer-level uniaxial strain GeOI;
(5) annealing the GeOI wafer with the strip-shaped SiN film array formed on the surface of the top Ge layer to further -step increase the stress of the SiN film and plastically deform the SiN buried insulating layer to ensure that the top Ge layer stress does not disappear after the SiN film is removed;
(6) and removing the strip-shaped SiN film array on the surface of the GeOI wafer through wet etching to finally obtain the wafer-level uniaxial tensile strain GeOI or uniaxial compressive strain GeOI material.
2. The method of claim 1, wherein the GeOI wafer in step (1) comprises different specifications of 3 inches, 4 inches, 5 inches, 6 inches, 8 inches, 12 inches with a top Ge layer thickness of 100-500 nm.
3. The method of claim 1, wherein the step (1) of cleaning the GeOI wafer comprises the steps of:
(1a) using acetone and isopropanol to alternately perform ultrasonic cleaning on the GeOI wafer so as to remove organic matter pollution on the surface of the substrate;
(1b) configuration 1: 1: 3, heating the mixed solution of ammonia water, hydrogen peroxide and deionized water to 120 ℃, soaking the GeOI wafer in the mixed solution for 12 minutes, taking out the GeOI wafer, and washing the GeOI wafer by using a large amount of deionized water to remove inorganic pollutants on the surface of the GeOI wafer;
(1c) and soaking the GeOI wafer in an HF acid buffer solution for 2 minutes to remove the oxide layer on the surface.
4. The method of claim 1, wherein the ion implantation in step (2) is performed with He ions at a dose of from 1.1E14cm-2～1.1E16cm-2The implantation energy varies from 70Kev to 150Kev depending on the thickness of the top Ge layer.
5. The method of claim 1, wherein step (3) comprises depositing a compressive SiN layer on the top Ge layer by a plasma chemical vapor deposition PECVD process having the following parameters:
the high-frequency power HF is 0.21 KW-0.41 KW;
the low-frequency power LF is from 0.61KW to 0.81 KW;
high puritySiH4High-purity NH with the flow rate of 0.21slm to 0.41slm3The flow rate is 2.2 slm-2.4 slm, and the flow rate of high-purity nitrogen is 2.2 slm-2.6 slm;
the pressure of the reaction chamber is 2.8 Torr-3.0 Torr;
the temperature of the reaction chamber is 400 ℃;
the deposition thickness is 1.0-1.2 μm.
6. The method of claim 1, wherein step (3) comprises depositing a tensile SiN layer on the top Ge layer using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process with the following parameters:
the high-frequency power HF is 1.2 KW-1.4 KW;
the low-frequency power LF is from 0.21KW to 0.41 KW;
high purity SiH4High-purity NH with the flow rate of 0.21slm to 0.41slm3The flow rate is 1.8 slm-2.0 slm, and the flow rate of high-purity nitrogen is 0.9 slm-1.3 slm;
the pressure of the reaction chamber is 3.0 Torr-3.2 Torr;
the temperature of the reaction chamber is 400 ℃;
the deposition thickness is 0.9-1.1 μm.
7. The method according to claim 1, wherein the step (4) of etching the SiN layer into the stripe array by using the lithography and reactive ion etching RIE process is performed as follows:
(4a) coating positive photoresist on the SiN layer, drying the photoresist, exposing by using a photoetching plate with strip width and interval of 0.13-0.19 μm, wherein the exposed area is a strip array with width and interval of 0.13-0.19 μm, removing the positive photoresist with exposure area easily soluble in developing solution by using developing solution, and forming a strip photoresist mask film array on the SiN layer;
(4b) etching a photoresist-free masking film region deposited on the top Ge of the GeOI wafer, namely SiN under an exposure region, by adopting a Reactive Ion Etching (RIE) process, and leaving the SiN under a strip-shaped photoresist masking film to obtain an SiN strip array with the width and the spacing of 0.13-0.19 mu m;
(4c) the strip-shaped photoresist masking film is removed, leaving only the SiN strip-shaped array.
8. The method of claim 1, wherein the annealing in step (5) is performed under the following process conditions: temperature: 310 ℃ to 410 ℃, time: 2.2-3.2 hours, environment: he. Ne, Ar or a mixture thereof.
9. The method according to claim 1, wherein the wet etching for removing the SiN film in step (6) is performed by using 85% phosphoric acid solution by volume fraction at a temperature of 150-200 ℃ for 5-20 minutes.
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| CN101454894A (en) * | 2006-05-30 | 2009-06-10 | 飞思卡尔半导体公司 | Engineering strain in thick strained-soi substrates |
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| CN101454894A (en) * | 2006-05-30 | 2009-06-10 | 飞思卡尔半导体公司 | Engineering strain in thick strained-soi substrates |
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