CN106067431B - 晶圆涂布系统与晶片封装体的制备方法 - Google Patents

晶圆涂布系统与晶片封装体的制备方法 Download PDF

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CN106067431B
CN106067431B CN201610235850.9A CN201610235850A CN106067431B CN 106067431 B CN106067431 B CN 106067431B CN 201610235850 A CN201610235850 A CN 201610235850A CN 106067431 B CN106067431 B CN 106067431B
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wafer
mobility
insulating materials
nozzle
encapsulation body
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CN106067431A (zh
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陈语同
苏冠群
许传进
陈键辉
叶晓岚
何彦仕
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XinTec Inc
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XinTec Inc
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Abstract

一种晶圆涂布系统与晶片封装体的制备方法。该晶圆涂布系统包含一晶圆底座、一流动性绝缘材料喷洒装置以及一晶圆倾斜升降销。晶圆底座具有一承载部与一旋转部,承载部装设于旋转部上,并用以承载一晶圆,且旋转部用以相对于一预定轴旋转。流动性绝缘材料喷洒装置位于晶圆底座上方,用以喷洒一流动性绝缘材料至晶圆,而晶圆倾斜升降销设置使晶圆与重力方向夹一第一锐角。本发明不仅提升了晶片封装体的绝缘性,还能够避免后续形成的导电层产生断线。

Description

晶圆涂布系统与晶片封装体的制备方法
技术领域
本发明关于一种晶圆涂布系统,以及使用此晶圆涂布系统的一种晶片封装体的制备方法。
背景技术
在各项电子产品要求多功能且外型尚须轻薄短小的需求之下,各项电子产品所对应的半导体晶片,不仅其尺寸微缩化,当中的布线密度亦随之提升,因此后续在制造半导体晶片封装体的挑战亦渐趋严峻。其中,晶圆级晶片封装是半导体晶片封装方式的一种,是晶圆上所有晶片生产完成后,直接对整片晶圆上所有晶片进行封装制程及测试,完成之后才切割制成单颗晶片封装体的晶片封装方式。
在半导体晶片尺寸微缩化、布线密度提高的情形之下,晶片的绝缘性质是当今晶片封装技术重要的研发方向之一,以防止产生错误的电性连接。通常使用氧化物作为晶片的绝缘层,但氧化物耗资昂贵,且沉积氧化物的方式繁复且耗时,而降低了制程效率。因此,环氧树酯系材料逐渐取代氧化物作为晶片封装体的绝缘层。
然而,环氧树酯系材料易受重力影响而聚集,其将不利于形成均匀的绝缘层,而大幅降低晶片封装体的良率。
发明内容
因此,本发明提供一种晶圆涂布系统以及使用此晶圆涂布系统的一种晶片封装体的制备方法,以形成均匀的绝缘层。
本发明的一态样提供一种晶圆涂布系统,包含一晶圆底座、一流动性绝缘材料喷洒装置以及一晶圆倾斜升降销。晶圆底座具有一承载部与一旋转部,承载部装设于旋转部上,并用以承载一晶圆,且旋转部用以相对于一预定轴旋转。流动性绝缘材料喷洒装置位于晶圆底座上方,用以喷洒一流动性绝缘材料至晶圆,而晶圆倾斜升降销设置使晶圆与重力方向夹一第一锐角。
根据本发明一或多个实施方式,晶圆倾斜升降销位于晶圆底座的下方。
根据本发明一或多个实施方式,晶圆倾斜升降销位于承载部与旋转部之间。
根据本发明一或多个实施方式,晶圆倾斜升降销控制第一锐角于45度至89度之间。
根据本发明一或多个实施方式,还包含一加热器连接至承载部,以加热晶圆。
根据本发明一或多个实施方式,流动性绝缘材料为感光性环氧树脂。
本发明的一态样提供一种晶圆涂布系统,包含一晶圆底座、一流动性绝缘材料喷洒装置以及一晶圆倾斜升降销。晶圆底座具有一承载部与一旋转部,承载部装设于旋转部上,并用以承载一晶圆,且旋转部用以相对于一预定轴旋转。流动性绝缘材料喷洒装置位于晶圆底座上方,流动性绝缘材料喷洒装置包含一喷嘴与一喷嘴移动单元。喷嘴设置以喷洒流动性绝缘材料,而喷嘴移动单元连接喷嘴,使喷嘴于晶圆上方轴向来回移动。
根据本发明一或多个实施方式,晶圆涂布系统还包含一连接杆连接承载部与喷嘴移动单元。
根据本发明一或多个实施方式,晶圆涂布系统还包含晶圆倾斜升降销,设置使晶圆与重力方向夹第一锐角。
根据本发明一或多个实施方式,还包含一喷嘴移动单元倾斜升降销设置于承载部与喷嘴移动单元之间,以使喷嘴移动单元与重力方向夹一第二锐角。
根据本发明一或多个实施方式,流动性绝缘材料为感光性环氧树脂。
本发明的另一态样提供一种晶片封装体的制备方法,包含下列步骤:先提供一晶圆,其包含一导电垫、以及相对的一第一表面与一第二表面;接着形成一穿孔自第二表面朝第一表面延伸,以暴露导电垫;再倾斜晶圆,使晶圆与重力方向夹一第一锐角;再旋转晶圆,并喷洒一流动性绝缘材料至晶圆的第二表面上与穿孔中;最后固化流动性绝缘材料。
根据本发明一或多个实施方式,还包含下列步骤。移除穿孔中的流动性绝缘材料以暴露导电垫,并形成一导电层于第二表面上与穿孔中。再形成一保护层覆盖导电层后,接着图案化保护层以形成一开口暴露导电层。最后形成一外部导电连结于该开口中。
根据本发明一或多个实施方式,还包含沿着一切割道切割晶圆,以形成一晶片封装体。
根据本发明一或多个实施方式,固化流动性绝缘材料的温度介于35℃至45℃之间。
根据本发明一或多个实施方式,第一锐角介于45度至89度之间。
根据本发明一或多个实施方式,第一锐角介于70度至89度之间。
根据本发明一或多个实施方式,第一锐角介于85度至89度之间。
根据本发明一或多个实施方式,倾斜晶圆使流动性绝缘材料自穿孔的一底部流动至穿孔的一侧壁。
根据本发明一或多个实施方式,流动性绝缘材料为一感光性环氧树脂。
根据本发明一或多个实施方式,固化流动性绝缘材料后还包含水平置放晶圆。
本发明的另一态样提供一种晶片封装体的制备方法,包含下列步骤:先提供一晶圆,其包含一导电垫、以及相对的一第一表面与一第二表面;接着形成一穿孔自第二表面朝第一表面延伸,以暴露导电垫,再倾斜晶圆,使晶圆与重力方向夹一第一锐角;旋转晶圆,并使用流动性绝缘材料喷洒装置喷洒流动性绝缘材料,流动性绝缘材料喷洒装置包含一喷嘴与一喷嘴移动单元,喷嘴喷洒流动性绝缘材料,而喷嘴移动单元连接喷嘴,使喷嘴于晶圆上方轴向来回移动;最后固化流动性绝缘材料。
根据本发明一或多个实施方式,晶片封装体的制备方法还包含倾斜晶圆,使晶圆与重力方向夹第一锐角。
本发明不仅提升了晶片封装体的绝缘性,还能够避免后续形成的导电层产生断线。
附图说明
为让本发明的上述和其他目的、特征、优点与实施例能更明显易懂,所附图式的详细说明如下。
图1绘式本发明的部分实施例中,一种晶圆涂布系统的剖面图;
图2绘式本发明的其他部分实施例中,一种晶圆涂布系统的剖面图;
图3绘式本发明的其他部分实施例中,一种晶圆涂布系统的剖面图;
图4绘示根据本发明部分实施方式的晶片封装体的制造方法流程图;
图5A~5F绘示本发明部分实施方式中晶片封装体在制程各个阶段的剖面图;
图6绘示本发明部分实施方式中晶圆倾斜的示意图;
图7A为图6的晶片区位于位置A时,沿着剖线AA的剖面图;
图7B为图6的晶片区位于位置B时,沿着剖线BB的剖面图;
图7C为图6的晶片区位于位置C时,沿着剖线CC的剖面图;以及
图7D为图6的晶片区位于位置D时,沿着剖线DD的剖面图。
其中,附图中符号的简单说明如下:
100:晶圆涂布系统 510:导电垫
110:晶圆底座 520:第一表面
112:承载部 530:第二表面
114:旋转部 540:穿孔
116:预订轴 542:右侧壁
120:晶圆倾斜升降销 544:左侧壁
130:流动性绝缘材料喷洒装置 546:前侧壁
132:喷嘴 548:后侧壁
134:喷嘴移动单元 550:流动性绝缘材料
136:方向 560:导电层
138:方向 570:保护层
140:加热器 572:开口
150:流动性绝缘材料 580:外部导电连结
160:连接杆 595:切割道
200:晶圆涂布系统 610:方向
300:晶圆涂布系统 620:方向
360:喷嘴移动单元倾斜升降销 A、B、C、D:位置
410~480:步骤 T1、T2、T3:厚度
500:晶圆 α:第一锐角
500a:晶片区 β:第二锐角。
具体实施方式
以下将以图式揭露本发明的多个实施方式,为明确说明起见,许多实务上的细节将在以下叙述中一并说明。然而,应了解到,这些实务上的细节不应用以限制本发明。也就是说,在本发明部分实施方式中,这些实务上的细节是非必要的。此外,为简化图式起见,一些已知惯用的结构与元件在图式中将以简单示意的方式绘示。
请先参阅图1,图1绘式本发明的部分实施例中,一种晶圆涂布系统的剖面图。一晶圆涂布系统100包含一晶圆底座110、一晶圆倾斜升降销120以及一流动性绝缘材料喷洒装置130。晶圆底座110包含一承载部112与一旋转部114,其中承载部112装设于旋转部114上以承载一晶圆500。而旋转部114用以相对于一预订轴116旋转。
晶圆倾斜升降销120位于晶圆底座110的下方。晶圆倾斜升降销120可提高或降低晶圆底座110其中一侧的高度,以令使晶圆底座110上的晶圆500与重力方向夹一第一锐角α。流动性绝缘材料喷洒装置130则位于晶圆底座110上方,以喷洒流动性绝缘材料150至晶圆500上。
值得注意的是,晶圆倾斜升降销120的位置并不以图1为限。请参阅图2,图2绘式本发明的其他部分实施方式中,一种晶圆涂布系统的剖面图。在图2中,与图1相同的元件使用相同的元件符号,在此不再详述。图2的晶圆涂布系统200与图1的晶圆涂布系统100之间的差别在于,晶圆倾斜升降销120位于晶圆底座110的承载部112与旋转部114之间。晶圆倾斜升降销120提高或降低承载部112其中一侧的高度,同样可令使承载部112上的晶圆500与重力方向夹一第一锐角α。
更详细的说,流动性绝缘材料150覆盖晶圆500的表面,还进入晶圆500的穿孔中覆盖穿孔的底部与侧壁,以作为绝缘层。晶圆500与重力方向之间的第一锐角α使流动性高的流动性绝缘材料150自穿孔的底部流往侧壁,不会在穿孔底部累积过厚的流动性绝缘材料150。同时,此第一锐角α亦避免晶圆500表面的流动性绝缘材料150因重力流的影响而流向穿孔底部,以维持晶圆500良好的绝缘性。在本发明的部分实施例中,晶圆倾斜升降销120控制第一锐角α于45度至89度之间。在本发明的其他部分实施例中,晶圆倾斜升降销120控制第一锐角α于70度至89度之间。在本发明的其他部分实施例中,晶圆倾斜升降销120控制第一锐角α于85度至89度之间。
在喷洒流动性绝缘材料150的过程中,旋转部114还相对于预定轴116旋转晶圆500,使流动性绝缘材料150能均匀的流往各个方向的侧壁。此外,晶圆涂布系统100还包含一加热器140连接至承载部112。加热器140提供热能至承载部112,以加热固化喷洒至晶圆500上的流动性绝缘材料150,而完成绝缘层的制备步骤。在本发明的部分实施例中,旋转部114可依制程需求调控适当转速,以制备均匀的绝缘层。
流动性绝缘材料喷洒装置130包含一喷嘴132与一喷嘴移动单元134。喷嘴132设置以喷洒流动性绝缘材料150,而喷嘴移动单元134设置以使喷嘴132能于晶圆500上方来回轴向移动。具体而言,晶圆500中有多个晶片区,其在切割后形成独立的晶片封装体。在旋转部114相对于预定轴116旋转晶圆500时,喷嘴移动单元134使喷嘴132沿着方向136或方向138来回的轴向移动至此些晶片区上方,以在每个晶片区中均匀的喷洒流动性绝缘材料150。
请继续参阅图1,图1的晶圆涂布系统100还具有一连接杆160,设置以连接承载部112与流动性绝缘材料喷洒装置130的喷嘴移动单元134,因此在倾斜晶圆500的同时会倾斜喷嘴移动单元134,使其与水平面之间具有一第二锐角β。连接杆160使第一锐角α与第二锐角β具有相同的角度,以让喷嘴132在移动时与晶圆500之间的垂直距离维持恒定,且喷嘴132能以大致垂直的方向喷洒流动性绝缘材料150至晶圆500上的各个晶片区中。
在本发明的其他部分实施例中,第一锐角α可不同于第二锐角β。请先参阅图3,图3绘式本发明的其他部分实施方式中,一种晶圆涂布系统的剖面图。在图3中,与图1相同的元件使用相同的元件符号,在此不再详述。图3的晶圆涂布系统300与图1的晶圆涂布系统100之间的差别在于,晶圆涂布系统300还具有一喷嘴移动单元倾斜升降销360设置于承载部112与喷嘴移动单元134之间,其可提高或降低喷嘴移动单元134其中一侧的高度,以令使喷嘴移动单元134与重力方向夹一第一锐角β。喷嘴移动单元倾斜升降销360使第一锐角α可不同于第二锐角β,因此喷嘴132在移动时与晶圆500之间能具有不同的垂直距离。此外,喷嘴132并非垂直对准晶圆500,而以大致斜向的方向喷洒流动性绝缘材料150至晶圆500上的各个晶片区中。换句话说,斜向喷洒可增加流动性绝缘材料150于穿孔侧壁上的沉积量,进而减少穿孔底部的流动性绝缘材料150的厚度。
请接着参阅图4,图4绘示根据本发明部分实施方式的晶片封装体的制造方法流程图。请同时参阅图5A~5F以进一步理解晶片封装体的制备过程,图5A~5F绘示晶片封装体在制程各个阶段的剖面图。
请先参阅步骤410与图5A,提供一晶圆500,其中晶圆500包含一导电垫510、以及相对的一第一表面520与一第二表面530。晶圆500上具有多个晶片区,在后续制程后会切割此些晶片区以形成多个晶片封装体。在本发明的部分实施例中,晶圆500包含半导体元件、内层介电层(ILD)、内金属介电层(IMD)、钝化层(passivation layer)与内金属结构,其中导电垫510可为内金属结构中的金属层。
请继续参阅步骤420与图5B,形成一穿孔540自第二表面530朝第一表面520延伸,并暴露导电垫510。形成穿孔540的方式例如可以是微影蚀刻,但不以此为限。
请接着参阅步骤430,倾斜晶圆500,使晶圆500与重力方向夹一第一锐角α。可将晶圆500置于图1所示的晶圆涂布系统100的晶圆底座110上,并使用晶圆倾斜升降销120调整晶圆底座110一侧的高度,以倾斜晶圆500。但本发明并不以此为限,亦可使用任何合适的方法来倾斜晶圆500,而不影响本发明的精神。请同时参阅图6,图6绘示本发明部分实施方式中晶圆倾斜的示意图。为了清楚说明本发明,图6只绘示单一晶片区500a于晶圆500中,但应理解的是,晶圆500具有多个晶片区,而多条切割道分离此些晶片区,且晶圆500与重力方向之间夹一第一锐角α。在本发明的部分实施例中,第一锐角α介于45度至89度之间。在本发明的其他部分实施例中,第一锐角α介于70度至89度之间。在本发明的其他部分实施例中,第一锐角α介于85度至89度之间。
在本实施例中,在晶圆500中形成穿孔540后再倾斜晶圆500,但不以此为限。在本发明的其他部分实施例中,可在形成穿孔540前就先倾斜晶圆500。
请继续参阅步骤440,旋转晶圆500,并喷洒流动性绝缘材料550至晶圆500的第二表面530上与穿孔540中。可使用晶圆涂布系统100的流动性绝缘材料喷洒装置130喷洒流动性绝缘材料550,而旋转部114相对于预定轴116旋转晶圆500,例如可使晶圆500沿方向610或方向620旋转。如前所述,喷嘴132通过喷嘴移动单元134于晶圆500上方轴向来回移动,以均匀喷洒流动性绝缘材料550至各个晶片区500a中。此外,喷嘴移动单元134与重力方向之间的第二锐角β可相同或不同于第一锐角α。在本发明的部分实施例中,可依制程需求调控晶圆500的旋转速度。
接者请参阅图7A至7D以理解喷洒流动性绝缘材料550至晶圆500上的机制。图7A至7D为晶圆旋转时,晶片区500a沿着不同剖线的剖面示意图。
请先参阅图6与图7A。图7A为图6的晶片区500a位于位置A时,沿着剖线AA的剖面图。如图6与图7A所示,因晶圆500与重力方向夹第一锐角α,流动性高的流动性绝缘材料550会流动聚集至穿孔540的右侧壁542上,增加右侧壁542上的流动性绝缘材料550的厚度,并相应减少穿孔540的左侧壁544上流动性绝缘材料550的厚度。
接着参阅图6与图7B。图7B为图6的晶片区500a位于位置B时,沿着剖线BB的剖面图。如图6与图7B所示,在沿着方向610旋转晶圆500使晶片区500a移动至位置B时,因晶圆500与重力方向夹第一锐角α,流动性绝缘材料550会流动聚集至穿孔540的前侧壁546,增加前侧壁546上流动性绝缘材料550的厚度。相对的,穿孔540的后侧壁548上的流动性绝缘材料550的厚度减少。
继续参阅图6与图7C。图7C为图6的晶片区500a位于位置C时,沿着剖线CC的剖面图。如图6与图7C所示,继续沿着方向610旋转晶圆500使晶片区500a移动至位置C时,因晶圆500与重力方向夹第一锐角α,部分流动性绝缘材料550会自穿孔540的右侧壁542流往左侧壁544,不但进一步增加左侧壁544上的流动性绝缘材料550的厚度,亦相对的减少右侧壁542上的流动性绝缘材料550的厚度,使左侧壁544与右侧壁542上的流动性绝缘材料550具有大致相同的厚度。
最后参阅图6与图7D。图7D为图6的晶片区500a位于位置D时,沿着剖线DD的剖面图。如图7D所示,继续沿着方向610旋转晶圆500使晶片区500a移动至位置D时,因晶圆500与重力方向夹第一锐角α,部分流动性绝缘材料550会自穿孔540的前侧壁546流往后侧壁548,不但进一步增加后侧壁548上的流动性绝缘材料550的厚度,亦相对的减少前侧壁546上的流动性绝缘材料550的厚度,使前侧壁546与后侧壁548上的流动性绝缘材料550具有大致相同的厚度。
通过倾斜晶圆500使流动性高的流动性绝缘材料550流往穿孔540的侧壁,以减少在穿孔540底部累积的流动性绝缘材料550,其将有利于后续制程。同时,此第一锐角α亦避免晶圆500的第二表面530上的流动性绝缘材料550因重力流的影响而流向穿孔540底部,而维持晶圆500良好的绝缘性。此外,可重复图7A至7D的步骤数次,以确保流动性绝缘材料550能均匀的流往各个方向的侧壁上。值得注意的是,为了清楚说明本发明,图7A至7D绘示流动性绝缘材料550喷洒至穿孔540的四个侧壁542、544、546与548的机制。但所属领域技术人员应理解本发明并不以此为限,旋转晶圆500为连续性的动作,以使各个方向的侧壁均具有大致均匀的流动性绝缘材料550。
在本发明的其他部分实施例中,可不旋转晶圆500,而在喷洒流动性绝缘材料550时不断改变倾斜角度。举例来说,不断的调控晶圆倾斜升降销120以使晶圆底座110上的晶圆500往前、往后、往左、往右或任意的方向倾斜,使流动性绝缘材料550能均匀的流往各个方向的侧壁上。
请继续参阅步骤450与图5C,固化流动性绝缘材料550。晶圆涂布系统100中的加热器140提供热能至承载台112,以固化晶圆500中的流动性绝缘材料550。其中固化晶圆500的温度介于35℃至45℃之间。在本发明的部分实施例中,在固化流动性绝缘材料550后即水平置放晶圆500,以进行后续的步骤。例如,再次调整晶圆倾斜升降销120使晶圆500平行于水平面。如图5C所示,在固化后,穿孔540底部上的流动性绝缘材料550具有厚度T1,穿孔540侧壁上的流动性绝缘材料550具有厚度T2,而第二表面530上的流动性绝缘材料550具有厚度T3。需先说明的是,倾斜晶圆500确保穿孔540的侧壁与第二表面530交界处的流动性绝缘材料550仍维持一定的厚度,并不会流入穿孔540中而累积于穿孔540的底部,因此提升了第二表面530的绝缘性。再者,穿孔540的底部不会累积过厚的流动性绝缘材料550。在本发明的部分实施方式中,厚度T1、T2与T3大致相同。在本发明的其他部分实施方式中,厚度T3大于厚度T2,而厚度T2还大于厚度T1。
请接着参阅步骤460与图5D,移除穿孔540中的流动性绝缘材料550以暴露导电垫510,并形成一导电层560于第二表面530上与穿孔540中。在本实施例中,此流动性绝缘材料550为感光性环氧树脂,因此可直接以微影蚀刻方式来图案化流动性绝缘材料550,而不需使用光阻层即可定义流动性绝缘材料550的图案。图案化后,穿孔540底部的流动性绝缘材料550被移除,使导电垫510于穿孔540中暴露出来。接着可利用例如是溅镀、蒸镀、电镀或无电镀的方式来沉积导电材料于流动性绝缘材料550与穿孔540中的导电垫510上,以形成导电层560。如前所述,倾斜晶圆500能降低穿孔540底部的流动性绝缘材料550的厚度T1,避免了图案化过厚的流动性绝缘材料550时产生下切(undercut),而造成后续形成的导电层560断线。在本发明的部分实施例中,导电层560的材质例如可以采用铝(aluminum)、铜(copper)、镍(nickel)或其他合适的导电材料。
请接着参阅步骤470与图5E,形成一保护层570于导电层560上,并图案化保护层570以形成开口572暴露导电层560。可通过刷涂环氧树脂系的材料于导电层560上,以形成保护层570。接着,再图案化保护层570以形成开口572,使部分的导电层560于保护层570的开口572中暴露出来。
最后请参阅步骤480,并请参阅图5F,形成一外部导电连结580于开口中,并沿着一切割道595切割晶圆500,以形成一晶片封装体。外部导电连结580为焊球、凸块等业界熟知的结构,且形状可以为圆形、椭圆形、方形、长方形,并不用以限制本发明。在形成外部导电连结580后,沿着切割道595切割晶圆500、流动性绝缘材料550、导电层560与保护层570,以分离晶圆500上个多个晶片区500a,形成独立的晶片封装体。
由上述本发明实施例可知,本发明具有下列优点。本发明提供的晶圆涂布系统可应用于喷洒流动性绝缘材料至晶圆上,以形成绝缘层。在此制程中,倾斜的晶圆使晶圆表面与穿孔侧壁上的流动性绝缘材料不易流动至穿孔的底部,不仅能形成均匀的绝缘层,还提升了晶片封装体的绝缘性。更重要的是,降低穿孔底部的流动性绝缘材料的厚度使其在图案化后不易形成下切,进而避免后续形成的导电层产生断线。综前所述,本发明提供的晶圆涂布系统与晶片封装体的制备方法能有效提升制程良率,进而大幅减少制程成本。
以上所述仅为本发明较佳实施例,然其并非用以限定本发明的范围,任何熟悉本项技术的人员,在不脱离本发明的精神和范围内,可在此基础上做进一步的改进和变化,因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (20)

1.一种晶圆涂布系统,其特征在于,包含:
晶圆底座,具有承载部与旋转部,该承载部装设于该旋转部上,并用以承载晶圆,且该旋转部用以相对于预定轴旋转;
流动性绝缘材料喷洒装置,位于该晶圆底座上方,用以喷洒流动性绝缘材料至该晶圆;以及
晶圆倾斜升降销,设置使该晶圆与重力方向夹第一锐角。
2.根据权利要求1所述的晶圆涂布系统,其特征在于,该晶圆倾斜升降销位于该晶圆底座的下方。
3.根据权利要求1所述的晶圆涂布系统,其特征在于,该晶圆倾斜升降销位于该承载部与该旋转部之间。
4.根据权利要求1所述的晶圆涂布系统,其特征在于,该晶圆倾斜升降销控制该第一锐角于45度至89度之间。
5.根据权利要求1所述的晶圆涂布系统,其特征在于,还包含加热器,该加热器连接至该承载部,以加热该晶圆。
6.根据权利要求1所述的晶圆涂布系统,其特征在于,该流动性绝缘材料为感光性环氧树脂。
7.一种晶圆涂布系统,其特征在于,包含:
晶圆底座,具有承载部与旋转部,该承载部装设于该旋转部上,并用以承载晶圆,且该旋转部用以相对于预定轴旋转;
流动性绝缘材料喷洒装置,位于该晶圆底座上方,该流动性绝缘材料喷洒装置包含:
喷嘴,设置以喷洒流动性绝缘材料至该晶圆;以及
喷嘴移动单元连接该喷嘴,使该喷嘴于该晶圆上方轴向来回移动;
以及
晶圆倾斜升降销,该晶圆倾斜升降销使该晶圆与重力方向夹第一锐角。
8.根据权利要求7所述的晶圆涂布系统,其特征在于,还包含连接杆,该连接杆连接该承载部与该喷嘴移动单元。
9.一种晶圆涂布系统,其特征在于,包含:
晶圆底座,具有承载部与旋转部,该承载部装设于该旋转部上,并用以承载晶圆,且该旋转部用以相对于预定轴旋转;
流动性绝缘材料喷洒装置,位于该晶圆底座上方,该流动性绝缘材料喷洒装置包含:
喷嘴,设置以喷洒流动性绝缘材料至该晶圆;以及
喷嘴移动单元连接该喷嘴,使该喷嘴于该晶圆上方轴向来回移动;
以及
喷嘴移动单元倾斜升降销,该喷嘴移动单元倾斜升降销设置于该承载部与该喷嘴移动单元之间,以使该喷嘴移动单元与重力方向夹第二锐角。
10.一种晶片封装体的制备方法,其特征在于,包含:
提供晶圆,该晶圆包含导电垫、以及相对的第一表面与第二表面;
形成自该第二表面朝该第一表面延伸的穿孔,以暴露该导电垫;
倾斜该晶圆,使该晶圆与重力方向夹第一锐角;
旋转该晶圆,并喷洒流动性绝缘材料至该晶圆的该第二表面上与该穿孔中;以及
固化该流动性绝缘材料。
11.根据权利要求10所述的晶片封装体的制备方法,其特征在于,还包含:
移除该穿孔中的该流动性绝缘材料以暴露该导电垫;
于第二表面上与该穿孔中形成导电层;
形成覆盖该导电层的保护层;
图案化该保护层以形成暴露该导电层的开口;以及
于该开口中形成外部导电连结。
12.根据权利要求11所述的晶片封装体的制备方法,其特征在于,还包含沿着切割道切割该晶圆,以形成晶片封装体。
13.根据权利要求10所述的晶片封装体的制备方法,其特征在于,固化该流动性绝缘材料的温度介于35℃至45℃之间。
14.根据权利要求10所述的晶片封装体的制备方法,其特征在于,该第一锐角介于45度至89度之间。
15.根据权利要求10所述的晶片封装体的制备方法,其特征在于,该第一锐角介于70度至89度之间。
16.根据权利要求10所述的晶片封装体的制备方法,其特征在于,该第一锐角介于85度至89度之间。
17.根据权利要求10所述的晶片封装体的制备方法,其特征在于,倾斜该晶圆使该流动性绝缘材料自该穿孔的底部流动至该穿孔的侧壁。
18.根据权利要求10所述的晶片封装体的制备方法,其特征在于,该流动性绝缘材料为感光性环氧树脂。
19.根据权利要求10所述的晶片封装体的制备方法,其特征在于,固化该流动性绝缘材料后还包含:
水平置放该晶圆。
20.一种晶片封装体的制备方法,其特征在于,包含:
提供晶圆,该晶圆包含导电垫、以及相对的第一表面与第二表面;
形成自该第二表面朝该第一表面延伸的穿孔,以暴露该导电垫;
倾斜该晶圆,使该晶圆与重力方向夹第一锐角;
旋转该晶圆,并使用流动性绝缘材料喷洒装置喷洒流动性绝缘材料,该流动性绝缘材料喷洒装置包含:
喷嘴,设置以喷洒该流动性绝缘材料至该晶圆的该第二表面上与该穿孔中;以及
喷嘴移动单元连接该喷嘴,使该喷嘴于该晶圆上方轴向来回移动;以及
固化该流动性绝缘材料。
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TWI585870B (zh) * 2015-05-20 2017-06-01 精材科技股份有限公司 晶片封裝體及其製造方法
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200816333A (en) * 2006-08-11 2008-04-01 Texas Instruments Inc Process for precision placement of integrated circuit overcoat material
CN101699622A (zh) * 2009-11-18 2010-04-28 晶方半导体科技(苏州)有限公司 半导体器件封装结构及其封装方法
CN103633038A (zh) * 2013-11-29 2014-03-12 苏州晶方半导体科技股份有限公司 封装结构及其形成方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6869831B2 (en) 2001-09-14 2005-03-22 Texas Instruments Incorporated Adhesion by plasma conditioning of semiconductor chip surfaces
US8604113B2 (en) 2006-11-15 2013-12-10 Sumitomo Bakelite Co., Ltd. Photosensitive resin composition, insulating film, protective film, and electronic equipment
US20090196717A1 (en) 2008-01-31 2009-08-06 Holden Scott C Apparatus for Handling a Substrate and a Method Thereof
JP4941570B2 (ja) * 2010-03-04 2012-05-30 東京エレクトロン株式会社 液処理装置、液処理方法及び記憶媒体
US8890191B2 (en) 2011-06-30 2014-11-18 Chuan-Jin Shiu Chip package and method for forming the same
KR101807194B1 (ko) 2011-07-29 2017-12-08 에이비비 리써치 리미티드 경화성 에폭시 수지 조성물
JPWO2013146948A1 (ja) 2012-03-29 2015-12-14 東レ株式会社 塗布方法および塗布装置
GB201315727D0 (en) 2013-09-04 2013-10-16 Dow Corning Coated silicon wafer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200816333A (en) * 2006-08-11 2008-04-01 Texas Instruments Inc Process for precision placement of integrated circuit overcoat material
CN101699622A (zh) * 2009-11-18 2010-04-28 晶方半导体科技(苏州)有限公司 半导体器件封装结构及其封装方法
CN103633038A (zh) * 2013-11-29 2014-03-12 苏州晶方半导体科技股份有限公司 封装结构及其形成方法

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