CN106055496B - 一种eeprom控制器的信号生成电路及控制方法 - Google Patents
一种eeprom控制器的信号生成电路及控制方法 Download PDFInfo
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- CN106055496B CN106055496B CN201610341887.XA CN201610341887A CN106055496B CN 106055496 B CN106055496 B CN 106055496B CN 201610341887 A CN201610341887 A CN 201610341887A CN 106055496 B CN106055496 B CN 106055496B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- Engineering & Computer Science (AREA)
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microcomputers (AREA)
- Read Only Memory (AREA)
Abstract
Description
Symbol | Parameter | Min. | Max. | Unit |
tCS | CE Setup time to AE | 0 | ns | |
tCH | CE Hold time to AE or HVSTR | 10 | ns | |
tAS | Address Setup time to AE | 0 | ns | |
tAH | Address Hold time to AE | 10 | ns | |
Tds | Data setup time to AE | 0 | ns | |
Tdh | Data hold time to AE | 10 | ns | |
TWS | WE/ERONLY/PGONLY/EMODE setup to AE | 0 | ns | |
TWH | WE/ERONLY/PGONLY/EMODE hold to AE | 10 | ns | |
tAEPH | AE pulse high width | 10 | ns | |
tAEPL | AE pulse low width | 10 | ns | |
tAADW | AE to AE delay for Write mode | 100 | ns |
Claims (11)
Priority Applications (1)
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CN201610341887.XA CN106055496B (zh) | 2016-05-20 | 2016-05-20 | 一种eeprom控制器的信号生成电路及控制方法 |
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CN201610341887.XA CN106055496B (zh) | 2016-05-20 | 2016-05-20 | 一种eeprom控制器的信号生成电路及控制方法 |
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CN106055496A CN106055496A (zh) | 2016-10-26 |
CN106055496B true CN106055496B (zh) | 2018-08-17 |
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Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN110492884B (zh) * | 2019-09-11 | 2024-02-13 | 长春思拓电子科技有限责任公司 | 超前半比预测电子系统 |
US12047080B2 (en) | 2021-07-07 | 2024-07-23 | Changxin Memory Technologies, Inc. | Input sampling method and circuit, memory and electronic device |
CN115602220A (zh) * | 2021-07-07 | 2023-01-13 | 长鑫存储技术有限公司(Cn) | 一种输入采样方法、输入采样电路及半导体存储器 |
US11978502B2 (en) | 2021-07-07 | 2024-05-07 | Changxin Memory Technologies, Inc. | Input sampling method, input sampling circuit and semiconductor memory |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6795520B2 (en) * | 2002-01-31 | 2004-09-21 | Zarlink Semiconductor Inc. | High speed digital counters |
CN101819809A (zh) * | 2010-04-13 | 2010-09-01 | 北京大学 | 一种数据自动读出生效的eeprom电路及其实现方法 |
CN102354530A (zh) * | 2011-08-25 | 2012-02-15 | 西安电子科技大学 | 用于无源uhfrfid芯片的eeprom读取装置 |
CN102468842A (zh) * | 2010-11-16 | 2012-05-23 | 北京中电华大电子设计有限责任公司 | 一种同步计数器电路及其实现方法 |
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2016
- 2016-05-20 CN CN201610341887.XA patent/CN106055496B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6795520B2 (en) * | 2002-01-31 | 2004-09-21 | Zarlink Semiconductor Inc. | High speed digital counters |
CN101819809A (zh) * | 2010-04-13 | 2010-09-01 | 北京大学 | 一种数据自动读出生效的eeprom电路及其实现方法 |
CN102468842A (zh) * | 2010-11-16 | 2012-05-23 | 北京中电华大电子设计有限责任公司 | 一种同步计数器电路及其实现方法 |
CN102354530A (zh) * | 2011-08-25 | 2012-02-15 | 西安电子科技大学 | 用于无源uhfrfid芯片的eeprom读取装置 |
Non-Patent Citations (2)
Title |
---|
EEPROM基于I2C总线的一种读写方法;苏琦;《山西电子技术》;20010228(第1期);16-19 * |
基于I2C接口EEPROM读写控制器设计;杨帆;《微型机与应用》;20150525;第34卷(第10期);22-24 * |
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Address after: 100192, room 2, building 66, C District, Zhongguancun Dongsheng Science Park, No. 305 Xiao Dong Road, Beijing, Haidian District Co-patentee after: STATE GRID CORPORATION OF CHINA Patentee after: BEIJING SMARTCHIP MICROELECTRONICS TECHNOLOGY Co.,Ltd. Co-patentee after: STATE GRID INFORMATION & TELECOMMUNICATION GROUP Co.,Ltd. Address before: 100192, room 2, building 66, C District, Zhongguancun Dongsheng Science Park, No. 305 Xiao Dong Road, Beijing, Haidian District Co-patentee before: State Grid Corporation of China Patentee before: BEIJING SMARTCHIP MICROELECTRONICS TECHNOLOGY Co.,Ltd. Co-patentee before: STATE GRID INFORMATION & TELECOMMUNICATION GROUP Co.,Ltd. |
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Effective date of registration: 20191118 Address after: 102299 1st floor, building 12, courtyard 79, Shuangying West Road, science and Technology Park, Changping District, Beijing Co-patentee after: STATE GRID CORPORATION OF CHINA Patentee after: Beijing Smart core semiconductor technology Co.,Ltd. Co-patentee after: STATE GRID INFORMATION & TELECOMMUNICATION GROUP Co.,Ltd. Address before: 100192, room 2, building 66, C District, Zhongguancun Dongsheng Science Park, No. 305 Xiao Dong Road, Beijing, Haidian District Co-patentee before: STATE GRID CORPORATION OF CHINA Patentee before: BEIJING SMARTCHIP MICROELECTRONICS TECHNOLOGY Co.,Ltd. Co-patentee before: STATE GRID INFORMATION & TELECOMMUNICATION GROUP Co.,Ltd. |
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