CN106034377A - Selective segment through hole electroplating technology and structure - Google Patents
Selective segment through hole electroplating technology and structure Download PDFInfo
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- CN106034377A CN106034377A CN201510121886.XA CN201510121886A CN106034377A CN 106034377 A CN106034377 A CN 106034377A CN 201510121886 A CN201510121886 A CN 201510121886A CN 106034377 A CN106034377 A CN 106034377A
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Abstract
A selective segment through hole electroplating technology is used to manufacture a circuit board which serves as a separated segment in the same through hole of a selective interconnection internal conducting layer. An electroplating-resistant resist is applied to a conducting layer of an inner core, and peeled off after an electroless electroplating technology. Electroless electroplating peeling-off of the electroplating-resistant resist causes discontinuity of a plating layer in the through hole wall. In the subsequent electroplating process, an internal plugged non-conducting layer cannot be electroplated due to the discontinuity of the plating layer. A generated circuit board structure includes multiple separated interconnected segments in the through hole.
Description
Invention field:
Present invention relates in general to printed circuit board (PCB).More properly, the present invention relates to that there is selectivity section via
The printed circuit board (PCB) of coating.
Background of invention:
Printed circuit board (PCB) (PCB) mechanically supports and uses from leading of being laminated to nonconductive substrate
Conductive trace, pad and other features electrical connection electronic building brick that electricity sheet (such as copper sheet) etches.By stacking and
It is laminated the conducting strip/nonconductive substrate lamination of multiple this etching to form multi-level printed circuit board (PCB).Different layers
On wire and be referred to as via electroplating ventilating hole interconnection.
What Fig. 1 illustrated a part for conventional printed circuit boards cuts out side view.Printed circuit board (PCB) 2 includes many
Individual stack layer, these layers are made up of multiple non-conductive layers 4,6 and multiple conductive layer 8.These non-conductive layers
By being the part of cored structure or can be only the prepreg of core or base material is made.Prepreg be dipping or
It is coated with thermosetting resin adhesive and consolidates and be solidified into the fiber reinforcement of interstage semi-solid products
Material.Prepreg is used as adhesive phase and bonds multiple discrete layers of multi-layer PCB structure, wherein, many
Layer PCB is made up of, including at least one the alternating layer of a plurality of wire being bonded together and multiple basic material
Individual internal electrically conductive layer.Base material is the organic or inorganic material for supporting conductor material pattern.Core is to cover metal
Paper tinsel base material, wherein, this base material has bulk metal conductor material in one or both sides.By being situated between in the middle of stacking
Enter multiple cored structures of prepreg and then this lamination carried out lamination to form laminated stack.Then,
Formed by drilling through this laminated stack and the wall in this hole being electroplated with conductive material (such as copper)
Via 10.These conductive layers 8 are interconnected by produced coating 12.
In exemplary application shown in FIG, coating 12 extends through the whole of via 10 incessantly
Thickness, thus provides the public interconnection with each conductive layer 8.Other apply in, meeting it is desirable that
It is that only some conductive layer carrys out public interconnection by the coating in via.The public interconnection layer section of being referred to as.Section
Formed and need cut-offfing in via wall coating, but, form the electroplating technology of coating typically crossing on hole wall
It is applied to whole wall surface.Therefore, cut-offfing to form required coating, this printed circuit board (PCB) is formed
Single component stack laminated together.Each component lamination lamination has desired plated via, but
When being laminated, the plated via from each component lamination lamination is formed whole via wall coating
The non-conducting material cut-off separate.Fig. 2 illustrate follow-up have to be ready to use in form two of printed circuit board (PCB)
A part for general components lamination cut out side view.Component lamination lamination 20 include multiple non-conductive layer 24,
26 and multiple conductive layer 28.These non-conductive layers 24 and these conductive layers 28 form multiple cored structure, this
A little cored structures are laminated, and wherein non-conductive layer 26 (such as prepreg) is between.By boring
Through this laminated stack and with conductive material, the wall plating in this hole is formed via 22.Produced coating
These conductive layers 28 are interconnected.Form the second component lamination lamination 30 in a similar manner and it includes multiple
The laminated stack of non-conductive layer 34,36 and multiple conductive layers 38 and plated via 32.Complete in order to be formed
Printed circuit board (PCB), stacks two assemblies 20 and 30 so that corresponding via 22 and 32 is directed at, and
It is laminated, and wherein non-conductive layer 40 is between, as shown in Figure 3.Non-conductive layer 40 carries
For the conductive coating of via 22 and cut-offfing in the conductive coating of via 32, thus at the printed circuit of Fig. 3
Plate forms two separate section.
Technique shown in Fig. 2 and Fig. 3 is referred to as generating broaching platen press.Generating broaching platen press has a problem in that and is difficult to
The via making stacked assembly is narrowly focused towards.As shown in Figure 3, of the via 22 in assembly 20
Cross centerline hole 42 to be narrowly focused towards less than a centerline hole 44 excessively with the via 32 in assembly 30.This
It is referred to as layer and to layer misalignment and performance issue can be caused.
In some applications, one or more in the conductive layer that the end face of printed circuit board (PCB) or bottom surface are nearest
Layer is not designed to interconnect with via coating.In order to cut off this connection of the one or more conductive layer,
Perform back drill-through journey, wherein, to printed circuit board (PCB) internal drilling at via.Bore dia is more wider than via diameter,
So that wall coating is disposed in the hole bored, thus remove the interconnection coating between multiple conductive layer.Fig. 4
Illustrate back the conventional printed circuit boards having bored via a part cut out side view.Except to printing
Returning in circuit board 52 has bored beyond hole 64, and printed circuit board (PCB) 52 is similar with the printed circuit board (PCB) 2 in Fig. 1.
Return the 64 several bottoms with printed circuit board (PCB) 52 removing the coating 62 in via 60 of holing and be positioned at identical
The appropriate section of position.Remaining coating 62 is that these conductive layers 58 provide interconnection, but, electric conductivity is
Good bottom 58 ' no longer interconnects with these conductive layers 58, because removing interconnection coating 62 in hole 64.
Making these conductive layers 58 perfect it is essential that return driller's skill, this produces from last interconnection conductive layers
The 58 via stubs (stub) 66 extended out.Via stub be via not with circuit connected in series
The current-carrying part connected.Via stub is the longest, and signaling reflex and degeneration are the biggest.So, it is therefore desirable to
Be intended to minimize the length of via stub.But, conventional driller's skill of returning has high transmutability and is difficult to
Control the length of via stub.It is time-consuming and expensive additionally, return brill.
Summary of the invention:
Multiple embodiments relate to manufacture have that selectivity internal layer connects as in same via separate
The selectivity section via electroplating technology of the circuit board of section.Resistance to platedresist is applied on the conductive layer of inner core
And then peeled off after without electric-type electroplating technology.To on this resistance to platedresist this without electric-type electroplate
Peel off and cause coating discontinuity on hole wall excessively.In following electroplating process, owing to this coating is discontinuous
Property, it is impossible to this connector non-conductive layer is electroplated.Produced board structure of circuit has many in this via
Individual separate electrical interconnection section.This selectivity section via electroplating technology uses single lamination step.
On the one hand, a kind of circuit board is disclosed.This circuit board includes laminated stack, and this laminated stack includes
Multiple non-conductive layers and multiple conductive layer.This laminated stack farther includes interior connector layer.This interior connector layer bag
Include one or more layer of resistance to platedresist.Via is formed through this laminated stack, wherein, except this
Via passes beyond the place at this interior connector layer place, and multiple walls of this via are electroplate with conductive material, thus
Form via wall coating discontinuity.In certain embodiments, each layer in these conductive layers is etched with figure
Case.In certain embodiments, this via includes the overall one borehole through this laminated stack.At some
In embodiment, this via wall coating formed with and multiple electrical interconnections of multiple conductive layers of intersecting of this via, and
And this via wall coating discontinuity makes the first electrical interconnection conduction interval and second conduction interval electricity is electrically interconnected absolutely
Edge.In certain embodiments, these one or more layers of resistance to platedresist are coupled to the conductive layer of this first paragraph
And it is coupled to the conductive layer of this second segment.In certain embodiments, these one or more resistance to platedresists
Layer prevents the formation of a plating stub extended out from this first paragraph.In certain embodiments, this one
Individual or multiple layers of resistance to platedresist prevent the formation of a plating stub extended out from this second segment.
In certain embodiments, this circuit board also includes one or more additional inner sandwich layer in this laminated stack, its
In, each additional inner sandwich layer forms additional via wall coating discontinuity.In certain embodiments, each attached
Add via wall coating discontinuity and produce additional electrical interconnection conductive interval.In certain embodiments, this crosses hole wall
Coating discontinuity is directed at these one or more layers of resistance to platedresist.In certain embodiments, this circuit
Plate also includes the cavity extended out in this via from this interior connector layer.In certain embodiments, this is interior
Connector layer include connector non-conductive layer, be coupled to this connector non-conductive layer first surface the first resistance to plating resist
Second layer of resistance to platedresist of the second surface losing oxidant layer and be coupled to this connector non-conductive layer.
On the other hand, another kind of circuit board is disclosed.This circuit board includes laminated stack, is formed to wear
The via crossing this laminated stack and the cavity extended out from this via.This laminated stack includes multiple non-conductive
Layer and multiple conductive layers, wherein, this laminated stack farther includes interior connector layer, and this interior connector layer includes one
Individual or multiple layers of resistance to platedresist.In addition to the place that this via passes this interior connector layer place, this mistake
Multiple walls in hole are electroplate with conductive material.This cavity extends out from this via of this interior connector layer, wherein,
This cavity forms via wall coating discontinuity.This via wall coating formed with and multiple leading of intersecting of this via
Multiple electrical interconnections of electric layer, and this via wall coating discontinuity make first electrical interconnection conduction interval and second
Conduction interval electric insulation is electrically interconnected.In certain embodiments, each layer in these conductive layers is etched with pattern.
In certain embodiments, this via includes the overall one borehole through this laminated stack.Implement at some
In example, these one or more layers of resistance to platedresist be coupled to the conductive layer of this first paragraph and be coupled to this
The conductive layer of two-stage nitration.In certain embodiments, these one or more layers of resistance to platedresist prevent one from this
The formation of the plating stub that first paragraph extends out.In certain embodiments, these one or more resistance to plating
Resist layer prevents the formation of a plating stub extended out from this second segment.In some embodiment
In, this circuit board also includes one or more additional inner sandwich layer in this laminated stack, wherein, each additional
Inner sandwich layer forms additional via wall coating discontinuity.In certain embodiments, each additional via wall coating
Discontinuity produces additional electrical interconnection conductive interval.In certain embodiments, this via wall coating discontinuity
It is directed at these one or more layers of resistance to platedresist.In certain embodiments, this interior connector layer includes connector
Non-conductive layer, it is coupled to the first layer of resistance to platedresist of the first surface of this connector non-conductive layer and is coupled to
Second layer of resistance to platedresist of the second surface of this connector non-conductive layer.
In yet other aspects, disclose a kind of Multi-network.This Multi-network includes circuit board
With the pin in the via being inserted in this circuit board.This circuit board includes laminated stack and this via.This laminated stack
Including multiple non-conductive layers and multiple conductive layer, wherein, this laminated stack farther includes interior connector layer, should
Interior connector layer includes one or more layer of resistance to platedresist.This via is formed through this laminated stack.
In addition to the place that this via passes this interior connector layer place, multiple walls of this via are electroplate with conduction material
Material, is consequently formed via wall coating discontinuity.This via wall coating formed with and this via intersect multiple
Multiple electrical interconnections of conductive layer, and this via wall coating discontinuity makes the first electrical interconnection conduction interval and the
Two are electrically interconnected conduction interval electric insulation.Be coupled in these first and second sections each section of this pin galvanic couple with provide from
In these first and second sections each section connects to the independent electrical of this pin.
In terms of yet still another, disclose a kind of method manufacturing circuit board.The method includes forming lamination
Lamination.This laminated stack includes multiple non-conductive layer, multiple conductive layer and interior connector layer, and wherein, this is interior
Connector layer includes one or more layer of resistance to platedresist.The method also includes being formed through this laminated stack
Via.This via pass these one or more layers of resistance to platedresist so that cross hole wall with this
Or the corresponding some of the multiple layer of resistance to platedresist includes resistance to platedresist.The method also includes stripping
It is exposed to the some away from this via from these one or more layers of resistance to platedresist.The method also includes
Perform, without electric-type electroplating technology, this is crossed hole wall to electroplate, so that the some of this coating is formed
In those parts including resistance to platedresist that this crosses hole wall.The method also includes the shape peeling off this coating
Become those parts in those parts including resistance to platedresist that this crosses hole wall and peel off this
Or these parts of the multiple layer of resistance to platedresist with these the one or more resistance to electricity in this laminated stack
Multiple via wall coating discontinuity is formed on this second mistake hole wall that plating resist layer coincides.The method is also
Including performing electroplating technology with electroplating at this remainder crossed on hole wall this coating further
Keep these via wall coating discontinuities simultaneously.In certain embodiments, this interior connector layer includes that connector is non-
Conductive layer, it is coupled to the first layer of resistance to platedresist of the first surface of this connector non-conductive layer and is coupled to this
Second layer of resistance to platedresist of the second surface of connector non-conductive layer.In certain embodiments, this electricity is performed
Depositing process makes the part dissolving on this connector non-conductive layer of this coating, thus across this whole interior connector layer
Form continuous via wall coating discontinuity.In certain embodiments, peel off these parts of this coating and shell
From these parts of this first layer of resistance to platedresist and this second layer of resistance to platedresist so that since this mistake
Multiple respective cavities that hole extends out initially form these via wall coating discontinuities, and wherein, first is empty
Chamber is directed at this first layer of resistance to platedresist and this second resistance to electricity in the second cavity and this laminated stack
Plating resist layer alignment.In certain embodiments, the multiple of these one or more layers of resistance to platedresist are peeled off
Partly form the cavity extended out from this via.
In certain embodiments, forming this laminated stack and include forming the first assembly, this first assembly includes
One non-conductive layer, be coupled to the first surface of this first non-conductive layer the first conductive layer, be coupled to this first
Second conductive layer of the second surface of non-conductive layer and be coupled to the first resistance to plating of this second conductive layer and resist
Erosion oxidant layer.Forming this laminated stack can also include forming the second assembly, this second assembly includes that second non-leads
Electric layer, be coupled to the 3rd conductive layer of the first surface of this second non-conductive layer, to be coupled to this second non-conductive
4th conductive layer of the second surface of layer and be coupled to the second resistance to platedresist of the 3rd conductive layer
Layer.Form this laminated stack and can also include in this first stack of components to this second assembly, so that
This first resistance to platedresist aspect is to this second layer of resistance to platedresist.Form this laminated stack can also wrap
Include and at least one additional non-conductive layer and additional conductive layer are stacked to this of this first assembly first lead
In electric layer and be stacked on the 4th conductive layer of this second assembly, it is consequently formed lamination.Form this lamination
Lamination can also include being laminated to form this laminated stack to this lamination.In certain embodiments, should
First stack of components includes positioning in-between non-conductive layer on this second assembly.
In certain embodiments, the method also includes these Conductive Layer Etch patterns in this laminated stack.
In certain embodiments, this via wall coating formed with and multiple electricity of multiple conductive layers of intersecting of this via mutual
Connect, and multiple second via wall coating discontinuity makes the first electrical interconnection conduction interval and the second electrical interconnection lead
Electric layer section electric insulation.In certain embodiments, perform this electroplating technology include to this first paragraph and to this second
Section executes electricity.In certain embodiments, this first layer of resistance to platedresist prevents one to extend from this first paragraph
The formation of the plating stub come.In certain embodiments, this second layer of resistance to platedresist prevent one from
The formation of the plating stub that this second segment extends out.In certain embodiments, form this laminated stack to enter
One step includes one or more additional inner sandwich layer, wherein, each additional inner sandwich layer in being included in this laminated stack
Form multiple additional via wall coating discontinuity.In certain embodiments, each additional inner sandwich layer produces attached
Power up interconnection conductive interval.In certain embodiments, form this via to include getting out through this laminated stack
Overall one borehole.
Accompanying drawing briefly describes
Some example embodiment have been described with reference to the drawings, and wherein, identical assembly is equipped with identical reference mark
Number.These example embodiment are intended to explanation and are not intended to the present invention.These accompanying drawings include with figure below:
What Fig. 1 illustrated a part for conventional printed circuit boards cuts out side view.
Fig. 2 illustrates a part for follow-up two the general components laminations having and being ready to use in formation printed circuit board (PCB)
Cut out side view.
Fig. 3 illustrates the generating broaching platen press of two component stack in Fig. 2.
What Fig. 4 illustrated back a part for the conventional printed circuit boards having bored via cuts out side view.
What Fig. 5 illustrated a part for the printed circuit board (PCB) according to embodiment cuts out side view.
Fig. 6 to Figure 12 illustrates the selectivity section via galvanizer for manufacturing the printed circuit board (PCB) in Fig. 5
Each step in skill.
What Figure 13 illustrated a part for the printed circuit board (PCB) according to another embodiment cuts out side view.
What Figure 14 illustrated a part for the printed circuit board (PCB) according to still another embodiment cuts out side view.
Figure 15 illustrates substituting lamination step.
Figure 16 illustrates the example print circuit board that the lamination step of Figure 15 produces.
The detailed description of embodiment:
Embodiments herein relates to a kind of printed circuit board (PCB).It will be understood by those skilled in the art that printing
Described in detail below being merely illustrative of circuit board and be not intended to limit by any way.Have and originally drape over one's shoulders
Such technical staff of the rights and interests of dew will readily occur other embodiments of this printed circuit board (PCB).
Now with detailed reference to the implementation of the printed circuit board (PCB) as shown in accompanying drawing.Run through accompanying drawing and with
Lower detailed description, identical reference designator will be used for referring to same or analogous part.For clear purpose,
The general characteristics of implementation described here is not all illustrated and is described.It will, of course, be understood that
In the development of any this actual implementation, it is necessary to make many implementations and specifically determine to realize
The specific objective of developer, as to and application and business relevant restrictive condition compatibility, and it will be recognized that
These specific objectives will be because of implementation and different because of developer.Moreover, it will be recognized that such exploitation work
Making may be complicated and time-consuming, but but for having the technical staff of rights and interests of present disclosure in this area will be
Conventional project task.
What Fig. 5 illustrated a part for the printed circuit board (PCB) according to embodiment cuts out side view.Use selectivity
Section via electroplating technology manufactures printed circuit board (PCB) 102, describes embodiment about Fig. 6 to Figure 12.Printing
Circuit board 102 includes multiple stack layer, and these layers are by multiple non-conductive layers 104,106 and multiple conductive layer
108 make.These non-conductive layers can be by the prepreg of a part or the base being cored structure or bullet assembly
Material is made.Cored structure includes one or two apparent surface of non-conductive layer (such as base material), this non-conductive layer
On figuratum conductive layer.By forming connector group to the surface applied layer of resistance to platedresist of cored structure
Part.Interpolation is formed by being positioned adjacent to two bullet assemblies each with the layer of resistance to platedresist 118
Plug layer 140.In exemplary configuration shown in Figure 5, non-conductive layer 106 between is (as half is solid
Change sheet) it is positioned between two layers of resistance to platedresist 118.By stacking in the middle of get involved non-conducting material (as
Prepreg) multiple plug structures and cored structure and then this lamination is carried out lamination and carry out cambium layer laminated
Layer.Any Conventional laminating techniques can be used.Exemplary laminated stack shown in Fig. 5 has two connectors
Assembly.It will be appreciated that, this laminated stack can be made into be had more or less than two bullet assemblies.Figure
Exemplary laminated stack shown in 5 does not include the multiple cores not the most being formed in multiple bullet assembly
Structure.It will be appreciated that, this laminated stack can be made into include one or more be not the most formed into many
Cored structure in individual bullet assembly.By drilling through this laminated stack and right with conductive material (such as copper)
The wall in this hole carries out plating to form via 110.Produced coating 112 is by multiple selective conductivity layers 108
Interconnection.Interior connector layer 140 is selectively positioned into for by printed circuit board (PCB) in laminated stack forming process
102 sections of being divided into 120 and 130.Connector 140 is included in electroplating process prevention cavity 115 and region 114
The resistance to platedresist 118 of middle formation coating 112.As a result of which it is, the coating 112 in section 120 and section 130
In coating 112 disconnect.This causes via 110 to have the section 120 and 130 of two electric insulations.Section also may be used
To be referred to as net, it is electronic circuit.Each section of offer is connected with the independent electrical of the pin being inserted in this via.
So, the printed circuit board (PCB) with multiple sections is many web frames.
In the present embodiment, two layers of resistance to platedresist 118 selectivity location substantially eliminate from from
The formation of a plurality of plating stub that nearest these conductive layers 108 of these cavitys 115 extend out.At certain
In a little embodiments, the flash plating being deposited in the exposure of the conductive layer 108 in cavity 115 stays.
Position in the laminated stack that the quantity of the layer in PCB 102 and connector 140 are shown in Figure 5 is only
For example purposes.This selectivity section via electroplating technology allows freely by each continuous print inner conductive
Layer is as separate section of interconnection in same via.In exemplary configuration shown in Figure 5, the three of top
It is a section that individual conductive layer is interconnected into, and three conductive layers of bottom are interconnected into as another section.Should
It is understood that the not all section of interconnection conductive layers being required for there is equal number.It is also believed that section is permissible
Have more or less than three interconnection conductive sections.In exemplary configuration shown in Figure 5, single connector 140
It is dispersed in printed circuit board (PCB) 102.Alternately, multiple this connectors can be dispersed in printed circuit board (PCB).
The multiple extra segments of formation are caused including multiple addition plug.
Fig. 6 to Figure 12 illustrates the selectivity section via electricity for manufacturing the printed circuit board (PCB) 102 in Fig. 5
Each step in depositing process.Every figure in Fig. 6 to Figure 12 illustrates stub according to each processing step
Printed circuit board (PCB) cut out side view.In figure 6, bullet assembly 122 is formed.Bullet assembly 122 includes
Cored structure and the layer of resistance to platedresist 118 being formed on the surface of this cored structure.This cored structure is to cover metal
Paper tinsel base material, including the nonconductive matrix sheet material layers 104 being formed on two apparent surfaces and multiple conductive layer 108.
It will be appreciated that, it is possible to use on a surface of this non-conductive layer, only include the substituting core knot of conductive layer
Structure.The layer of resistance to platedresist 118 (as liquid can photosensitive resistance to platedresist) is applied in these conductive layers
On one of 108.It will be appreciated that, it is possible to use withstand follow-up and cross the other kinds of resistance to of hole wall plating step
Platedresist.Manufacture one or more addition plug assembly in a similar manner.Use two bullet assembly systems
Make each inner sandwich layer.So, the quantity of manufactured bullet assembly depends on having including in laminated stack
The quantity of inner sandwich layer.In the exemplary embodiment of Fig. 5, single inner sandwich layer is included in this laminated stack,
And so, manufacture two bullet assemblies.Alternatively, have at printed circuit board (PCB) and to be included be not the most formed
In the case of one or more cored structures in multiple bullet assemblies, can this stage manufacture this or
Multiple cored structures.
In the figure 7, laminated stack is formed.Bullet assembly 122 is in turn laminated to another bullet assembly 122 '
On, wherein non-conductive layer 106 is between.Bullet assembly 122 and bullet assembly 122 ' are oriented such that
The respective layer of resistance to platedresist 118 face each other of each assembly, as shown in Figure 7.Institute in the figure 7
In the exemplary configuration shown, multiple additional conductive layer 108 and multiple non-conductive layer 106 between are added
It is added to top and the bottom of this lamination.Single lamination step produces the laminated stack shown in Fig. 7.This lamination
These additional conductive layer 108 on the top of lamination and bottom are etched with pattern.
In fig. 8, drilling bore hole passes the laminated stack of Fig. 7 to form via 110.The formation of via 110
Make resistance to platedresist 118 be exposed to via 110 sidewall on.
At Fig. 9, perform the first stripping technology of resistance to platedresist.Work is peeled off at this first resistance to platedresist
During skill, remove a part for resistance to platedresist 118.Another part of resistance to platedresist 118 exists
It is left after this resistance to platedresist strip step.The part peeling off resistance to platedresist resists in these resistance to plating
Each layer in erosion oxidant layer 118 is in via 110 surrounding and forms cavity 115.
At Figure 10, perform desmearing process and remove the residue in via 110.It follows that perform without electricity
Formula electroplating technology is to form coating 112 ' on the sidewall of via 110.In certain embodiments, copper is used as
Coating material.It will be appreciated that, it is possible to use other coating materials.Coating 112 ' is formed and each conductive layer 108
Interconnection.In the region of connector 140, coating 112 ' is formed at the resistance to platedresist 118 in cavity 115
And on the connector non-conductive layer 106 exposed between two layers of resistance to platedresist 118.
At Figure 11, perform the second stripping technology of resistance to platedresist.Work is peeled off at this second resistance to platedresist
During skill, remove another portion being attached to the layer of resistance to platedresist 118 and the material of resistance to platedresist 118
Two coating 112 ' on Fen, thus further expand these cavitys 115.Galvanizer without electric-type at Figure 10
During skill, the coating 112 ' of deposition deposits on resistance to platedresist 118 the most well, and the most resistance to
Platedresist 118 is covered by coating 112 ' the most completely.Further, coating 112 ' and resistance to platedresist 118
Between cohesive force do not have the cohesive force between coating 112 ' and other layers being exposed in via strong.So,
During this stripping technology of resistance to platedresist, peel off chemical process and lacking the position that coating 112 ' covers
Attack resistance to platedresist 118.Along with resistance to platedresist 118 dissolves, sink without to coating 112 '
Amass the support of part on resistance to platedresist 118, and remove this part of coating 112 '.Residual
Resistance to platedresist 118 amount remaining after this second resistance to platedresist strip step.
In fig. 12, perform electroplating technology, thus on the sidewall of via 110, produce thicker coating 112.
In certain embodiments, copper is used as coating material.In order to perform this electroplating technology, to section 120 and 130
Execute electricity.But, due to the via wall coating discontinuity at the layer of resistance to platedresist 118, it is attached to two
Coating 112 ' not electrical connection on connector non-conductive layer 106 between the layer of resistance to platedresist 118.So,
In this electroplating process, the electroplating chemical process of application makes this coating 112 ' dissolve.This coating 112 ' molten
Solution forms cavity 114 for coating 112, and this cavity is formed in via 110, thus across whole
Interior connector layer 140 causes via wall coating discontinuity.
In certain embodiments, this connector is positioned in the place in addition to the centre of this laminated stack.Figure
13 parts illustrating the printed circuit board (PCB) according to another embodiment cut out side view.Printed circuit board (PCB)
202 include multiple stack layer, and these layers are by the multiple non-conductive layers being laminated in another on connector layer 240
204,206 make with multiple conductive layers 208 in case by with before described similar in the way of formed with having
The laminated stack of the via 210 of coating 212.Can be with the side similar with the connector 140 in Fig. 6 to Fig. 8
Formula forms interior connector layer 240.In produced, connector layer 240 includes cavity 214 and 215, these cavitys
Continuous via wall coating discontinuity is formed across whole inner sandwich layer 240.
Figure 13 also illustrates additional functional, and wherein, this interior connector layer is selectively positioned to towards electricity
" back side " of road plate, thus by with return bore similar in the way of effectively make the leading of quantity of selection at the back side
Electric layer (such as, section 230) and section 220 electric insulation.But, at this selectivity section via electroplating technology
In the case of, not such as the conventional a plurality of via stub returning and being had in driller's skill.
In the embodiment above, during single inner sandwich layer is included in this laminated stack.In other embodiments, should
Laminated stack can include multiple inner sandwich layer.Figure 14 illustrates the printed circuit according to still another embodiment
A part for plate cut out side view.Printed circuit board (PCB) 302 includes two inner sandwich layers 340 and 360.Permissible
These inner sandwich layers are made, as by by two connector groups by the mode similar with that described before mode
Part is laminated together.In exemplary embodiment shown in fig. 14, with the bullet assembly 122 in Fig. 6
The single layer of resistance to platedresist be contrasted, this bullet assembly can be manufactured into the layer of resistance to platedresist
It is applied on each conductive layer of this cored structure.This connector on the opposite sides with the layer of resistance to platedresist
Assembly is the basis of the section 350 shown in Figure 14.Then, two types are similar with bullet assembly 122
Connector can with the two-sided bullet assembly of resistance to platedresist be stacked with formed in connector layer 340 and
360.The extra play being made up of multiple non-conductive layers 304,306 and multiple conductive layer 308 is stacked to interpolation
On plug layer 340 and 360, and it is laminated to form laminated stack to produced lamination.Then, right
This laminated stack carries out holing to form via 310.First is performed resistance in the mode that mode above-mentioned is similar
Platedresist strip step, without electric-type plating step, the second resistance to platedresist strip step and plating step
Suddenly.In produced, connector layer 340 and 360 each includes multiple layer of resistance to platedresist 318 and across whole
Inner sandwich layer forms the cavity 314 and 315 of via wall coating discontinuity.Along with adding this second inner sandwich layer,
Form extra segment 350.
In the embodiment above, by two bullet assemblies, (wherein non-conductive layer is positioned at each bullet assembly
The respective layer of resistance to platedresist between) carry out lamination to form inner sandwich layer.Alternately, can be by this
Two bullet assemblies are laminated together and do not make non-conductive layer between the respective resistance to plating of each bullet assembly
In the middle of resist layer.Figure 15 illustrates substituting lamination step.Use two bullet assemblies 422 and 422 '
Manufacture this laminated stack, the most each respective layer of resistance to platedresist of bullet assembly 422 and 422 ' 418 with
The connector non-conductive layer being eliminated in the part of the position of the layer of resistance to platedresist 118 is laminated together with shape
Become the basis of connector 440.Figure 16 illustrates the example print circuit board that the lamination step of Figure 15 produces
402。
It will be appreciated that, according to application-specific and application requirement, the connector shown in the embodiment of Fig. 6 to Figure 16
Each structure configuration and position can exchange.
This selectivity section via electroplating technology allows freely to connect separate as in same via of internal layer
Section.This selectivity section via electroplating technology can substitute for back boring and generating broaching platen press, realizes and both simultaneously
The design that technique is identical.Which save operating cost and shorten PCB process time.Brill is returned with routine
In technique, uncontrollable stub lengths compares, and this selectivity section via electroplating technology substantially eliminates
Electroplate stub and therefore improve signal transmission integrity.Coating stub be via not with circuit string
The current-carrying part that connection connects.By substantially eliminating plating stub, when signal is advanced along via, can
To minimize signaling reflex and degeneration.When the physics size of drill bit needs the spacing increasing adjacent borehole, return
The elimination boring step also saving the disabled real estate on printed circuit board (PCB).Compared with generating broaching platen press,
This selectivity section via electroplating technology needs single assembling lamination, and this give through printed circuit board (PCB) is whole
The via alignment that thickness is lucky, this provides the most overall layer and to layer registration and therefore carries for wiring
Supply more space.This selectivity section via electroplating technology also supports disposable drill process.
The specific embodiment the most just combining details describes the application to help to understand that attaching is multiple
The structure of the flexible print wiring of stiff member and operating principle.Being permitted shown in each figure and in the assembly of description
Multicompartment can exchange with realize needed for result, and this specification should be read into also include this mutually
Change.So, at this, specific embodiment and details thereof are quoted the model being not intended to limit appended claims
Enclose.For a person skilled in the art it will be apparent that without departing from spirit and scope
In the case of can be selected for explanation embodiment make amendment.
Claims (38)
1. a circuit board, including:
A. laminated stack, this laminated stack includes multiple non-conductive layer and multiple conductive layer, wherein, this layer
Laminated layer farther includes interior connector layer, and this interior connector layer includes one or more layer of resistance to platedresist；With
And
B. the via of this laminated stack it is formed through, wherein, except this via is through this interior connector layer
Beyond the place at place, multiple walls of this via are electroplate with conductive material, are consequently formed via wall coating and do not connect
Continuous property.
2. circuit board as claimed in claim 1, wherein, each Conductive Layer Etch in these conductive layers has figure
Case.
3. circuit board as claimed in claim 1, wherein, this via includes the entirety through this laminated stack
One borehole.
4. circuit board as claimed in claim 1, wherein, this via wall coating formed with and this via intersect
Multiple electrical interconnections of multiple conductive layers, and this via wall coating discontinuity make first electrical interconnection conduction interval
Conduction interval electric insulation is electrically interconnected with second.
5. circuit board as claimed in claim 4, wherein, these one or more layers of resistance to platedresist are coupled to
The conductive layer of this first paragraph and be coupled to the conductive layer of this second segment.
6. circuit board as claimed in claim 5, wherein, these one or more layers of resistance to platedresist prevent one
The formation of the plating stub that bar extends out from this first paragraph.
7. circuit board as claimed in claim 6, wherein, these one or more layers of resistance to platedresist prevent one
The formation of the plating stub that bar extends out from this second segment.
8. circuit board as claimed in claim 4, includes one or more additional inner sandwich layer in this laminated stack,
Wherein, each additional inner sandwich layer forms additional via wall coating discontinuity.
9. circuit board as claimed in claim 8, wherein, each additional via wall coating discontinuity produces attached
Power up interconnection conductive interval.
10. circuit board as claimed in claim 1, wherein, this via wall coating discontinuity and this or many
The individual layer of resistance to platedresist is directed at.
11. circuit boards as claimed in claim 1, farther include to extend in this via from this interior connector layer
Cavity out.
12. circuit boards as claimed in claim 1, wherein, this interior connector layer includes connector non-conductive layer, coupling
To first layer of resistance to platedresist of first surface of this connector non-conductive layer with to be coupled to this connector non-conductive
Second layer of resistance to platedresist of the second surface of layer.
13. 1 kinds of circuit boards, including:
A. laminated stack, this laminated stack includes multiple non-conductive layer and multiple conductive layer, wherein, this layer
Laminated layer farther includes interior connector layer, and this interior connector layer includes one or more layer of resistance to platedresist；
B. the via of this laminated stack it is formed through, wherein, except this via is through this interior connector layer
Beyond the place at place, multiple walls of this via are electroplate with conductive material；And
C. the cavity extended out in this via from this interior connector layer, wherein this cavity formed hole wall
Coating discontinuity, wherein, this via wall coating formed with and multiple conductions of intersecting of this via
Multiple electrical interconnections of layer, and this via wall coating discontinuity makes the first electrical interconnection conduction interval electric with second
Interconnection conductive interval electric insulation.
14. circuit boards as claimed in claim 13, wherein, each Conductive Layer Etch in these conductive layers has
Pattern.
15. circuit boards as claimed in claim 13, wherein, this via includes the entirety through this laminated stack
One borehole.
16. circuit boards as claimed in claim 13, wherein, these the one or more layer of resistance to platedresist couplings
To the conductive layer of this first paragraph and be coupled to the conductive layer of this second segment.
17. circuit boards as claimed in claim 16, wherein, these one or more layers of resistance to platedresist prevent
Article one, the formation of the plating stub extended out from this first paragraph.
18. circuit boards as claimed in claim 17, wherein, these one or more layers of resistance to platedresist prevent
Article one, the formation of the plating stub extended out from this second segment.
19. circuit boards as claimed in claim 13, include one or more additional inner core in this laminated stack
Layer, wherein, each additional inner sandwich layer forms additional via wall coating discontinuity.
20. circuit boards as claimed in claim 19, wherein, each additional via wall coating discontinuity produces
Additional electrical interconnection conductive interval.
21. circuit boards as claimed in claim 13, wherein, this via wall coating discontinuity with this or
Multiple layers of resistance to platedresist are directed at.
22. circuit boards as claimed in claim 13, wherein, this interior connector layer includes connector non-conductive layer, idol
It is coupled to first layer of resistance to platedresist of first surface of this connector non-conductive layer and is coupled to that this connector is non-leads
Second layer of resistance to platedresist of the second surface of electric layer.
23. 1 kinds of Multi-networks, including:
A. circuit board, this circuit board includes:
I. laminated stack, this laminated stack includes multiple non-conductive layer and multiple conductive layer, wherein,
This laminated stack farther includes interior connector layer, and this interior connector layer includes one or more resistance to platedresist
Layer；And
Ii. the via of this laminated stack it is formed through, wherein, except this via is through this interpolation
Beyond the place at plug layer place, multiple walls of this via are electroplate with conductive material, are consequently formed via wall coating
Discontinuity, wherein, this via wall coating formed with and this via multiple conductive layers of intersecting
Multiple electrical interconnections, and this via wall coating discontinuity make first electrical interconnection conduction interval with second electrical interconnection
Conduction interval electric insulation；And
B. being inserted in the pin in this via, wherein, this pin galvanic couple is coupled to each section in these first and second sections
To provide each section of independent electrical to this pin from these first and second sections to connect.
24. 1 kinds of methods manufacturing circuit board, the method includes:
A. form laminated stack, wherein, this laminated stack include multiple non-conductive layer, multiple conductive layer with
And interior connector layer, wherein, this interior connector layer includes one or more layer of resistance to platedresist；
B. forming the via through this laminated stack, wherein, this via passes these one or more resistance to plating
Resist layer, so that cross the multiple portions corresponding with these one or more layers of resistance to platedresist of hole wall
Divide and include resistance to platedresist；
That c. peels off these one or more layers of resistance to platedresist is exposed to the some at this via；
C. perform, without electric-type electroplating technology, this is crossed hole wall to electroplate, so that this coating is multiple
Part is formed in these those parts including resistance to platedresist crossing hole wall；
D. being formed in these those parts including resistance to platedresist crossing hole wall of this coating is peeled off
Those parts and peel off these parts of this one or more layers of resistance to platedresist to fold with this lamination
Multiple via is formed on this second mistake hole wall that these one or more layers of resistance to platedresist in Ceng coincide
Wall coating discontinuity；And
E. electroplating technology is performed with crossing the remainder on hole wall carry out electricity at this this coating further
These via wall coating discontinuities are kept while plating.
25. methods as claimed in claim 24, wherein, this interior connector layer includes connector non-conductive layer, coupling
To first layer of resistance to platedresist of first surface of this connector non-conductive layer with to be coupled to this connector non-conductive
Second layer of resistance to platedresist of the second surface of layer.
26. methods as claimed in claim 25, wherein, perform this electroplating technology make this coating at this connector
Part dissolving on non-conductive layer, thus forms continuous via wall coating across this whole interior connector layer discontinuous
Property.
27. methods as claimed in claim 25, wherein, peel off these parts of this coating and peel off this first
These parts of the layer of resistance to platedresist and this second layer of resistance to platedresist are so that since this via extends
The multiple respective cavities come initially form these via wall coating discontinuities, wherein, the first cavity with this
This second resistance to platedresist in one layer of resistance to platedresist alignment and the second cavity and this laminated stack
Layer alignment.
28. methods as claimed in claim 24, wherein, peel off these one or more layers of resistance to platedresist
Some forms the cavity extended out from this via.
29. methods as claimed in claim 24, wherein, form this laminated stack and include:
A. forming the first assembly, this first assembly includes the first non-conductive layer, to be coupled to this first non-conductive
Layer first surface the first conductive layer, be coupled to this first non-conductive layer second surface second conduction
Layer and be coupled to the first layer of resistance to platedresist of this second conductive layer；
B. forming the second assembly, this second assembly includes the second non-conductive layer, to be coupled to this second non-conductive
3rd conductive layer of the first surface of layer, it is coupled to the 4th conduction of the second surface of this second non-conductive layer
Layer and be coupled to the second layer of resistance to platedresist of the 3rd conductive layer；
C. by this first stack of components to this second assembly, so that this first layer of resistance to platedresist
Towards this second layer of resistance to platedresist；
D. at least one additional non-conductive layer and an additional conductive layer are stacked to being somebody's turn to do of this first assembly
On first conductive layer and be stacked on the 4th conductive layer of this second assembly, it is consequently formed lamination；And
E. it is laminated to form this laminated stack to this lamination.
30. methods as claimed in claim 29, wherein, will wrap in this first stack of components to this second assembly
Include and non-conductive layer is positioned in-between.
31. methods as claimed in claim 24, farther include to lose these conductive layers in this laminated stack
Needle drawing case.
32. method as claimed in claim 24, wherein, this second via wall coating formed with and this via phase
The multiple electrical interconnections of multiple conductive layers handed over, and multiple second via wall coating discontinuity makes the first electricity mutually
Even conduction interval and second is electrically interconnected conduction interval electric insulation.
33. methods as claimed in claim 32, wherein, perform this electroplating technology and include this first paragraph and right
This second segment executes electricity.
34. methods as claimed in claim 32, wherein, this first layer of resistance to platedresist prevents one from this
The formation of the plating stub that first paragraph extends out.
35. methods as claimed in claim 34, wherein, this second layer of resistance to platedresist prevents one from this
The formation of the plating stub that second segment extends out.
36. methods as claimed in claim 32, wherein, form this laminated stack and further include at this lamination
Including one or more additional inner sandwich layer in lamination, wherein, each additional inner sandwich layer forms multiple additional via
Wall coating discontinuity.
37. methods as claimed in claim 36, wherein, each additional inner sandwich layer produces additional electrical interconnection conductive
Interval.
38. methods as claimed in claim 24, wherein, form this via and include getting out one borehole through being somebody's turn to do
The entirety of laminated stack.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510121886.XA CN106034377B (en) | 2015-03-19 | 2015-03-19 | Selective segment via plating process and structure |
| US14/834,205 US9867290B2 (en) | 2015-03-19 | 2015-08-24 | Selective segment via plating process and structure |
| US14/834,180 US9763327B2 (en) | 2015-03-19 | 2015-08-24 | Selective segment via plating process and structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510121886.XA CN106034377B (en) | 2015-03-19 | 2015-03-19 | Selective segment via plating process and structure |
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| CN106034377B CN106034377B (en) | 2020-06-16 |
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| CN106982522A (en) * | 2017-03-14 | 2017-07-25 | 开平依利安达电子第三有限公司 | Multi net voting through hole circuit board and its manufacture method |
| CN108738379A (en) * | 2017-02-22 | 2018-11-02 | 华为技术有限公司 | The forming method of plated through-hole, the manufacturing method of circuit board and circuit board |
| CN108901146A (en) * | 2018-08-10 | 2018-11-27 | 重庆方正高密电子有限公司 | Circuit board and its selective electroplating technique, manufacture craft |
| CN109379859A (en) * | 2018-10-10 | 2019-02-22 | 广州添利电子科技有限公司 | The residual copper stake manufacture craft of back drill zero in PCB substrate |
| CN109862704A (en) * | 2019-04-02 | 2019-06-07 | 生益电子股份有限公司 | A kind of PCB production method and PCB containing buried via hole |
| CN109862718A (en) * | 2019-04-02 | 2019-06-07 | 生益电子股份有限公司 | A kind of method for processing through hole and PCB that hole wall layers of copper is disconnected in designated layer |
| CN109862719A (en) * | 2019-04-02 | 2019-06-07 | 生益电子股份有限公司 | A kind of PCB production method that realizing a hole Multi net voting and PCB |
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| CN110996526A (en) * | 2019-12-27 | 2020-04-10 | 生益电子股份有限公司 | Method for manufacturing signal via hole |
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| CN108738379A (en) * | 2017-02-22 | 2018-11-02 | 华为技术有限公司 | The forming method of plated through-hole, the manufacturing method of circuit board and circuit board |
| CN108738379B (en) * | 2017-02-22 | 2020-02-21 | 华为技术有限公司 | Metallized hole forming method, circuit board manufacturing method and circuit board |
| CN106982522A (en) * | 2017-03-14 | 2017-07-25 | 开平依利安达电子第三有限公司 | Multi net voting through hole circuit board and its manufacture method |
| CN108901146A (en) * | 2018-08-10 | 2018-11-27 | 重庆方正高密电子有限公司 | Circuit board and its selective electroplating technique, manufacture craft |
| CN109379859A (en) * | 2018-10-10 | 2019-02-22 | 广州添利电子科技有限公司 | The residual copper stake manufacture craft of back drill zero in PCB substrate |
| CN109862719A (en) * | 2019-04-02 | 2019-06-07 | 生益电子股份有限公司 | A kind of PCB production method that realizing a hole Multi net voting and PCB |
| CN109862718A (en) * | 2019-04-02 | 2019-06-07 | 生益电子股份有限公司 | A kind of method for processing through hole and PCB that hole wall layers of copper is disconnected in designated layer |
| CN109890149A (en) * | 2019-04-02 | 2019-06-14 | 生益电子股份有限公司 | A kind of production method and PCB of two-sided crimping PCB |
| CN109862704A (en) * | 2019-04-02 | 2019-06-07 | 生益电子股份有限公司 | A kind of PCB production method and PCB containing buried via hole |
| CN109862719B (en) * | 2019-04-02 | 2022-04-29 | 生益电子股份有限公司 | PCB manufacturing method for realizing one-hole multi-network and PCB |
| CN109890149B (en) * | 2019-04-02 | 2022-04-29 | 生益电子股份有限公司 | Manufacturing method of double-sided compression-joint PCB and PCB |
| CN110996526A (en) * | 2019-12-27 | 2020-04-10 | 生益电子股份有限公司 | Method for manufacturing signal via hole |
| CN110996526B (en) * | 2019-12-27 | 2020-11-03 | 生益电子股份有限公司 | Method for manufacturing signal via hole |
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